PDID

REGWRPROT

BODCR

TEMPCR

PORCR

GPA_MFP

GPB_MFP

GPC_MFP

GPD_MFP

RSTSRC

GPE_MFP

ALT_MFP

IPRSTC1

IPRSTC2

PDID : Part Device Identification Number This register reflects device part number code. S/W can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only

REGPROTDIS : Register Write Protection Disable Index (Read only) 1 = Write-Protection is disabled for writing protected registers 0 = Write-Protection is enabled for writing protected registers. Any write to the protected register is ignored. The Protected registers are: IPRST1: address 0x5000_0008 BODCR: address 0x5000_0018 PORCR: address 0x5000_0024 PWRCON: address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear) APBCLK bit[0]: address 0x5000_0208 (bit[0] is watchdog timer clock enable) CLK_SEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source select) CLK_SEL1 bit[1:0]: address 0x5000_0214 (for watch dog clock source select) ISPCON: address 0x5000_C000 (Flash ISP Control register) WTCR: address 0x4000_4000 FATCON: address 0x5000_C018
bits : 0 - 0 (1 bit)
access : read-only

REGWRPROT : Register Write-Protection Code (Write only) Some write-protected registers have to be disabled the protected function by writing the sequence value "59h", "16h", "88h" to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protected registers can be normal write.
bits : 0 - 7 (8 bit)
access : write-only

BOD_EN : Brown Out Detector Enable The default value is set by flash controller user configuration register config0 bit[23]. 1 = Brown Out Detector function is enabled 0 = Brown Out Detector function is disabled This bit is the protected bit. It means programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write

BOD_VL : Brown Out Detector Threshold Voltage Selection The default value is set by flash controller user configuration register config0 bit[22:21]. This bit is the protected bit. It means programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. BOV_VL[1] BOV_VL[0] Brown out voltage 1 1 4.5V 1 0 3.8V 0 1 2.7V 0 0 2.2V
bits : 1 - 2 (2 bit)
access : read-write

BOD_RSTEN : Brown Out Reset 1 = Enable the Brown Out "RESET" function. While the Brown Out Detector function is enabled (BOD_EN high) and BOD reset function is enabled (BOD_RSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BOD_OUT high). 0 = Enable the Brown Out "INTERRUPT" function While the BOD function is enabled (BOD_EN high) and BOD interrupt function is enabled (BOD_RSTEN low), BOD will assert an interrupt if BOD_OUT is high. BOD interrupt will keep till to the BOD_EN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BOD_EN low). The default value is set by flash controller user configuration register config0 bit[20]. This bit is the protected bit. It means programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
bits : 3 - 3 (1 bit)
access : read-write

BOD_INTF : Brown Out Detector Interrupt Flag 1 = When Brown Out Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the brown out interrupt is requested if brown out interrupt is enabled. 0 = Brown Out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting. Software can write 1 to clear this bit to zero.
bits : 4 - 4 (1 bit)
access : read-write

BOD_LPM : Brown Out Detector Low power Mode 1 = Enable the BOD low power mode 0 = BOD operate in normal mode (default) The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. This bit is the protected bit. It means programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
bits : 5 - 5 (1 bit)
access : read-write

BOD_OUT : Brown Out Detector output status 1 = Brown Out Detector output status is 1. It means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled , this bit always responds 0 0 = Brown Out Detector output status is 0. It means the detected voltage is higher than BOD_VL setting or BOD_EN is 0
bits : 6 - 6 (1 bit)
access : read-only

LVR_EN : Low Voltage Reset Enable The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled in default. 1 = Enabled Low Voltage Reset function. After enabling the bit, the LVR function will be active with 100uS delay for LVR output stable (default) 0 = Disabled Low Voltage Reset function This bit is the protected bit. It means programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100
bits : 7 - 7 (1 bit)
access : read-write

VTEMP_EN : Temperature sensor Enable This bit is used to enable/disable temperature sensor function. 1 = Enabled temperature sensor function 0 = Disabled temperature sensor function (default) After this bit is set to 1, the value of temperature can get from ADC conversion result by ADC channel selecting channel 7 and alternative multiplexer channel selecting temperature sensor. Detail ADC conversion function please reference ADC function chapter.
bits : 0 - 0 (1 bit)
access : read-write

POR_DIS_CODE : The register is used for the Power-On-Reset enable control When power on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: /RESET, Watch dog, LVR reset, BOD reset, ICE reset command and the software-chip reset function This bit is the protected bit. It means programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 15 (16 bit)
access : read-write

GPA_MFP0 : PA.0 Pin Function Selection 1 = The ADC0 (Analog-to-Digital converter channel 0) function is selected to the pin PA.0 0 = The GPIOA[0] is selected to the pin PA.0
bits : 0 - 0 (1 bit)
access : read-write

GPA_MFP1 : PA.1 Pin Function Selection The pin function depends on GPA_MFP1 and EBI_HB_EN[4] (ALT_MFP[20]) and EBI_EN (ALT_MFP[11]). EBI_HB_EN[4] EBI_EN GPA_MFP[1] PA.1 function x x 0 GPIO x 0 1 ADC1 (ADC) 0 1 1 ADC1 (ADC) 1 1 1 AD12 (EBI AD bus bit 12)
bits : 1 - 1 (1 bit)
access : read-write

GPA_MFP2 : PA.2 Pin Function Selection The pin function depends on GPA_MFP2 and EBI_HB_EN[3] (ALT_MFP[19]) and EBI_EN (ALT_MFP[11]). EBI_HB_EN[3] EBI_EN GPA_MFP[2] PA.2 function x x 0 GPIO x 0 1 ADC2 (ADC) 0 1 1 ADC2 (ADC) 1 1 1 AD11 (EBI AD bus bit 11)
bits : 2 - 2 (1 bit)
access : read-write

GPA_MFP3 : PA.3 Pin Function Selection The pin function depends on GPA_MFP3 and EBI_HB_EN[2] (ALT_MFP[18]) and EBI_EN (ALT_MFP[11]). EBI_HB_EN[2] EBI_EN GPA_MFP[3] PA.3 function x x 0 GPIO x 0 1 ADC3 (ADC) 0 1 1 ADC3 (ADC) 1 1 1 AD10 (EBI AD bus bit 10)
bits : 3 - 3 (1 bit)
access : read-write

GPA_MFP4 : PA.4 Pin Function Selection The pin function depends on GPA_MFP4 and EBI_HB_EN[1] (ALT_MFP[17]) and EBI_EN (ALT_MFP[11]). EBI_HB_EN[1] EBI_EN GPA_MFP[4] PA.4 function x x 0 GPIO x 0 1 ADC4 (ADC) 0 1 1 ADC4 (ADC) 1 1 1 AD9 (EBI AD bus bit 9)
bits : 4 - 4 (1 bit)
access : read-write

GPA_MFP5 : PA.5 Pin Function Selection The pin function depends on GPA_MFP5 and EBI_HB_EN[0] (ALT_MFP[16]) and EBI_EN (ALT_MFP[11]). EBI_HB_EN[0] EBI_EN GPA_MFP[5] PA.5 function x x 0 GPIO x 0 1 ADC5 (ADC) 0 1 1 ADC5 (ADC) 1 1 1 AD8 (EBI AD bus bit 8)
bits : 5 - 5 (1 bit)
access : read-write

GPA_MFP6 : PA.6 Pin Function Selection The pin function depends on GPA_MFP6 and EBI_EN (ALT_MFP[11]). EBI_EN GPA_MFP[6] PA.6 function x 0 GPIO 0 1 ADC6 (ADC) 1 1 AD7 (EBI AD bus bit 7)
bits : 6 - 6 (1 bit)
access : read-write

GPA_MFP7 : PA.7 Pin Function Selection The pin function depends on GPA_MFP7 and PA7_S21 (ALT_MFP[2]) and EBI_EN (ALT_MFP[11]). EBI_EN PA7_S21 GPA_MFP[7] PA.7 function x x 0 GPIO 0 0 1 ADC7 (ADC) 0 1 1 SPISS21 (SPI2) 1 x 1 AD6 (EBI AD bus bit 6)
bits : 7 - 7 (1 bit)
access : read-write

GPA_MFP8 : PA.8 Pin Function Selection 1 = The I2C0 SDA function is selected to the pin PA.8 0 = The GPIOA[8] is selected to the pin PA.8
bits : 8 - 8 (1 bit)
access : read-write

GPA_MFP9 : PA.9 Pin Function Selection 1 = The I2C0 SCL function is selected to the pin PA.9 0 = The GPIOA[9] is selected to the pin PA.9
bits : 9 - 9 (1 bit)
access : read-write

GPA_MFP10 : PA.10 Pin Function Selection The pin function depends on GPA_MFP10 and EBI_EN (ALT_MFP[11]). EBI_EN GPA_MFP[10] PA.10 function x 0 GPIO 0 1 SDA1 (I2C) 1 1 nWR (EBI)
bits : 10 - 10 (1 bit)
access : read-write

GPA_MFP11 : PA.11 Pin Function Selection The pin function depends on GPA_MFP11 and EBI_EN (ALT_MFP[11]). EBI_EN GPA_MFP[11] PA.11 function x 0 GPIO 0 1 SCL1 (I2C) 1 1 nRD (EBI)
bits : 11 - 11 (1 bit)
access : read-write

GPA_MFP12 : PA.12 Pin Function Selection The pin function depends on GPA_MFP12 and EBI_HB_EN[5] (ALT_MFP[21]) and EBI_EN (ALT_MFP[11]). EBI_HB_EN[5] EBI_EN GPA_MFP[12] PA.12 function x x 0 GPIO x 0 1 PWM0 (PWM) 0 1 1 PWM0 (PWM) 1 1 1 AD13 (EBI AD bus bit 13)
bits : 12 - 12 (1 bit)
access : read-write

GPA_MFP13 : PA.13 Pin Function Selection The pin function depends on GPA_MFP13 and EBI_HB_EN[6] (ALT_MFP[22]) and EBI_EN (ALT_MFP[11]). EBI_HB_EN[6] EBI_EN GPA_MFP[13] PA.13 function x x 0 GPIO x 0 1 PWM1 (PWM) 0 1 1 PWM1 (PWM) 1 1 1 AD14 (EBI AD bus bit 14)
bits : 13 - 13 (1 bit)
access : read-write

GPA_MFP14 : PA.14 Pin Function Selection The pin function depends on GPA_MFP14 and EBI_HB_EN[7] (ALT_MFP[23]) and EBI_EN (ALT_MFP[11]). EBI_HB_EN[7] EBI_EN GPA_MFP[14] PA.14 function x x 0 GPIO x 0 1 PWM2 (PWM) 0 1 1 PWM2 (PWM) 1 1 1 AD15 (EBI AD bus bit 15)
bits : 14 - 14 (1 bit)
access : read-write

GPA_MFP15 : PA.14 Pin Function Selection The pin function depends on GPA_MFP15 and PA15_I2SMCLK (ALT_MFP[9]). PA15_I2SMCLK GPA_MFP[15] PA.15 function x 0 GPIO 0 1 PWM3 (PWM) 1 1 I2SMCLK (I2S)
bits : 15 - 15 (1 bit)
access : read-write

GPA_TYPEn : 1 = Enable GPIOA[15:0] I/O input Schmitt Trigger function 0 = Disable GPIOA[15:0] I/O input Schmitt Trigger function
bits : 16 - 31 (16 bit)
access : read-write

GPB_MFP0 : PB.0 Pin Function Selection 1 = The UART0 RXD function is selected to the pin PB.0 0 = The GPIOB[0] is selected to the pin PB.0
bits : 0 - 0 (1 bit)
access : read-write

GPB_MFP1 : PB.1 Pin Function Selection 1 = The UART0 TXD function is selected to the pin PB.1 0 = The GPIOB[1] is selected to the pin PB.1
bits : 1 - 1 (1 bit)
access : read-write

GPB_MFP2 : PB.2 Pin Function Selection The pin function depends on GPB_MFP2 and EBI_nWRL_EN (ALT_MFP[13]) and EBI_EN (ALT_MFP[11]). EBI_nWRL_EN EBI_EN GPB_MFP[2] PB.2 function x x 0 GPIO x 0 1 RTS0 (UART0) 0 1 1 RTS0 (UART0) 1 1 1 nWRL (EBI write low byte enable)
bits : 2 - 2 (1 bit)
access : read-write

GPB_MFP3 : PB.3 Pin Function Selection The pin function depends on GPB_MFP3 and EBI_nWRH_EN (ALT_MFP[14]) and EBI_EN (ALT_MFP[11]). EBI_nWRH_EN EBI_EN GPB_MFP[3] PB.3 function x x 0 GPIO x 0 1 CTS0 (UART0) 0 1 1 CTS0 (UART0) 1 1 1 nWRH (EBI write high byte enable)
bits : 3 - 3 (1 bit)
access : read-write

GPB_MFP4 : PB.4 Pin Function Selection 1 = The UART1 RXD function is selected to the pin PB.4 0 = The GPIOB[4] is selected to the pin PB.4
bits : 4 - 4 (1 bit)
access : read-write

GPB_MFP5 : PB.5 Pin Function Selection 1 = The UART1 TXD function is selected to the pin PB.5 0 = The GPIOB[5] is selected to the pin PB.5
bits : 5 - 5 (1 bit)
access : read-write

GPB_MFP6 : PB.6 Pin Function Selection The pin function depends on GPB_MFP6 and EBI_EN (ALT_MFP[11]). EBI_EN GPB_MFP[6] PB.6 function x 0 GPIO 0 1 TRS1 (UART1) 1 1 ALE (EBI)
bits : 6 - 6 (1 bit)
access : read-write

GPB_MFP7 : PB.7 Pin Function Selection The pin function depends on GPB_MFP7 and EBI_EN (ALT_MFP[11]). EBI_EN GPB_MFP[7] PB.7 function x 0 GPIO 0 1 CTS1 (UART1) 1 1 nCS (EBI)
bits : 7 - 7 (1 bit)
access : read-write

GPB_MFP8 : PB.8 Pin Function Selection 1 = The TM0 (Timer/Counter external trigger clock input) function is selected to the pin PB.8 0 = The GPIOB[8] is selected to the pin PB.8
bits : 8 - 8 (1 bit)
access : read-write

GPB_MFP9 : PB.9 Pin Function Selection The pin function depends on GPB_MFP9 and PB9_S11 (ALT_MFP[1]). PB9_S11 GPB_MFP[9] PB.9 function x 0 GPIO 0 1 TM1 1 1 SPISS11 (SPI1)
bits : 9 - 9 (1 bit)
access : read-write

GPB_MFP10 : PB.10 Pin Function Selection The pin function depends on GPB_MFP10 and PB10_S01 (ALT_MFP[0]). PB10_S01 GPB_MFP[10] PB.10 function x 0 GPIO 0 1 TM2 1 1 SPISS01 (SPI0)
bits : 10 - 10 (1 bit)
access : read-write

GPB_MFP11 : PB.11 Pin Function Selection The pin function depends on GPB_MFP11 and PB11_PWM4 (ALT_MFP[4]). PB11_PWM4 GPB_MFP[11] PB.11 function x 0 GPIO 0 1 TM3 1 1 PWM4 (PWM)
bits : 11 - 11 (1 bit)
access : read-write

GPB_MFP12 : PB.12 Pin Function Selection The pin function depends on GPB_MFP12 and PB12_CLKO (ALT_MFP[10]) and EBI_EN (ALT_MFP[11]). EBI_EN PB12_CLKO GPB_MFP[12] PB.12 function x x 0 GPIO 0 0 1 CPO0(CMP) 0 1 1 CLKO (Clock Driver output) 1 x 1 AD0(EBI AD bus bit 0)
bits : 12 - 12 (1 bit)
access : read-write

GPB_MFP13 : PB.13 Pin Function Selection The pin function depends on GPB_MFP13 and EBI_EN (ALT_MFP[11]). EBI_EN GPB_MFP[13] PB.13 function x 0 GPIO 0 1 CPO1 (CMP) 1 1 AD1 (EBI AD bus bit 1)
bits : 13 - 13 (1 bit)
access : read-write

GPB_MFP14 : PB.14 Pin Function Selection The pin function depends on GPB_MFP14 and PB14_S31 (ALT_MFP[3]). PB14_S31 GPB_MFP[14] PB.14 function x 0 GPIO 0 1 /INT0 1 1 SPISS31 (SPI3)
bits : 14 - 14 (1 bit)
access : read-write

GPB_MFP15 : PB.15 Pin Function Selection 1 = The External Interrupt INT1 function is selected to the pin PB.15 0 = The GPIOB[15] is selected to the pin PB.15
bits : 15 - 15 (1 bit)
access : read-write

GPB_TYPEn : 1 = Enable GPIOB[15:0] I/O input Schmitt Trigger function 0 = Disable GPIOB[15:0] I/O input Schmitt Trigger function
bits : 16 - 31 (16 bit)
access : read-write

SPI0_SS0_I2SLRCLK : PC.0 Pin Function Selection Bits PC0_I2SLRCLK (ALT_MFP[5]) and GPC_MFP[0] determine the PC.0 function. PC0_I2SLRCLK GPC_MFP[0] PC.0 function x 0 GPIO 0 1 SPISS00(SPI0) 1 1 I2SLRCLK (I2S)
bits : 0 - 0 (1 bit)
access : read-write

SPI0_CLK_I2SBCLK : PC.1 Pin Function Selection Bits PC1_I2SBCLK (ALT_MFP[6]) and GPC_MFP[1] determine the PC.1 function. PC1_I2SBCLK GPC_MFP[1] PC.1 function x 0 GPIO 0 1 SPICLK0 (SPI0) 1 1 I2SBLK (I2S)
bits : 1 - 1 (1 bit)
access : read-write

SPI0_MISO0_I2SDI : PC.2 Pin Function Selection Bits PC2_I2SDI (ALT_MFP[7]) and GPC_MFP[2] determine the PC.2 function. PC2_I2SDI GPC_MFP[2] PC.2 function x 0 GPIO 0 1 MISO00 (SPI0) 1 1 I2SDI (I2S)
bits : 2 - 2 (1 bit)
access : read-write

SPI0_MOSI0_I2SDO : PC.3 Pin Function Selection Bits PC3_I2SDO (ALT_MFP[8]) and GPC_MFP[3] determine the PC.3 function. PC3_I2SDO GPC_MFP[3] PC.3 function x 0 GPIO 0 1 MOSI00 (SPI0) 1 1 I2SDO (I2S)
bits : 3 - 3 (1 bit)
access : read-write

SPI0_MISO1 : PC.4 Pin Function Selection 1 = The SPI0 MISO1 (master input, slave output pin-1) function is selected to the pin PC.4 0 = The GPIOC[4] is selected to the pin PC.4
bits : 4 - 4 (1 bit)
access : read-write

SPI0_MOSI1 : PC.5 Pin Function Selection 1 = The SPI0 MOSI1 (master output, slave input pin-1) function is selected to the pin PC.5 0 = The GPIOC[5] is selected to the pin PC.5
bits : 5 - 5 (1 bit)
access : read-write

CPP0_AD4 : PC.6 Pin Function Selection The pin function depends on GPC_MFP6 and EBI_EN (ALT_MFP[11]). EBI_EN GPC_MFP[6] PC.6 function x 0 GPIO 0 1 CPP0 (CMP) 1 1 AD4 (EBI AD bus bit 4)
bits : 6 - 6 (1 bit)
access : read-write

CPN0_AD5 : PC.7 Pin Function Selection The pin function depends on GPC_MFP7 and EBI_EN (ALT_MFP[11]). EBI_EN GPC_MFP[7] PC.7 function x 0 GPIO 0 1 CPN0 (CMP) 1 1 AD5 (EBI AD bus bit 5)
bits : 7 - 7 (1 bit)
access : read-write

SPI1_SS0_MCLK : PC.8 Pin Function Selection The pin function depends on GPC_MFP8 and EBI_MCLK_EN (ALT_MFP[12]) and EBI_EN (ALT_MFP[11]). EBI_MCLK_EN EBI_EN GPC_MFP[8] PC.8 function x x 0 GPIO x 0 1 SPISS10 (SPI1) 0 1 1 SPISS10 (SPI1) 1 1 1 MCLK (EBI Clock output)
bits : 8 - 8 (1 bit)
access : read-write

SPI1_CLK : PC.9 Pin Function Selection 1 = The SPI1 SPICLK function is selected to the pin PC.9 0 = The GPIOC[9] is selected to the pin PC.9
bits : 9 - 9 (1 bit)
access : read-write

SPI1_MISO0 : PC.10 Pin Function Selection 1 = The SPI1 MISO0 (master input, slave output pin-0) function is selected to the pin PC.10 0 = The GPIOC[10] is selected to the pin PC.10
bits : 10 - 10 (1 bit)
access : read-write

SPI1_MOSI0 : PC.11 Pin Function Selection 1 = The SPI1 MOSI0 (master output, slave input pin-0) function is selected to the pin PC.11 0 = The GPIOC[11] is selected to the pin PC.11
bits : 11 - 11 (1 bit)
access : read-write

SPI1_MISO1 : PC.12 Pin Function Selection 1 = The SPI1 MISO1 (master input, slave output pin-1) function is selected to the pin PC.12 0 = The GPIOC[12] is selected to the pin PC.12
bits : 12 - 12 (1 bit)
access : read-write

SPI1_MOSI1 : PC.13 Pin Function Selection 1 = The SPI1 MOSI1 (master output, slave input pin-1) function is selected to the pin PC.13 0 = The GPIOC[13] is selected to the pin PC.13
bits : 13 - 13 (1 bit)
access : read-write

CPP1_AD2 : PC.14 Pin Function Selection The pin function depends on GPC_MFP14 and EBI_EN (ALT_MFP[11]). EBI_EN GPC_MFP[14] PC.14 function x 0 GPIO 0 1 CPP1 (CMP) 1 1 AD2 (EBI AD bus bit 2)
bits : 14 - 14 (1 bit)
access : read-write

CPP1_AD3 : PC.15 Pin Function Selection The pin function depends on GPC_MFP15 and EBI_EN (ALT_MFP[11]). EBI_EN GPC_MFP[15] PC.15 function x 0 GPIO 0 1 CPN1 (CMP) 1 1 AD3 (EBI AD bus bit 3)
bits : 15 - 15 (1 bit)
access : read-write

SCHMITT : 1 = Enable GPIOC[15:0] I/O input Schmitt Trigger function 0 = Disable GPIOC[15:0] I/O input Schmitt Trigger function
bits : 16 - 31 (16 bit)
access : read-write

GPD_MFP0 : PD.0 Pin Function Selection (Medium Density Only) 1 = The SPI2 SS20 function is selected to the pin PD.0 0 = The GPIOD[0] is selected to the pin PD.0
bits : 0 - 0 (1 bit)
access : read-write

GPD_MFP1 : PD.1 Pin Function Selection For NUC100/NUC120/NUC130/NUC140 Medium Density 1 = The SPI2 SPICLK function is selected to the pin PD.1 0 = The GPIOD[1] is selected to the pin PD.1 For NUC100/NUC120/NUC130/NUC140 Low Density and NUC101 LQFP48 package Reserved For NUC101 QFN36 package 1 = The SPI0 SS01 function is selected to the pin PD.1 0 = The GPIOD[1] is selected to the pin PD.1
bits : 1 - 1 (1 bit)
access : read-write

GPD_MFP2 : PD.2 Pin Function Selection For NUC100/NUC120/NUC130/NUC140 Medium Density 1 = The SPI2 MISO0 (master input, slave output pin-0) function is selected to the pin PD.2 0 = The GPIOD[2] is selected to the pin PD.2 For NUC100/NUC120/NUC130/NUC140 Low Density and NUC101 LQFP48 package Reserved For NUC101 QFN36 package 1 = The SPI0 MISO1 (master input, slave output pin-1) function is selected to the pin PD.2 0 = The GPIOD[2] is selected to the pin PD.2
bits : 2 - 2 (1 bit)
access : read-write

GPD_MFP3 : PD.3 Pin Function Selection For NUC100/NUC120/NUC130/NUC140 Medium Density 1 = The SPI2 MOSI0 (master output, slave input pin-0) function is selected to the pin GPD3 0 = The GPIOD[3] is selected to the pin PD.3 For NUC100/NUC120/NUC130/NUC140 Low Density and NUC101 LQFP48 package Reserved For NUC101 QFN36 package 1 = The SPI0 MOSI1 (master output, slave input pin-1) function is selected to the pin PD.3 0 = The GPIOD[3] is selected to the pin PD.3
bits : 3 - 3 (1 bit)
access : read-write

GPD_MFP4 : PD.4 Pin Function Selection (Medium Density Only) 1 = The SPI2 MISO1 (master input, slave output pin-1) function is selected to the pin PD.4 0 = The GPIOD[4]is selected to the pin PD.4
bits : 4 - 4 (1 bit)
access : read-write

GPD_MFP5 : PD.5 Pin Function Selection (Medium Density Only) 1 = The SPI2 MOSI1 (master output, slave input pin-1) function is selected to the pin PD.5 0 = The GPIOD[5] is selected to the pin PD.5
bits : 5 - 5 (1 bit)
access : read-write

GPD_MFP6 : PD.6 Pin Function Selection (Medium Density Only) 1 = The CAN0 RX function is selected to the pin PD.6 0 = The GPIOD[6] is selected to the pin PD.6
bits : 6 - 6 (1 bit)
access : read-write

GPD_MFP7 : PD.7 Pin Function Selection (Medium Density Only) 1 = The CAN0 TX function is selected to the pin PD.7 0 = The GPIOD[7] is selected to the pin PD.7
bits : 7 - 7 (1 bit)
access : read-write

GPD_MFP8 : PD.8 Pin Function Selection (Medium Density Only) 1 = The SPI3 SS30 function is selected to the pin PD8 0 = The GPIOD[8] is selected to the pin PD8
bits : 8 - 8 (1 bit)
access : read-write

GPD_MFP9 : PD.9 Pin Function Selection (Medium Density Only) 1 = The SPI3 SPICLK function is selected to the pin PD.9 0 = The GPIOD-9 is selected to the pin PD.9
bits : 9 - 9 (1 bit)
access : read-write

GPD_MFP10 : PD.10 Pin Function Selection (Medium Density Only) 1 = The SPI3 MISO0 (master input, slave output pin-0) function is selected to the pin PD.10 0 = The GPIOD[10] is selected to the pin PD.10
bits : 10 - 10 (1 bit)
access : read-write

GPD_MFP11 : PD.11 Pin Function Selection (Medium Density Only) 1 = The SPI3 MOSI0 (master output, slave input pin-0) function is selected to the pin PD.11 0 = The GPIOD[11] is selected to the pin PD.11
bits : 11 - 11 (1 bit)
access : read-write

GPD_MFP12 : PD.12 Pin Function Selection (Medium Density Only) 1 = The SPI3 MISO1 (master input, slave output pin-1) function is selected to the pin PD.12 0 = The GPIOD[12] is selected to the pin PD.12
bits : 12 - 12 (1 bit)
access : read-write

GPD_MFP13 : PD.13 Pin Function Selection (Medium Density Only) 1 = The SPI3 MOSI1 (master output, slave input pin-1) function is selected to the pin PD.13 0 = The GPIOD[13] is selected to the pin PD.13
bits : 13 - 13 (1 bit)
access : read-write

GPD_MFP14 : PD.14 Pin Function Selection (Medium Density Only) 1 = The UART2 RXD function is selected to the pin PD.14 0 = The GPIOD[14] selected to the pin PD.14
bits : 14 - 14 (1 bit)
access : read-write

GPD_MFP15 : PD.15 Pin Function Selection (Medium Density Only) 1 = The UART2 TXD function is selected to the pin PD.15 0 = The GPIOD[15] selected to the pin PD.15
bits : 15 - 15 (1 bit)
access : read-write

GPD_TYPEn : 1 = Enable GPIOD[15:0] I/O input Schmitt Trigger function 0 = Disable GPIOD[15:0] I/O input Schmitt Trigger function
bits : 16 - 31 (16 bit)
access : read-write

RSTS_POR : The RSTS_POR flag is set by the "reset signal" from the Power-On Reset (POR) module or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source 1= The Power-On Reset (POR) or CHIP_RST had issued the reset signal to reset the system. 0= No reset from POR or CHIP_RS Software can write 1 to clear this bit to zero.
bits : 0 - 0 (1 bit)
access : read-write

RSTS_RESET : The RSTS_RESET flag is set by the "reset signal" from the /RESET pin to indicate the previous reset source. 1 = The Pin /RESET had issued the reset signal to reset the system. 0 = No reset from /RESET pin Software can write 1 to clear this bit to zero.
bits : 1 - 1 (1 bit)
access : read-write

RSTS_WDT : The The RSTS_WDT flag is set by the "reset signal" from the watchdog timer to indicate the previous reset source. 1 = The watchdog timer had issued the reset signal to reset the system. 0 = No reset from watchdog timer Software can write 1 to clear this bit to zero.
bits : 2 - 2 (1 bit)
access : read-write

RSTS_LVR : The RSTS_LVR flag is set by the "reset signal" from the Low-Voltage-Reset controller to indicate the previous reset source. 1 = The LVR controller had issued the reset signal to reset the system. 0 = No reset from LVR Software can write 1 to clear this bit to zero.
bits : 3 - 3 (1 bit)
access : read-write

RSTS_BOD : The RSTS_BOD flag is set by the "reset signal" from the Brown-Out-Detector controller to indicate the previous reset source. 1 = The BOD had issued the reset signal to reset the system. 0 = No reset from BOD Software can write 1 to clear this bit to zero.
bits : 4 - 4 (1 bit)
access : read-write

RSTS_SYS : The RSTS_SYS flag is set by the "reset signal" from the Cortex_M0 kernel to indicate the previous reset source. 1 = The Cortex_M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESTREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex_M0 kernel. 0 = No reset from Cortex_M0 Software can write 1 to clear this bit to zero.
bits : 5 - 5 (1 bit)
access : read-write

RSTS_CPU : The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC). 1 = The Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1 0 = No reset from CPU Software can write 1 to clear this bit to zero.
bits : 7 - 7 (1 bit)
access : read-write

GPE_MFP0 : PE.0 Pin Function Selection (Medium Density Only) 1 = The PWM6 function is selected to the pin PE.0 0 = The GPIOE[0] is selected to the pin PE.0
bits : 0 - 0 (1 bit)
access : read-write

GPE_MFP1 : PE.1 Pin Function Selection (Medium Density Only) 1 = The PWM7 function is selected to the pin PE.1 0 = The GPIOE[1] is selected to the pin PE.1
bits : 1 - 1 (1 bit)
access : read-write

GPE_MFP5 : PE.5 Pin Function Selection (Medium Density Only) 1 = The PWM5 function is selected to the pin PE.5 0 = The GPIOE[5] is selected to the pin PE.5
bits : 5 - 5 (1 bit)
access : read-write

GPE_TYPEn : 1 = Enable GPIOE[15:0] I/O input Schmitt Trigger function 0 = Disable GPIOE[15:0] I/O input Schmitt Trigger function Note: In this field, Low Density only has GPE_TYPE5 bit
bits : 16 - 31 (16 bit)
access : read-write

PB10_S01 : Bits PB10_S01 and GPB_MFP10 determine the PB.10 function. PB10_S01 GPB_MFP[10] PB.10 function x 0 GPIO 0 1 TM2 1 1 SPISS01 (SPI0)
bits : 0 - 0 (1 bit)
access : read-write

PB9_S11 : Bits PB9_S11 and GPB_MFP9 determine the PB.9 function. PB9_S11 GPB_MFP[9] PB.9 function x 0 GPIO 0 1 TM1 1 1 SPISS11 (SPI1)
bits : 1 - 1 (1 bit)
access : read-write

PA7_S21 : Bits PA7_S21, PA_MFP7 and EBI_EN (ALT_MFP[11])determine the PA.7 function. EBI_EN PA7_S21 GPA_MFP[7] PA.7 function x x 0 GPIO 0 0 1 ADC7 (ADC) 0 1 1 SPISS21 (SPI2) 1 x 1 AD6 (EBI AD bus bit 6)
bits : 2 - 2 (1 bit)
access : read-write

PB14_S31 : Bits PB14_S31 and GPB_MFP14 determine the GPB14 function. PB14_S31 GPB_MFP[14] PB.14 function x 0 GPIO 0 1 /INT0 1 1 SPISS31 (SPI3)
bits : 3 - 3 (1 bit)
access : read-write

PB11_PWM4 : Bits PB11_PWM4 and GPB_MFP[11] determine the PB.11 function. PB11_PWM4 GPB_MFP[11] PB.11 function x 0 GPIO 0 1 TM3 1 1 PWM4 (PWM)
bits : 4 - 4 (1 bit)
access : read-write

PC0_I2SLRCLK : Bits PC0_I2SLRCLK and GPC_MFP[0] determine the PC.0 function. PC0_I2SLRCLK GPC_MFP[0] PC.0 function x 0 GPIO 0 1 SPISS00(SPI0) 1 1 I2SLRCLK (I2S)
bits : 5 - 5 (1 bit)
access : read-write

PC1_I2SBCLK : Bits PC1_I2SBCLK and GPC_MFP[1] determine the PC.1 function. PC1_I2SBCLK GPC_MFP[1] PC.1 function x 0 GPIO 0 1 SPICLK0 (SPI0) 1 1 I2SBLK (I2S)
bits : 6 - 6 (1 bit)
access : read-write

PC2_I2SDI : Bits PC2_I2SDI and GPC_MFP[2] determine the PC.2 function. PC2_I2SDI GPC_MFP[2] PC.2 function x 0 GPIO 0 1 MISO00 (SPI0) 1 1 I2SDI (I2S)
bits : 7 - 7 (1 bit)
access : read-write

PC3_I2SDO : Bits PC3_I2SDO and GPC_MFP[3] determine the PC.3 function. PC3_I2SDO GPC_MFP[3] PC.3 function x 0 GPIO 0 1 MOSI00 (SPI0) 1 1 I2SDO (I2S)
bits : 8 - 8 (1 bit)
access : read-write

PA15_I2SMCLK : Bits PA15_I2SMCLK and GPA_MFP[15] determine the PA.15 function. PA15_I2SMCLK GPA_MFP[15] PA.15 function x 0 GPIO 0 1 PWM3 (PWM) 1 1 I2SMCLK (I2S)
bits : 9 - 9 (1 bit)
access : read-write

PB12_CLKO : Bits PB12_CLKO and GPB_MFP[12] determine the PB.12 function. EBI_EN PB12_CLKO GPB_MFP[12] PB.12 function x x 0 GPIO x 0 1 CPO0 (CMP) 0 1 1 CLKO (Clock Driver output) 1 1 1 AD0 (EBI AD bus bit 0)
bits : 10 - 10 (1 bit)
access : read-write

EBI_EN : EBI_EN is use to switch GPIO function to EBI function (AD[15:0], ALE, RE, WE, CS, MCLK), it need additional registers EBI_EN[7:0] and EBI_MCLK_EN for some GPIO to switch to EBI function(AD[15:8], MCLK)
bits : 11 - 11 (1 bit)
access : read-write

EBI_MCLK_EN : Bits EBI_MCLK_EN, EBI_EN and GPC_MFP[8] determine the PC.8 function. EBI_MCLK_EN EBI_EN GPC_MFP[8] PC.8 function x x 0 GPIO x 0 1 SPISS10 (SPI1) 0 1 1 SPISS10 (SPI1) 1 1 1 MCLK (EBI Clock output)
bits : 12 - 12 (1 bit)
access : read-write

EBI_nWRL_EN : Bits EBI_nWRL_EN, EBI_EN and GPB_MFP[2] determine the PB.2 function. EBI_nWRL_EN EBI_EN GPB_MFP[2] PB.2 function x x 0 GPIO x 0 1 RTS0 (UART0) 0 1 1 RTS0 (UART0) 1 1 1 nWRL (EBI write low byte enable)
bits : 13 - 13 (1 bit)
access : read-write

EBI_nWRH_EN : Bits EBI_nWRH_EN, EBI_EN and GPB_MFP[3] determine the PB.3 function EBI_nWRH_EN EBI_EN GPB_MFP[3] PB.3 function x x 0 GPIO x 0 1 CTS0 (UART0) 0 1 1 CTS0 (UART0) 1 1 1 nWRH (EBI write high byte enable)
bits : 14 - 14 (1 bit)
access : read-write

EBI_HB_EN : EBI_HB_EN is use to switch GPIO function to EBI address/data bus high byte (AD[15:8]), EBI_HB_EN, EBI_EN and corresponding GPx_MFP[y] determine the Px.y function.
bits : 16 - 23 (8 bit)
access : read-write

CHIP_RST : CHIP one shot reset (write-protection bit) Setting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIP_RST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. About the difference between CHIP_RST and SYSRESETREQ, please refer to section 5.2.2 of TRM. This bit is the protected bit. It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 1 = CHIP one shot reset 0 = CHIP normal operation
bits : 0 - 0 (1 bit)
access : read-write

CPU_RST : CPU kernel one shot reset (write-protection bit) Setting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles This bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 1 = CPU one shot reset 0 = CPU normal operation
bits : 1 - 1 (1 bit)
access : read-write

PDMA_RST : PDMA Controller Reset (write-protection bit in NUC100/NUC120/NUC130/NUC140 Low Density and NUC101) Setting this bit to 1 will generate a reset signal to the PDMA. User need to set this bit to 0 to release from reset state This bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100 1 = PDMA controller reset 0 = PDMA controller normal operation
bits : 2 - 2 (1 bit)
access : read-write

EBI_RST : EBI Controller Reset (write-protection bit in NUC100/NUC120/NUC130/NUC140 Low Density 64-pin package) Set this bit to 1 will generate a reset signal to the EBI. User need to set this bit to 0 to release from the reset state. This bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 1 = EBI controller reset 0 = EBI controller normal operation
bits : 3 - 3 (1 bit)
access : read-write

GPIO_RST : GPIO controller Reset 1 = GPIO controller reset 0 = GPIO controller normal operation
bits : 1 - 1 (1 bit)
access : read-write

TMR0_RST : Timer0 controller Reset 1 = Timer0 controller reset 0 = Timer0 controller normal operation
bits : 2 - 2 (1 bit)
access : read-write

TMR1_RST : Timer1 controller Reset 1 = Timer1 controller reset 0 = Timer1 controller normal operation
bits : 3 - 3 (1 bit)
access : read-write

TMR2_RST : Timer2 controller Reset 1 = Timer2 controller reset 0 = Timer2 controller normal operation
bits : 4 - 4 (1 bit)
access : read-write

TMR3_RST : Timer3 controller Reset 1 = Timer3 controller reset 0 = Timer3 controller normal operation
bits : 5 - 5 (1 bit)
access : read-write

I2C0_RST : I2C0 controller Reset 1 = I2C0 controller reset 0 = I2C0 controller normal operation
bits : 8 - 8 (1 bit)
access : read-write

I2C1_RST : I2C1 controller Reset 1 = I2C1 controller reset 0 = I2C1 controller normal operation
bits : 9 - 9 (1 bit)
access : read-write

SPI0_RST : SPI0 controller Reset 1 = SPI0 controller reset 0 = SPI0 controller normal operation
bits : 12 - 12 (1 bit)
access : read-write

SPI1_RST : SPI1 controller Reset 1 = SPI1 controller reset 0 = SPI1 controller normal operation
bits : 13 - 13 (1 bit)
access : read-write

SPI2_RST : SPI2 controller Reset (Medium Density Only) 1 = SPI2 controller reset 0 = SPI2 controller normal operation
bits : 14 - 14 (1 bit)
access : read-write

SPI3_RST : SPI3 controller Reset (Medium Density Only) 1 = SPI3 controller reset 0 = SPI3 controller normal operation
bits : 15 - 15 (1 bit)
access : read-write

UART0_RST : UART0 controller Reset 1 = UART0 controller reset 0 = UART0 controller normal operation
bits : 16 - 16 (1 bit)
access : read-write

UART1_RST : UART1 controller Reset 1 = UART1 controller reset 0 = UART1 controller normal operation
bits : 17 - 17 (1 bit)
access : read-write

UART2_RST : UART2 controller Reset (Medium Density Only) 1 = UART2 controller reset 0 = UART2 controller normal operation
bits : 18 - 18 (1 bit)
access : read-write

PWM03_RST : PWM03 controller Reset 1 = PWM03 controller reset 0 = PWM03 controller normal operation
bits : 20 - 20 (1 bit)
access : read-write

PWM47_RST : PWM47 controller Reset (Medium Density Only) 1 = PWM47 controller reset 0 = PWM47 controller normal operation
bits : 21 - 21 (1 bit)
access : read-write

ACMP_RST : Analog Comparator Controller Reset 1 = Analog Comparator controller reset 0 = Analog Comparator controller normal operation
bits : 22 - 22 (1 bit)
access : read-write

PS2_RST : PS2 Controller Reset 1 = PS2 controller reset 0 = PS2 controller normal operation
bits : 23 - 23 (1 bit)
access : read-write

CAN0_RST : CAN0 Controller Reset 1 = CAN0 controller reset 0 = CAN0 controller normal operation
bits : 24 - 24 (1 bit)
access : read-write

USBD_RST : USB Device Controller Reset 1 = USB device controller reset 0 = USB devide controller normal operation
bits : 27 - 27 (1 bit)
access : read-write

ADC_RST : ADC Controller Reset 1 = ADC controller reset 0 = ADC controller normal operation
bits : 28 - 28 (1 bit)
access : read-write

I2S_RST : I2S Controller Reset 1 = I2S controller reset 0 = I2S controller normal operation
bits : 29 - 29 (1 bit)
access : read-write