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GPIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PMD

PIN

DBEN

IMD

IEN

ISRC

OFFD

DOUT

DMASK


PMD

GPIO Port Pin I/O Mode Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMD PMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMD8 PMD9 PMD10 PMD11 PMD12 PMD13 PMD14 PMD15

PMD0 : GPIOX I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins 00 = GPIO port [n] pin is in INPUT mode. 01 = GPIO port [n] pin is in OUTPUT mode. 10 = GPIO port [n] pin is in Open-Drain mode. 11 = GPIO port [n] pin is in Quasi-bidirectional mode.
bits : 0 - 1 (2 bit)
access : read-write

PMD1 : GPIOX I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins 00 = GPIO port [n] pin is in INPUT mode. 01 = GPIO port [n] pin is in OUTPUT mode. 10 = GPIO port [n] pin is in Open-Drain mode. 11 = GPIO port [n] pin is in Quasi-bidirectional mode.
bits : 2 - 3 (2 bit)
access : read-write

PMD2 : GPIOX I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins 00 = GPIO port [n] pin is in INPUT mode. 01 = GPIO port [n] pin is in OUTPUT mode. 10 = GPIO port [n] pin is in Open-Drain mode. 11 = GPIO port [n] pin is in Quasi-bidirectional mode.
bits : 4 - 5 (2 bit)
access : read-write

PMD3 : GPIOX I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins 00 = GPIO port [n] pin is in INPUT mode. 01 = GPIO port [n] pin is in OUTPUT mode. 10 = GPIO port [n] pin is in Open-Drain mode. 11 = GPIO port [n] pin is in Quasi-bidirectional mode.
bits : 6 - 7 (2 bit)
access : read-write

PMD4 : GPIOX I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins 00 = GPIO port [n] pin is in INPUT mode. 01 = GPIO port [n] pin is in OUTPUT mode. 10 = GPIO port [n] pin is in Open-Drain mode. 11 = GPIO port [n] pin is in Quasi-bidirectional mode.
bits : 8 - 9 (2 bit)
access : read-write

PMD5 : GPIOX I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins 00 = GPIO port [n] pin is in INPUT mode. 01 = GPIO port [n] pin is in OUTPUT mode. 10 = GPIO port [n] pin is in Open-Drain mode. 11 = GPIO port [n] pin is in Quasi-bidirectional mode.
bits : 10 - 11 (2 bit)
access : read-write

PMD6 : GPIOX I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins 00 = GPIO port [n] pin is in INPUT mode. 01 = GPIO port [n] pin is in OUTPUT mode. 10 = GPIO port [n] pin is in Open-Drain mode. 11 = GPIO port [n] pin is in Quasi-bidirectional mode.
bits : 12 - 13 (2 bit)
access : read-write

PMD7 : GPIOX I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins 00 = GPIO port [n] pin is in INPUT mode. 01 = GPIO port [n] pin is in OUTPUT mode. 10 = GPIO port [n] pin is in Open-Drain mode. 11 = GPIO port [n] pin is in Quasi-bidirectional mode.
bits : 14 - 15 (2 bit)
access : read-write

PMD8 : GPIOX I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins 00 = GPIO port [n] pin is in INPUT mode. 01 = GPIO port [n] pin is in OUTPUT mode. 10 = GPIO port [n] pin is in Open-Drain mode. 11 = GPIO port [n] pin is in Quasi-bidirectional mode.
bits : 16 - 17 (2 bit)
access : read-write

PMD9 : GPIOX I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins 00 = GPIO port [n] pin is in INPUT mode. 01 = GPIO port [n] pin is in OUTPUT mode. 10 = GPIO port [n] pin is in Open-Drain mode. 11 = GPIO port [n] pin is in Quasi-bidirectional mode.
bits : 18 - 19 (2 bit)
access : read-write

PMD10 : GPIOX I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins 00 = GPIO port [n] pin is in INPUT mode. 01 = GPIO port [n] pin is in OUTPUT mode. 10 = GPIO port [n] pin is in Open-Drain mode. 11 = GPIO port [n] pin is in Quasi-bidirectional mode.
bits : 20 - 21 (2 bit)
access : read-write

PMD11 : GPIOX I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins 00 = GPIO port [n] pin is in INPUT mode. 01 = GPIO port [n] pin is in OUTPUT mode. 10 = GPIO port [n] pin is in Open-Drain mode. 11 = GPIO port [n] pin is in Quasi-bidirectional mode.
bits : 22 - 23 (2 bit)
access : read-write

PMD12 : GPIOX I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins 00 = GPIO port [n] pin is in INPUT mode. 01 = GPIO port [n] pin is in OUTPUT mode. 10 = GPIO port [n] pin is in Open-Drain mode. 11 = GPIO port [n] pin is in Quasi-bidirectional mode.
bits : 24 - 25 (2 bit)
access : read-write

PMD13 : GPIOX I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins 00 = GPIO port [n] pin is in INPUT mode. 01 = GPIO port [n] pin is in OUTPUT mode. 10 = GPIO port [n] pin is in Open-Drain mode. 11 = GPIO port [n] pin is in Quasi-bidirectional mode.
bits : 26 - 27 (2 bit)
access : read-write

PMD14 : GPIOX I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins 00 = GPIO port [n] pin is in INPUT mode. 01 = GPIO port [n] pin is in OUTPUT mode. 10 = GPIO port [n] pin is in Open-Drain mode. 11 = GPIO port [n] pin is in Quasi-bidirectional mode.
bits : 28 - 29 (2 bit)
access : read-write

PMD15 : GPIOX I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins 00 = GPIO port [n] pin is in INPUT mode. 01 = GPIO port [n] pin is in OUTPUT mode. 10 = GPIO port [n] pin is in Open-Drain mode. 11 = GPIO port [n] pin is in Quasi-bidirectional mode.
bits : 30 - 31 (2 bit)
access : read-write


PIN

GPIO Port Pin Value
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIN PIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 PIN8 PIN9 PIN10 PIN11 PIN12 PIN13 PIN14 PIN15

PIN0 : Port [A/B/C/D/E] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 0 - 0 (1 bit)
access : read-only

PIN1 : Port [A/B/C/D/E] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 1 - 1 (1 bit)
access : read-only

PIN2 : Port [A/B/C/D/E] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 2 - 2 (1 bit)
access : read-only

PIN3 : Port [A/B/C/D/E] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 3 - 3 (1 bit)
access : read-only

PIN4 : Port [A/B/C/D/E] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 4 - 4 (1 bit)
access : read-only

PIN5 : Port [A/B/C/D/E] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 5 - 5 (1 bit)
access : read-only

PIN6 : Port [A/B/C/D/E] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 6 - 6 (1 bit)
access : read-only

PIN7 : Port [A/B/C/D/E] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 7 - 7 (1 bit)
access : read-only

PIN8 : Port [A/B/C/D/E] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 8 - 8 (1 bit)
access : read-only

PIN9 : Port [A/B/C/D/E] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 9 - 9 (1 bit)
access : read-only

PIN10 : Port [A/B/C/D/E] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 10 - 10 (1 bit)
access : read-only

PIN11 : Port [A/B/C/D/E] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 11 - 11 (1 bit)
access : read-only

PIN12 : Port [A/B/C/D/E] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 12 - 12 (1 bit)
access : read-only

PIN13 : Port [A/B/C/D/E] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 13 - 13 (1 bit)
access : read-only

PIN14 : Port [A/B/C/D/E] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 14 - 14 (1 bit)
access : read-only

PIN15 : Port [A/B/C/D/E] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 15 - 15 (1 bit)
access : read-only


DBEN

GPIO Port De-bounce Enable
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBEN DBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBEN0 DBEN1 DBEN2 DBEN3 DBEN4 DBEN5 DBEN6 DBEN7 DBEN8 DBEN9 DBEN10 DBEN11 DBEN12 DBEN13 DBEN14 DBEN15

DBEN0 : Port [A/B/C/D/E] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 1 = The bit[n] de-bounce function is enabled 0 = The bit[n] de-bounce function is disabled The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 0 - 0 (1 bit)
access : read-write

DBEN1 : Port [A/B/C/D/E] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 1 = The bit[n] de-bounce function is enabled 0 = The bit[n] de-bounce function is disabled The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 1 - 1 (1 bit)
access : read-write

DBEN2 : Port [A/B/C/D/E] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 1 = The bit[n] de-bounce function is enabled 0 = The bit[n] de-bounce function is disabled The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 2 - 2 (1 bit)
access : read-write

DBEN3 : Port [A/B/C/D/E] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 1 = The bit[n] de-bounce function is enabled 0 = The bit[n] de-bounce function is disabled The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 3 - 3 (1 bit)
access : read-write

DBEN4 : Port [A/B/C/D/E] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 1 = The bit[n] de-bounce function is enabled 0 = The bit[n] de-bounce function is disabled The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 4 - 4 (1 bit)
access : read-write

DBEN5 : Port [A/B/C/D/E] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 1 = The bit[n] de-bounce function is enabled 0 = The bit[n] de-bounce function is disabled The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 5 - 5 (1 bit)
access : read-write

DBEN6 : Port [A/B/C/D/E] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 1 = The bit[n] de-bounce function is enabled 0 = The bit[n] de-bounce function is disabled The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 6 - 6 (1 bit)
access : read-write

DBEN7 : Port [A/B/C/D/E] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 1 = The bit[n] de-bounce function is enabled 0 = The bit[n] de-bounce function is disabled The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 7 - 7 (1 bit)
access : read-write

DBEN8 : Port [A/B/C/D/E] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 1 = The bit[n] de-bounce function is enabled 0 = The bit[n] de-bounce function is disabled The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 8 - 8 (1 bit)
access : read-write

DBEN9 : Port [A/B/C/D/E] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 1 = The bit[n] de-bounce function is enabled 0 = The bit[n] de-bounce function is disabled The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 9 - 9 (1 bit)
access : read-write

DBEN10 : Port [A/B/C/D/E] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 1 = The bit[n] de-bounce function is enabled 0 = The bit[n] de-bounce function is disabled The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 10 - 10 (1 bit)
access : read-write

DBEN11 : Port [A/B/C/D/E] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 1 = The bit[n] de-bounce function is enabled 0 = The bit[n] de-bounce function is disabled The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 11 - 11 (1 bit)
access : read-write

DBEN12 : Port [A/B/C/D/E] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 1 = The bit[n] de-bounce function is enabled 0 = The bit[n] de-bounce function is disabled The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 12 - 12 (1 bit)
access : read-write

DBEN13 : Port [A/B/C/D/E] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 1 = The bit[n] de-bounce function is enabled 0 = The bit[n] de-bounce function is disabled The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 13 - 13 (1 bit)
access : read-write

DBEN14 : Port [A/B/C/D/E] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 1 = The bit[n] de-bounce function is enabled 0 = The bit[n] de-bounce function is disabled The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 14 - 14 (1 bit)
access : read-write

DBEN15 : Port [A/B/C/D/E] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt 1 = The bit[n] de-bounce function is enabled 0 = The bit[n] de-bounce function is disabled The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 15 - 15 (1 bit)
access : read-write


IMD

GPIO Port Interrupt Mode Control
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMD IMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMD0 IMD1 IMD2 IMD3 IMD4 IMD5 IMD6 IMD7 IMD8 IMD9 IMD10 IMD11 IMD12 IMD13 IMD14 IMD15

IMD0 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrup. 1 = Level trigger interrupt 0 = Edge trigger interrupt If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 0 - 0 (1 bit)
access : read-write

IMD1 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrup. 1 = Level trigger interrupt 0 = Edge trigger interrupt If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 1 - 1 (1 bit)
access : read-write

IMD2 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrup. 1 = Level trigger interrupt 0 = Edge trigger interrupt If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 2 - 2 (1 bit)
access : read-write

IMD3 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrup. 1 = Level trigger interrupt 0 = Edge trigger interrupt If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 3 - 3 (1 bit)
access : read-write

IMD4 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrup. 1 = Level trigger interrupt 0 = Edge trigger interrupt If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 4 - 4 (1 bit)
access : read-write

IMD5 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrup. 1 = Level trigger interrupt 0 = Edge trigger interrupt If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 5 - 5 (1 bit)
access : read-write

IMD6 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrup. 1 = Level trigger interrupt 0 = Edge trigger interrupt If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 6 - 6 (1 bit)
access : read-write

IMD7 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrup. 1 = Level trigger interrupt 0 = Edge trigger interrupt If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 7 - 7 (1 bit)
access : read-write

IMD8 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrup. 1 = Level trigger interrupt 0 = Edge trigger interrupt If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 8 - 8 (1 bit)
access : read-write

IMD9 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrup. 1 = Level trigger interrupt 0 = Edge trigger interrupt If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 9 - 9 (1 bit)
access : read-write

IMD10 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrup. 1 = Level trigger interrupt 0 = Edge trigger interrupt If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 10 - 10 (1 bit)
access : read-write

IMD11 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrup. 1 = Level trigger interrupt 0 = Edge trigger interrupt If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 11 - 11 (1 bit)
access : read-write

IMD12 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrup. 1 = Level trigger interrupt 0 = Edge trigger interrupt If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 12 - 12 (1 bit)
access : read-write

IMD13 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrup. 1 = Level trigger interrupt 0 = Edge trigger interrupt If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 13 - 13 (1 bit)
access : read-write

IMD14 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrup. 1 = Level trigger interrupt 0 = Edge trigger interrupt If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 14 - 14 (1 bit)
access : read-write

IMD15 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrup. 1 = Level trigger interrupt 0 = Edge trigger interrupt If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 15 - 15 (1 bit)
access : read-write


IEN

GPIO Port Interrupt Enable
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IF_EN0 IF_EN1 IF_EN2 IF_EN3 IF_EN4 IF_EN5 IF_EN6 IF_EN7 IF_EN8 IF_EN9 IF_EN10 IF_EN11 IF_EN12 IF_EN13 IF_EN14 IF_EN15 IR_EN0 IR_EN1 IR_EN2 IR_EN3 IR_EN4 IR_EN5 IR_EN6 IR_EN7 IR_EN8 IR_EN9 IR_EN10 IR_EN11 IR_EN12 IR_EN13 IR_EN14 IR_EN15

IF_EN0 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. 1 = Enable the PIN[n] state low-level or high-to-low change interrupt 0 = Disable the PIN[n] state low-level or high-to-low change interrupt
bits : 0 - 0 (1 bit)
access : read-write

IF_EN1 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. 1 = Enable the PIN[n] state low-level or high-to-low change interrupt 0 = Disable the PIN[n] state low-level or high-to-low change interrupt
bits : 1 - 1 (1 bit)
access : read-write

IF_EN2 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. 1 = Enable the PIN[n] state low-level or high-to-low change interrupt 0 = Disable the PIN[n] state low-level or high-to-low change interrupt
bits : 2 - 2 (1 bit)
access : read-write

IF_EN3 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. 1 = Enable the PIN[n] state low-level or high-to-low change interrupt 0 = Disable the PIN[n] state low-level or high-to-low change interrupt
bits : 3 - 3 (1 bit)
access : read-write

IF_EN4 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. 1 = Enable the PIN[n] state low-level or high-to-low change interrupt 0 = Disable the PIN[n] state low-level or high-to-low change interrupt
bits : 4 - 4 (1 bit)
access : read-write

IF_EN5 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. 1 = Enable the PIN[n] state low-level or high-to-low change interrupt 0 = Disable the PIN[n] state low-level or high-to-low change interrupt
bits : 5 - 5 (1 bit)
access : read-write

IF_EN6 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. 1 = Enable the PIN[n] state low-level or high-to-low change interrupt 0 = Disable the PIN[n] state low-level or high-to-low change interrupt
bits : 6 - 6 (1 bit)
access : read-write

IF_EN7 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. 1 = Enable the PIN[n] state low-level or high-to-low change interrupt 0 = Disable the PIN[n] state low-level or high-to-low change interrupt
bits : 7 - 7 (1 bit)
access : read-write

IF_EN8 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. 1 = Enable the PIN[n] state low-level or high-to-low change interrupt 0 = Disable the PIN[n] state low-level or high-to-low change interrupt
bits : 8 - 8 (1 bit)
access : read-write

IF_EN9 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. 1 = Enable the PIN[n] state low-level or high-to-low change interrupt 0 = Disable the PIN[n] state low-level or high-to-low change interrupt
bits : 9 - 9 (1 bit)
access : read-write

IF_EN10 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. 1 = Enable the PIN[n] state low-level or high-to-low change interrupt 0 = Disable the PIN[n] state low-level or high-to-low change interrupt
bits : 10 - 10 (1 bit)
access : read-write

IF_EN11 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. 1 = Enable the PIN[n] state low-level or high-to-low change interrupt 0 = Disable the PIN[n] state low-level or high-to-low change interrupt
bits : 11 - 11 (1 bit)
access : read-write

IF_EN12 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. 1 = Enable the PIN[n] state low-level or high-to-low change interrupt 0 = Disable the PIN[n] state low-level or high-to-low change interrupt
bits : 12 - 12 (1 bit)
access : read-write

IF_EN13 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. 1 = Enable the PIN[n] state low-level or high-to-low change interrupt 0 = Disable the PIN[n] state low-level or high-to-low change interrupt
bits : 13 - 13 (1 bit)
access : read-write

IF_EN14 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. 1 = Enable the PIN[n] state low-level or high-to-low change interrupt 0 = Disable the PIN[n] state low-level or high-to-low change interrupt
bits : 14 - 14 (1 bit)
access : read-write

IF_EN15 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. 1 = Enable the PIN[n] state low-level or high-to-low change interrupt 0 = Disable the PIN[n] state low-level or high-to-low change interrupt
bits : 15 - 15 (1 bit)
access : read-write

IR_EN0 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt. 1 = Enable the PIN[n] level-high or low-to-high interrupt 0 = Disable the PIN[n] level-high or low-to-high interrupt.
bits : 16 - 16 (1 bit)
access : read-write

IR_EN1 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt. 1 = Enable the PIN[n] level-high or low-to-high interrupt 0 = Disable the PIN[n] level-high or low-to-high interrupt.
bits : 17 - 17 (1 bit)
access : read-write

IR_EN2 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt. 1 = Enable the PIN[n] level-high or low-to-high interrupt 0 = Disable the PIN[n] level-high or low-to-high interrupt.
bits : 18 - 18 (1 bit)
access : read-write

IR_EN3 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt. 1 = Enable the PIN[n] level-high or low-to-high interrupt 0 = Disable the PIN[n] level-high or low-to-high interrupt.
bits : 19 - 19 (1 bit)
access : read-write

IR_EN4 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt. 1 = Enable the PIN[n] level-high or low-to-high interrupt 0 = Disable the PIN[n] level-high or low-to-high interrupt.
bits : 20 - 20 (1 bit)
access : read-write

IR_EN5 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt. 1 = Enable the PIN[n] level-high or low-to-high interrupt 0 = Disable the PIN[n] level-high or low-to-high interrupt.
bits : 21 - 21 (1 bit)
access : read-write

IR_EN6 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt. 1 = Enable the PIN[n] level-high or low-to-high interrupt 0 = Disable the PIN[n] level-high or low-to-high interrupt.
bits : 22 - 22 (1 bit)
access : read-write

IR_EN7 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt. 1 = Enable the PIN[n] level-high or low-to-high interrupt 0 = Disable the PIN[n] level-high or low-to-high interrupt.
bits : 23 - 23 (1 bit)
access : read-write

IR_EN8 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt. 1 = Enable the PIN[n] level-high or low-to-high interrupt 0 = Disable the PIN[n] level-high or low-to-high interrupt.
bits : 24 - 24 (1 bit)
access : read-write

IR_EN9 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt. 1 = Enable the PIN[n] level-high or low-to-high interrupt 0 = Disable the PIN[n] level-high or low-to-high interrupt.
bits : 25 - 25 (1 bit)
access : read-write

IR_EN10 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt. 1 = Enable the PIN[n] level-high or low-to-high interrupt 0 = Disable the PIN[n] level-high or low-to-high interrupt.
bits : 26 - 26 (1 bit)
access : read-write

IR_EN11 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt. 1 = Enable the PIN[n] level-high or low-to-high interrupt 0 = Disable the PIN[n] level-high or low-to-high interrupt.
bits : 27 - 27 (1 bit)
access : read-write

IR_EN12 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt. 1 = Enable the PIN[n] level-high or low-to-high interrupt 0 = Disable the PIN[n] level-high or low-to-high interrupt.
bits : 28 - 28 (1 bit)
access : read-write

IR_EN13 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt. 1 = Enable the PIN[n] level-high or low-to-high interrupt 0 = Disable the PIN[n] level-high or low-to-high interrupt.
bits : 29 - 29 (1 bit)
access : read-write

IR_EN14 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt. 1 = Enable the PIN[n] level-high or low-to-high interrupt 0 = Disable the PIN[n] level-high or low-to-high interrupt.
bits : 30 - 30 (1 bit)
access : read-write

IR_EN15 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wakeup function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt. 1 = Enable the PIN[n] level-high or low-to-high interrupt 0 = Disable the PIN[n] level-high or low-to-high interrupt.
bits : 31 - 31 (1 bit)
access : read-write


ISRC

GPIO Port Interrupt Trigger Source Indicator
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISRC ISRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISRC0 ISRC1 ISRC2 ISRC3 ISRC4 ISRC5 ISRC6 ISRC7 ISRC8 ISRC9 ISRC10 ISRC11 ISRC12 ISRC13 ISRC14 ISRC15

ISRC0 : Port [A/B/C/D/E] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generate an interrupt 0 = No interrupt at GPIOx[n] Write : 1= Clear the correspond pending interrupt 0= No action
bits : 0 - 0 (1 bit)
access : read-write

ISRC1 : Port [A/B/C/D/E] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generate an interrupt 0 = No interrupt at GPIOx[n] Write : 1= Clear the correspond pending interrupt 0= No action
bits : 1 - 1 (1 bit)
access : read-write

ISRC2 : Port [A/B/C/D/E] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generate an interrupt 0 = No interrupt at GPIOx[n] Write : 1= Clear the correspond pending interrupt 0= No action
bits : 2 - 2 (1 bit)
access : read-write

ISRC3 : Port [A/B/C/D/E] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generate an interrupt 0 = No interrupt at GPIOx[n] Write : 1= Clear the correspond pending interrupt 0= No action
bits : 3 - 3 (1 bit)
access : read-write

ISRC4 : Port [A/B/C/D/E] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generate an interrupt 0 = No interrupt at GPIOx[n] Write : 1= Clear the correspond pending interrupt 0= No action
bits : 4 - 4 (1 bit)
access : read-write

ISRC5 : Port [A/B/C/D/E] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generate an interrupt 0 = No interrupt at GPIOx[n] Write : 1= Clear the correspond pending interrupt 0= No action
bits : 5 - 5 (1 bit)
access : read-write

ISRC6 : Port [A/B/C/D/E] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generate an interrupt 0 = No interrupt at GPIOx[n] Write : 1= Clear the correspond pending interrupt 0= No action
bits : 6 - 6 (1 bit)
access : read-write

ISRC7 : Port [A/B/C/D/E] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generate an interrupt 0 = No interrupt at GPIOx[n] Write : 1= Clear the correspond pending interrupt 0= No action
bits : 7 - 7 (1 bit)
access : read-write

ISRC8 : Port [A/B/C/D/E] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generate an interrupt 0 = No interrupt at GPIOx[n] Write : 1= Clear the correspond pending interrupt 0= No action
bits : 8 - 8 (1 bit)
access : read-write

ISRC9 : Port [A/B/C/D/E] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generate an interrupt 0 = No interrupt at GPIOx[n] Write : 1= Clear the correspond pending interrupt 0= No action
bits : 9 - 9 (1 bit)
access : read-write

ISRC10 : Port [A/B/C/D/E] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generate an interrupt 0 = No interrupt at GPIOx[n] Write : 1= Clear the correspond pending interrupt 0= No action
bits : 10 - 10 (1 bit)
access : read-write

ISRC11 : Port [A/B/C/D/E] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generate an interrupt 0 = No interrupt at GPIOx[n] Write : 1= Clear the correspond pending interrupt 0= No action
bits : 11 - 11 (1 bit)
access : read-write

ISRC12 : Port [A/B/C/D/E] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generate an interrupt 0 = No interrupt at GPIOx[n] Write : 1= Clear the correspond pending interrupt 0= No action
bits : 12 - 12 (1 bit)
access : read-write

ISRC13 : Port [A/B/C/D/E] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generate an interrupt 0 = No interrupt at GPIOx[n] Write : 1= Clear the correspond pending interrupt 0= No action
bits : 13 - 13 (1 bit)
access : read-write

ISRC14 : Port [A/B/C/D/E] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generate an interrupt 0 = No interrupt at GPIOx[n] Write : 1= Clear the correspond pending interrupt 0= No action
bits : 14 - 14 (1 bit)
access : read-write

ISRC15 : Port [A/B/C/D/E] Interrupt Trigger Source Indicator Read : 1 = Indicates GPIOx[n] generate an interrupt 0 = No interrupt at GPIOx[n] Write : 1= Clear the correspond pending interrupt 0= No action
bits : 15 - 15 (1 bit)
access : read-write


OFFD

GPIO Port Pin OFF Digital Enable
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFD OFFD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFD

OFFD : GPIOx Pin[n] OFF digital input path Enable Each of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, users can OFF digital input path to avoid creepage 1 = Disable IO digital input path (digital input tied to low) 0 = Enable IO digital input path
bits : 16 - 31 (16 bit)
access : read-write


DOUT

GPIO Port Data Output Value
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOUT DOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 DOUT8 DOUT9 DOUT10 DOUT11 DOUT12 DOUT13 DOUT14 DOUT15

DOUT0 : GPIOx Pin[n] Output Value Each of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode. 1 = GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode. 0 = GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode.
bits : 0 - 0 (1 bit)
access : read-write

DOUT1 : GPIOx Pin[n] Output Value Each of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode. 1 = GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode. 0 = GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode.
bits : 1 - 1 (1 bit)
access : read-write

DOUT2 : GPIOx Pin[n] Output Value Each of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode. 1 = GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode. 0 = GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode.
bits : 2 - 2 (1 bit)
access : read-write

DOUT3 : GPIOx Pin[n] Output Value Each of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode. 1 = GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode. 0 = GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode.
bits : 3 - 3 (1 bit)
access : read-write

DOUT4 : GPIOx Pin[n] Output Value Each of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode. 1 = GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode. 0 = GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode.
bits : 4 - 4 (1 bit)
access : read-write

DOUT5 : GPIOx Pin[n] Output Value Each of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode. 1 = GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode. 0 = GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode.
bits : 5 - 5 (1 bit)
access : read-write

DOUT6 : GPIOx Pin[n] Output Value Each of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode. 1 = GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode. 0 = GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode.
bits : 6 - 6 (1 bit)
access : read-write

DOUT7 : GPIOx Pin[n] Output Value Each of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode. 1 = GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode. 0 = GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode.
bits : 7 - 7 (1 bit)
access : read-write

DOUT8 : GPIOx Pin[n] Output Value Each of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode. 1 = GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode. 0 = GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode.
bits : 8 - 8 (1 bit)
access : read-write

DOUT9 : GPIOx Pin[n] Output Value Each of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode. 1 = GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode. 0 = GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode.
bits : 9 - 9 (1 bit)
access : read-write

DOUT10 : GPIOx Pin[n] Output Value Each of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode. 1 = GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode. 0 = GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode.
bits : 10 - 10 (1 bit)
access : read-write

DOUT11 : GPIOx Pin[n] Output Value Each of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode. 1 = GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode. 0 = GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode.
bits : 11 - 11 (1 bit)
access : read-write

DOUT12 : GPIOx Pin[n] Output Value Each of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode. 1 = GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode. 0 = GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode.
bits : 12 - 12 (1 bit)
access : read-write

DOUT13 : GPIOx Pin[n] Output Value Each of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode. 1 = GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode. 0 = GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode.
bits : 13 - 13 (1 bit)
access : read-write

DOUT14 : GPIOx Pin[n] Output Value Each of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode. 1 = GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode. 0 = GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode.
bits : 14 - 14 (1 bit)
access : read-write

DOUT15 : GPIOx Pin[n] Output Value Each of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode. 1 = GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode. 0 = GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode.
bits : 15 - 15 (1 bit)
access : read-write


DMASK

GPIO Port Data Output Write Mask
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMASK DMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMASK0 DMASK1 DMASK2 DMASK3 DMASK4 DMASK5 DMASK6 DMASK7 DMASK8 DMASK9 DMASK10 DMASK11 DMASK12 DMASK13 DMASK14 DMASK15

DMASK0 : Port [A/B/C/D/E] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to"1", the corresponding GPIOx_DOUTn bit is protected. The write signal is masked, write data to the protect bit is ignored 1 = The corresponding GPIOx_DOUT[n] bit is protected 0 = The corresponding GPIOx_DOUT[n] bit can be updated
bits : 0 - 0 (1 bit)
access : read-write

DMASK1 : Port [A/B/C/D/E] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to"1", the corresponding GPIOx_DOUTn bit is protected. The write signal is masked, write data to the protect bit is ignored 1 = The corresponding GPIOx_DOUT[n] bit is protected 0 = The corresponding GPIOx_DOUT[n] bit can be updated
bits : 1 - 1 (1 bit)
access : read-write

DMASK2 : Port [A/B/C/D/E] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to"1", the corresponding GPIOx_DOUTn bit is protected. The write signal is masked, write data to the protect bit is ignored 1 = The corresponding GPIOx_DOUT[n] bit is protected 0 = The corresponding GPIOx_DOUT[n] bit can be updated
bits : 2 - 2 (1 bit)
access : read-write

DMASK3 : Port [A/B/C/D/E] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to"1", the corresponding GPIOx_DOUTn bit is protected. The write signal is masked, write data to the protect bit is ignored 1 = The corresponding GPIOx_DOUT[n] bit is protected 0 = The corresponding GPIOx_DOUT[n] bit can be updated
bits : 3 - 3 (1 bit)
access : read-write

DMASK4 : Port [A/B/C/D/E] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to"1", the corresponding GPIOx_DOUTn bit is protected. The write signal is masked, write data to the protect bit is ignored 1 = The corresponding GPIOx_DOUT[n] bit is protected 0 = The corresponding GPIOx_DOUT[n] bit can be updated
bits : 4 - 4 (1 bit)
access : read-write

DMASK5 : Port [A/B/C/D/E] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to"1", the corresponding GPIOx_DOUTn bit is protected. The write signal is masked, write data to the protect bit is ignored 1 = The corresponding GPIOx_DOUT[n] bit is protected 0 = The corresponding GPIOx_DOUT[n] bit can be updated
bits : 5 - 5 (1 bit)
access : read-write

DMASK6 : Port [A/B/C/D/E] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to"1", the corresponding GPIOx_DOUTn bit is protected. The write signal is masked, write data to the protect bit is ignored 1 = The corresponding GPIOx_DOUT[n] bit is protected 0 = The corresponding GPIOx_DOUT[n] bit can be updated
bits : 6 - 6 (1 bit)
access : read-write

DMASK7 : Port [A/B/C/D/E] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to"1", the corresponding GPIOx_DOUTn bit is protected. The write signal is masked, write data to the protect bit is ignored 1 = The corresponding GPIOx_DOUT[n] bit is protected 0 = The corresponding GPIOx_DOUT[n] bit can be updated
bits : 7 - 7 (1 bit)
access : read-write

DMASK8 : Port [A/B/C/D/E] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to"1", the corresponding GPIOx_DOUTn bit is protected. The write signal is masked, write data to the protect bit is ignored 1 = The corresponding GPIOx_DOUT[n] bit is protected 0 = The corresponding GPIOx_DOUT[n] bit can be updated
bits : 8 - 8 (1 bit)
access : read-write

DMASK9 : Port [A/B/C/D/E] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to"1", the corresponding GPIOx_DOUTn bit is protected. The write signal is masked, write data to the protect bit is ignored 1 = The corresponding GPIOx_DOUT[n] bit is protected 0 = The corresponding GPIOx_DOUT[n] bit can be updated
bits : 9 - 9 (1 bit)
access : read-write

DMASK10 : Port [A/B/C/D/E] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to"1", the corresponding GPIOx_DOUTn bit is protected. The write signal is masked, write data to the protect bit is ignored 1 = The corresponding GPIOx_DOUT[n] bit is protected 0 = The corresponding GPIOx_DOUT[n] bit can be updated
bits : 10 - 10 (1 bit)
access : read-write

DMASK11 : Port [A/B/C/D/E] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to"1", the corresponding GPIOx_DOUTn bit is protected. The write signal is masked, write data to the protect bit is ignored 1 = The corresponding GPIOx_DOUT[n] bit is protected 0 = The corresponding GPIOx_DOUT[n] bit can be updated
bits : 11 - 11 (1 bit)
access : read-write

DMASK12 : Port [A/B/C/D/E] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to"1", the corresponding GPIOx_DOUTn bit is protected. The write signal is masked, write data to the protect bit is ignored 1 = The corresponding GPIOx_DOUT[n] bit is protected 0 = The corresponding GPIOx_DOUT[n] bit can be updated
bits : 12 - 12 (1 bit)
access : read-write

DMASK13 : Port [A/B/C/D/E] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to"1", the corresponding GPIOx_DOUTn bit is protected. The write signal is masked, write data to the protect bit is ignored 1 = The corresponding GPIOx_DOUT[n] bit is protected 0 = The corresponding GPIOx_DOUT[n] bit can be updated
bits : 13 - 13 (1 bit)
access : read-write

DMASK14 : Port [A/B/C/D/E] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to"1", the corresponding GPIOx_DOUTn bit is protected. The write signal is masked, write data to the protect bit is ignored 1 = The corresponding GPIOx_DOUT[n] bit is protected 0 = The corresponding GPIOx_DOUT[n] bit can be updated
bits : 14 - 14 (1 bit)
access : read-write

DMASK15 : Port [A/B/C/D/E] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to"1", the corresponding GPIOx_DOUTn bit is protected. The write signal is masked, write data to the protect bit is ignored 1 = The corresponding GPIOx_DOUT[n] bit is protected 0 = The corresponding GPIOx_DOUT[n] bit can be updated
bits : 15 - 15 (1 bit)
access : read-write



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