CON

TXFIFO

RXFIFO

CLKDIV

IE

STATUS

I2SEN : Enable I2S Controller 1 = Enable 0 = Disable
bits : 0 - 0 (1 bit)
access : read-write

TXEN : Transmit Enable 1 = Enable data transmit 0 = Disable data transmit
bits : 1 - 1 (1 bit)
access : read-write

RXEN : Receive Enable 1 = Enable data receive 0 = Disable data receive
bits : 2 - 2 (1 bit)
access : read-write

MUTE : Transmit Mute Enable 1 = Transmit channel zero 0 = Transmit data is shifted from buffer
bits : 3 - 3 (1 bit)
access : read-write

WORDWIDTH : Word Width 00 = data is 8 bit 01 = data is 16 bit 10 = data is 24 bit 11 = data is 32 bit
bits : 4 - 5 (2 bit)
access : read-write

MONO : Monaural Data 1 = Data is monaural format 0 = Data is stereo format
bits : 6 - 6 (1 bit)
access : read-write

FORMAT : Data Format 1 = MSB justified data format 0 = I2S data format
bits : 7 - 7 (1 bit)
access : read-write

SLAVE : Slave Mode I2S can operate as master or slave. For master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro(TM) NUC100 series to Audio CODEC chip. In slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip. 1 = Slave mode 0 = Master mode
bits : 8 - 8 (1 bit)
access : read-write

TXTH : Transmit FIFO Threshold Level If remain data word (32 bits) in transmit FIFO is the same or less than threshold level then TXTHI flag is set. 000 = 0 word data in transmit FIFO 001 = 1 word data in transmit FIFO 010 = 2 words data in transmit FIFO 011 = 3 words data in transmit FIFO 100 = 4 word data in transmit FIFO 101 = 5 word data in transmit FIFO 110 = 6 word data in transmit FIFO 111 = 7 word data in transmit FIFO
bits : 9 - 11 (3 bit)
access : read-write

RXTH : Receive FIFO Threshold Level When received data word(s) in buffer is equal or higher than threshold level then RXTHI flag is set. 000 = 1 word data in receive FIFO 001 = 2 word data in receive FIFO 010 = 3 word data in receive FIFO 011 = 4 word data in receive FIFO 100 = 5 word data in receive FIFO 101 = 6 word data in receive FIFO 110 = 7 word data in receive FIFO 111 = 8 word data in receive FIFO
bits : 12 - 14 (3 bit)
access : read-write

MCLKEN : Master Clock Enable If NuMicro(TM) NUC100 series external crystal clock is frequency 2*N*256fs then software can program MCLK_DIV[2:0] in I2S_CLKDIV register to get 256fs clock to audio codec chip. 1 = Enable master clock 0 = Disable master clock
bits : 15 - 15 (1 bit)
access : read-write

RCHZCEN : Right channel zero cross detect enable If this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then RZCF flag in I2S_STATUS register is set to 1. 1 = Enable right channel zero cross detect 0 = Disable right channel zero cross detect
bits : 16 - 16 (1 bit)
access : read-write

LCHZCEN : Left channel zero cross detect enable If this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCF flag in I2S_STATUS register is set to 1. 1 = Enable left channel zero cross detect 0 = Disable left channel zero cross detect
bits : 17 - 17 (1 bit)
access : read-write

CLR_TXFIFO : Clear Transmit FIFO Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXFIFO_LEVEL[3:0] returns to zero and transmit FIFO becomes empty but data in transmit FIFO is not changed. This bit is clear by hardware automatically, read it return zero.
bits : 18 - 18 (1 bit)
access : read-write

CLR_RXFIFO : Clear Receive FIFO Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXFIFO_LEVEL[3:0] returns to zero and receive FIFO becomes empty. This bit is clear by hardware automatically, read it return zero.
bits : 19 - 19 (1 bit)
access : read-write

TXDMA : Enable Transmit DMA When TX DMA is enabled, I2S requests DMA to transfer data from SRAM to transmit FIFO if FIFO is not full. 1 = Enable TX DMA 0 = Disable TX DMA
bits : 20 - 20 (1 bit)
access : read-write

RXDMA : Enable Receive DMA When RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty. 1 = Enable RX DMA 0 = Disable RX DMA
bits : 21 - 21 (1 bit)
access : read-write

TXFIFO : Transmit FIFO register I2S contains 8 words (8x32 bit) data buffer for data transmit. Write data to this register to prepare data for transmit. The remain word number is indicated by TX_LEVEL[3:0] in I2S_STATUS.
bits : 0 - 31 (32 bit)
access : write-only

RXFIFO : Receive FIFO register I2S contains 8 words (8x32 bit) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RX_LEVEL[3:0] in I2S_STATUS register.
bits : 0 - 31 (32 bit)
access : read-only

MCLK_DIV : Master Clock Divider If chip external crystal frequency is (2xMCLK_DIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. If MCLK_DIV is set to 0, MCLK is the same as external clock input. For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLK_DIV=1. F_MCLK = F_I2SCLK/(2x(MCLK_DIV)) (When MCLK_DIV is >= 1 ) F_MCLK = F_I2SCLK (When MCLK_DIV is set to 0 )
bits : 0 - 2 (3 bit)
access : read-write

BCLK_DIV : Bit Clock Divider If I2S operates in master mode, bit clock is provided by NuMicro(TM) NUC100 series. Software can program these bits to generate sampling rate clock frequency. F_BCLK = F_I2SCLK /(2x(BCLK_DIV + 1))
bits : 8 - 15 (8 bit)
access : read-write

RXUDFIE : Receive FIFO underflow interrupt enable If software read receive FIFO when it is empty then RXUDF flag in I2SSTATUS register is set to 1. 1 = Enable interrupt 0 = Disable interrupt
bits : 0 - 0 (1 bit)
access : read-write

RXOVFIE : Receive FIFO overflow interrupt enable 1 = Enable interrupt 0 = Disable interrupt
bits : 1 - 1 (1 bit)
access : read-write

RXTHIE : Receive FIFO threshold level interrupt When data word in receive FIFO is equal or higher then RXTH[2:0] and the RXTHI bit is set to 1. If RXTHIE bit is enabled, interrupt occur. 1 = Enable interrupt 0 = Disable interrupt
bits : 2 - 2 (1 bit)
access : read-write

TXUDFIE : Transmit FIFO underflow interrupt enable Interrupt occurs if this bit is set to 1 and transmit FIFO underflow flag is set to 1. 1 = Enable interrupt 0 = Disable interrupt
bits : 8 - 8 (1 bit)
access : read-write

TXOVFIE : Transmit FIFO overflow interrupt enable Interrupt occurs if this bit is set to 1 and transmit FIFO overflow flag is set to 1. 1 = Enable interrupt 0 = Disable interrupt
bits : 9 - 9 (1 bit)
access : read-write

TXTHIE : Transmit FIFO threshold level interrupt enable Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH[2:0]. 1 = Enable interrupt 0 = Disable interrupt
bits : 10 - 10 (1 bit)
access : read-write

RZCIE : Right channel zero cross interrupt enable Interrupt occurs if this bit is set to 1 and right channel zero cross. 1 = Enable interrupt 0 = Disable interrupt
bits : 11 - 11 (1 bit)
access : read-write

LZCIE : Left channel zero cross interrupt enable Interrupt occurs if this bit is set to 1 and left channel zero cross. 1 = Enable interrupt 0 = Disable interrupt
bits : 12 - 12 (1 bit)
access : read-write

I2SINT : I2S Interrupt flag 1 = I2S interrupt 0 = No I2S interrup It is wire-OR of I2STXINT and I2SRXINT bits. This bit is read only.
bits : 0 - 0 (1 bit)
access : read-only

I2SRXINT : I2S receive interrupt 1 = Receive interrupt 0 = No receive interrupt This bit is read only
bits : 1 - 1 (1 bit)
access : read-only

I2STXINT : I2S transmit interrupt 1 = Transmit interrupt 0 = No transmit interrupt This bit is read only
bits : 2 - 2 (1 bit)
access : read-only

RIGHT : Right channel This bit indicate current transmit data is belong to right channel. 1 = Right channel 0 = Left channel This bit is read only.
bits : 3 - 3 (1 bit)
access : read-only

RXUDF : Receive FIFO underflow flag Read receive FIFO when it is empty, this bit set to 1 indicate underflow occur. 1 = Underflow occur 0 = No underflow occur Write 1 to clear this bit.
bits : 8 - 8 (1 bit)
access : read-write

RXOVF : Receive FIFO overflow flag When receive FIFO is full and receive hardware attempt write to data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote. 1 = Overflow occur 0 = No overflow occur Write 1 to clear this bit.
bits : 9 - 9 (1 bit)
access : read-write

RXTHF : Receive FIFO threshold flag When data word(s) in receive FIFO is equal or higher than threshold value set in RXTH[2:0] the RXTHF bit becomes to 1. It keeps at 1 till RXFIFO_LEVEL[3:0] less than RXTH[1:0] after software read RXFIFO register. 1 = Data word(s) in FIFO is equal or higher than threshold level 0 = Data word(s) in FIFO is lower than threshold level This bit is read only.
bits : 10 - 10 (1 bit)
access : read-only

RXFULL : Receive FIFO full This bit reflect data words number in receive FIFO is 8. 1 = Full 0 = Not full This bit is read only.
bits : 11 - 11 (1 bit)
access : read-only

RXEMPTY : Receive FIFO empty This bit reflects data words number in receive FIFO is zero. 1 = Empty 0 = Not empty This bit is read only.
bits : 12 - 12 (1 bit)
access : read-only

TXUDF : Transmit FIFO underflow flag When transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1. 1 = Underflow 0 = No underflow Software can write 1 to clear this bit.
bits : 16 - 16 (1 bit)
access : read-write

TXOVF : Transmit FIFO overflow flag Write data to transmit FIFO when it is full and this bit set to 1. 1 = Overflow 0 = No overflow Software can write 1 to clear this bit.
bits : 17 - 17 (1 bit)
access : read-write

TXTHF : Transmit FIFO threshold flag When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH[2:0] the TXTHF bit becomes to 1. It keeps at 1 till TXFIFO_LEVEL[3:0] is higher than TXTH[1:0] after software write TXFIFO register. 1 = Data word(s) in FIFO is equal or lower than threshold level 0 = Data word(s) in FIFO is higher than threshold level This bit is read only.
bits : 18 - 18 (1 bit)
access : read-only

TXFULL : Transmit FIFO full This bit reflect data word number in transmit FIFO is 8. 1 = Full 0 = Not full This bit is read only.
bits : 19 - 19 (1 bit)
access : read-only

TXEMPTY : Transmit FIFO empty This bit reflect data word number in transmit FIFO is zero. 1 = Empty 0 = Not empty This bit is read only.
bits : 20 - 20 (1 bit)
access : read-only

TXBUSY : Transmit Busy This bit is clear to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer. 1 = Transmit shift buffer is busy 0 = Transmit shift buffer is empty This bit is read only.
bits : 21 - 21 (1 bit)
access : read-only

RZCF : Right channel zero cross flag It indicates right channel next sample data sign bit is changed or all data bits are zero. 1 = Right channel zero cross is detected 0 = No zero cross Software can write 1 to clear this bit to zero.
bits : 22 - 22 (1 bit)
access : read-write

LZCF : Left channel zero cross flag It indicates left channel next sample data sign bit is changed or all data bits are zero. 1 = Left channel zero cross is detected 0 = No zero cross Software can write 1 to clear this bit to zero.
bits : 23 - 23 (1 bit)
access : read-write

RX_LEVEL : Receive FIFO level These bits indicate word number in receive FIFO. 0000 = No data 0001 = 1 word in receive FIFO 0010 = 2 word in receive FIFO 0011 = 3 word in receive FIFO 0100 = 4 word in receive FIFO 0101 = 5 word in receive FIFO 0110 = 6 word in receive FIFO 0111 = 7 word in receive FIFO 1000 = 8 word in receive FIFO
bits : 24 - 27 (4 bit)
access : read-only

TX_LEVEL : Transmit FIFO level These bits indicate word number in Transmit FIFO. 0000 = No data 0001 = 1 word in Transmit FIFO 0010 = 2 word in Transmit FIFO 0011 = 3 word in Transmit FIFO 0100 = 4 word in Transmit FIFO 0101 = 5 word in Transmit FIFO 0110 = 6 word in Transmit FIFO 0111 = 7 word in Transmit FIFO 1000 = 8 word in Transmit FIFO
bits : 28 - 31 (4 bit)
access : read-only