\n
address_offset : 0x0 Bytes (0x0)
size : 0x88 byte (0x0)
mem_usage : registers
protection : not protected
MCU IRQ0 (BOD) interrupt source identify
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: BOD_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ4 (GPA/B) interrupt source identify
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: GPB_INT Bit0: GPA_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ5 (GPC/D/E) interrupt source identify
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: GPE_INT Bit1: GPD_INT Bit0: GPC_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ6 (PWMA) interrupt source identify
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit3: PWM3_INT Bit2: PWM2_INT Bit1: PWM1_INT Bit0: PWM0_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ7 (PWMB) interrupt source identify
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit3: PWM7_INT Bit2: PWM6_INT Bit1: PWM5_INT Bit0: PWM4_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ8 (TMR0) interrupt source identify
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: TMR0_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ9 (TMR1) interrupt source identify
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: TMR1_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ10 (TMR2) interrupt source identify
address_offset : 0x28 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: TMR2_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ11 (TMR3) interrupt source identify
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: TMR3_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ12 (URT0) interrupt source identify
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: URT0_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ13 (URT1) interrupt source identify
address_offset : 0x34 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: URT1_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ14 (SPI0) interrupt source identify
address_offset : 0x38 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: SPI0_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ15 (SPI1) interrupt source identify
address_offset : 0x3C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: SPI1_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ1 (WDG) interrupt source identify
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: WDG_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ16 (SPI2) interrupt source identify
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: SPI2_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ17 (SPI3) interrupt source identify
address_offset : 0x44 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: SPI3_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ18 (I2C0) interrupt source identify
address_offset : 0x48 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: I2C0_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ19 (I2C1) interrupt source identify
address_offset : 0x4C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: I2C1_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ20 (CAN0) interrupt source identify
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: CAN0_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ21 (Reserved) interrupt source identity
address_offset : 0x54 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Reserved
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ22 (Reserved) interrupt source identify
address_offset : 0x58 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Reserved
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ23 (USBD) interrupt source identify
address_offset : 0x5C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: USBD_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ24 (PS2) interrupt source identify
address_offset : 0x60 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: PS2_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ25 (ACMP) interrupt source identify
address_offset : 0x64 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: ACMP_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ26 (PDMA) interrupt source identify
address_offset : 0x68 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: PDMA_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ27 (Reserved) interrupt source identify
address_offset : 0x6C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: I2S_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ28 (PWRWU) interrupt source identify
address_offset : 0x70 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: PWRWU_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ29 (ADC) interrupt source identify
address_offset : 0x74 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: ADC_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ30 (Reserved) interrupt source identify
address_offset : 0x78 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Reserved
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ31 (RTC) interrupt source identify
address_offset : 0x7C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: RTC_INT
bits : 0 - 2 (3 bit)
access : read-only
MCU IRQ2 (EINT0) interrupt source identify
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: EINT0 - external interrupt 0 from PB.14
bits : 0 - 2 (3 bit)
access : read-only
NMI source interrupt select control register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMI_SEL : The NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL.
bits : 0 - 4 (5 bit)
access : read-write
MCU IRQ Number identify register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_IRQ : MCU IRQ Source Register The MCU_IRQ collect all the interrupts from the peripherals and generate the synchronous interrupt to MCU Cortex-M0. There are two modes to generate interrupt to MCU Cortex-M0, the normal mode and test mode. The MCU_IRQ collect all interrupt from each peripheral and synchronize them then interrupt the Cortex-M0. When the MCU_IRQ[n] is "0": Set MCU_IRQ[n] "1" will generate a interrupt to Cortex_M0 NVIC[n]. When the MCU_IRQ[n] is "1" (mean a interrupt is assert) set "1" to the MCU_bit[n] will clear the interrupt. Set MCU_IRQ[n] "0": no any effect
bits : 0 - 31 (32 bit)
access : read-write
MCU IRQ3 (EINT1) interrupt source identify
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 Bit1: 0 Bit0: EINT1 - external interrupt 1 from PB.15
bits : 0 - 2 (3 bit)
access : read-only
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