PDMA_CSRx

PDMA_POINTx

PDMA_CSARx

PDMA_CDARx

PDMA_CBCRx

PDMA_IERx

PDMA_ISRx

PDMA_SARx

PDMA_DARx

PDMA_SBUF0_cx

PDMA_BCRx

PDMACEN : PDMA Channel Enable Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. Note: SW_RST(PDMA_CSRx[1], x= 0~8) will clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

SW_RST : Software Engine Reset 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit will reset the internal state machine and pointers. The contents of control register will not be cleared. This bit will auto clear after few clock cycles.
bits : 1 - 1 (1 bit)
access : read-write

MODE_SEL : PDMA Mode Select 00 = Memory to Memory mode (Memory-to-Memory). 01 = IP to Memory mode (APB-to-Memory). 10 = Memory to IP mode (Memory-to-APB).
bits : 2 - 3 (2 bit)
access : read-write

SAD_SEL : Transfer Source Address Direction Select 00 = Transfer Source address is incremented successively. 01 = Reserved. 10 = Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations). 11 = Reserved.
bits : 4 - 5 (2 bit)
access : read-write

DAD_SEL : Transfer Destination Address Direction Select 00 = Transfer Destination address is incremented successively. 01 = Reserved. 10 = Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination). 11 = Reserved.
bits : 6 - 7 (2 bit)
access : read-write

APB_TWS : Peripheral transfer Width Select 00 = One word (32 bits) is transferred for every PDMA operation. 01 = One byte (8 bits) is transferred for every PDMA operation. 10 = One half-word (16 bits) is transferred for every PDMA operation. 11 = Reserved. Note: This field is meaningful only when MODE_SEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB).
bits : 19 - 20 (2 bit)
access : read-write

TRIG_EN : Trig_EN 0 = No effect. 1 = Enable PDMA data read or write transfer. Note: When PDMA transfer completed, this bit will be cleared automatically. If the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
bits : 23 - 23 (1 bit)
access : read-write

PDMA_POINT : PDMA Internal Buffer Pointer Register (Read Only) This field indicates the internal buffer pointer.
bits : 0 - 3 (4 bit)
access : read-only

PDMA_CSAR : PDMA Current Source Address Register (Read Only) This field indicates the source address where the PDMA transfer is just occurring.
bits : 0 - 31 (32 bit)
access : read-only

PDMA_CDAR : PDMA Current Destination Address Register (Read Only) This field indicates the destination address where the PDMA transfer is just occurring.
bits : 0 - 31 (32 bit)
access : read-only

PDMA_CBCR : PDMA Current Byte Count Register (Read Only) This field indicates the current remained byte count of PDMA. Note : SW_RST will clear this register value.
bits : 0 - 15 (16 bit)
access : read-only

TABORT_IE : PDMA Read/Write Target Abort Interrupt Enable 0 = Disable target abort interrupt generation during PDMA transfer. 1 = Enable target abort interrupt generation during PDMA transfer.
bits : 0 - 0 (1 bit)
access : read-write

BLKD_IE : PDMA Transfer Done Interrupt Enable 0 = Disable interrupt generator during PDMA transfer done. 1 = Enable interrupt generator during PDMA transfer done.
bits : 1 - 1 (1 bit)
access : read-write

TABORT_IF : PDMA Read/Write Target Abort Interrupt Flag 0 = No bus ERROR response received. 1 = Bus ERROR response received. NOTE: Software can write 1 to clear this bit to zero.
bits : 0 - 0 (1 bit)
access : read-write

BLKD_IF : Block Transfer Done Interrupt Flag This bit indicates that PDMA has finished all transfer. 0 = Not finished yet. 1 = Done. NOTE: Software can write 1 to clear this bit to zero.
bits : 1 - 1 (1 bit)
access : read-write

PDMA_SAR : PDMA Transfer Source Address Register This field indicates a 32-bit source address of PDMA. Note : The source address must be word alignment
bits : 0 - 31 (32 bit)
access : read-write

PDMA_DAR : PDMA Transfer Destination Address Register This field indicates a 32-bit destination address of PDMA. Note : The destination address must be word alignment
bits : 0 - 31 (32 bit)
access : read-write

PDMA_SBUF0 : PDMA Shared Buffer FIFO 0 (Read Only) Each channel has its own 1 word internal buffer.
bits : 0 - 31 (32 bit)
access : read-only

PDMA_BCR : PDMA Transfer Byte Count Register This field indicates a 16-bit transfer byte count of PDMA.it must be word alignment.
bits : 0 - 15 (16 bit)
access : read-write