\n

PDMA_GCR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PDMA_GCRCSR

PDSSR2

PDSSR0

PDSSR1

PDMA_GCRISR


PDMA_GCRCSR

PDMA Global Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_GCRCSR PDMA_GCRCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK0_EN CLK1_EN CLK2_EN CLK3_EN CLK4_EN CLK5_EN CLK6_EN CLK7_EN CLK8_EN

CLK0_EN : PDMA Controller Channel 0 Clock Enable Control 0 = Disable 1 = Enable
bits : 8 - 8 (1 bit)
access : read-write

CLK1_EN : PDMA Controller Channel 1 Clock Enable Control(Medium Density Only) 0 = Disable 1 = Enable
bits : 9 - 9 (1 bit)
access : read-write

CLK2_EN : PDMA Controller Channel 2 Clock Enable Control(Medium Density Only) 0 = Disable 1 = Enable
bits : 10 - 10 (1 bit)
access : read-write

CLK3_EN : PDMA Controller Channel 3 Clock Enable Control(Medium Density Only) 0 = Disable 1 = Enable
bits : 11 - 11 (1 bit)
access : read-write

CLK4_EN : PDMA Controller Channel 4 Clock Enable Control(Medium Density Only) 0 = Disable 1 = Enable
bits : 12 - 12 (1 bit)
access : read-write

CLK5_EN : PDMA Controller Channel 5 Clock Enable Control(Medium Density Only) 0 = Disable 1 = Enable
bits : 13 - 13 (1 bit)
access : read-write

CLK6_EN : PDMA Controller Channel 6 Clock Enable Control(Medium Density Only) 0 = Disable 1 = Enable
bits : 14 - 14 (1 bit)
access : read-write

CLK7_EN : PDMA Controller Channel 7 Clock Enable Control(Medium Density Only) 0 = Disable 1 = Enable
bits : 15 - 15 (1 bit)
access : read-write

CLK8_EN : PDMA Controller Channel 8 Clock Enable Control(Medium Density Only) 0 = Disable 1 = Enable
bits : 16 - 16 (1 bit)
access : read-write


PDSSR2

PDMA Service Selection Control Register 2
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDSSR2 PDSSR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2S_RXSEL I2S_TXSEL

I2S_RXSEL : PDMA I2S RX Selection This filed defines which PDMA channel is connected to the on-chip peripheral I2S RX. Software can change the channel RX setting by I2S_RXSEL 4'b0000: CH0 4'b0001: CH1 4'b0010: CH2 4'b0011: CH3 4'b0100: CH4 4'b0101: CH5 4'b0110: CH6 4'b0111: CH7 4'b1000: CH8 Others : Reserved Note : Ex : I2S_RXSEL = 4'b0110, that means I2S_RX is connected to PDMA_CH6(Low Density should set as 4'b0000 for PDMA channel 0 only)
bits : 0 - 3 (4 bit)
access : read-write

I2S_TXSEL : PDMA I2S TX Selection This filed defines which PDMA channel is connected to the on-chip peripheral I2S TX. Software can configure the TX channel setting by I2S_TXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL.
bits : 4 - 7 (4 bit)
access : read-write


PDSSR0

PDMA Service Selection Control Register 0
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDSSR0 PDSSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI0_RXSEL SPI0_TXSEL SPI1_RXSEL SPI1_TXSEL SPI2_RXSEL SPI2_TXSEL SPI3_RXSEL SPI3_TXSEL

SPI0_RXSEL : PDMA SPI0 RX Selection This filed defines which PDMA channel is connected to the on-chip peripheral SPI0 RX. Software can change the channel RX setting by SPI0_RXSEL 4'b0000: CH0 4'b0001: CH1 4'b0010: CH2 4'b0011: CH3 4'b0100: CH4 4'b0101: CH5 4'b0110: CH6 4'b0111: CH7 4'b1000: CH8 Others : Reserved Note : Ex : SPI0_RXSEL = 4'b0110, that means SPI0_RX is connected to PDMA_CH6(Low Density should set as 4'b0000 for PDMA channel 0 only)
bits : 0 - 3 (4 bit)
access : read-write

SPI0_TXSEL : PDMA SPI0 TX Selection This filed defines which PDMA channel is connected to the on-chip peripheral SPI0 TX. Software can configure the TX channel setting by SPI0_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
bits : 4 - 7 (4 bit)
access : read-write

SPI1_RXSEL : PDMA SPI1 RX Selection This filed defines which PDMA channel is connected to the on-chip peripheral SPI1 RX. Software can configure the RX channel setting by SPI1_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
bits : 8 - 11 (4 bit)
access : read-write

SPI1_TXSEL : PDMA SPI1 TX Selection This filed defines which PDMA channel is connected to the on-chip peripheral SPI1 TX. Software can configure the TX channel setting by SPI1_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
bits : 12 - 15 (4 bit)
access : read-write

SPI2_RXSEL : PDMA SPI2 RX Selection (Medium Density Only) This filed defines which PDMA channel is connected to the on-chip peripheral SPI2 RX. Software can configure the RX channel setting by SPI2_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
bits : 16 - 19 (4 bit)
access : read-write

SPI2_TXSEL : PDMA SPI2 TX Selection (Medium Density Only) This filed defines which PDMA channel is connected to the on-chip peripheral SPI2 TX. Software can configure the TX channel setting by SPI2_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
bits : 20 - 23 (4 bit)
access : read-write

SPI3_RXSEL : PDMA SPI3 RX Selection (Medium Density Only) This filed defines which PDMA channel is connected to the on-chip peripheral SPI3 RX. Software can configure the RX channel setting by SPI3_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
bits : 24 - 27 (4 bit)
access : read-write

SPI3_TXSEL : PDMA SPI3 TX Selection (Medium Density Only) This filed defines which PDMA channel is connected to the on-chip peripheral SPI3 TX. Software can configure the TX channel setting by SPI3_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
bits : 28 - 31 (4 bit)
access : read-write


PDSSR1

PDMA Service Selection Control Register 1
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDSSR1 PDSSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART0_RXSEL UART0_TXSEL UART1_RXSEL UART1_TXSEL ADC_RXSEL

UART0_RXSEL : This filed defines which PDMA channel is connected to the on-chip peripheral UART0 RX. Software can change the channel RX setting by UART0_RXSEL 4'b0000: CH0 4'b0001: CH1 4'b0010: CH2 4'b0011: CH3 4'b0100: CH4 4'b0101: CH5 4'b0110: CH6 4'b0111: CH7 4'b1000: CH8 Others : Reserved Note : Ex : UART0_RXSEL = 4'b0110, that means UART0_RX is connected to PDMA_CH6(Low Density should set as 4'b0000 for PDMA channel 0 only)
bits : 0 - 3 (4 bit)
access : read-write

UART0_TXSEL : PDMA UART0 TX Selection This filed defines which PDMA channel is connected to the on-chip peripheral UART0 TX. Software can configure the TX channel setting by UART0_TXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL
bits : 4 - 7 (4 bit)
access : read-write

UART1_RXSEL : PDMA UART1 RX Selection This filed defines which PDMA channel is connected to the on-chip peripheral UART1 RX. Software can configure the RX channel setting by UART1_RXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL
bits : 8 - 11 (4 bit)
access : read-write

UART1_TXSEL : PDMA UART1 TX Selection This filed defines which PDMA channel is connected to the on-chip peripheral UART1 TX. Software can configure the TX channel setting by UART1_TXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL
bits : 12 - 15 (4 bit)
access : read-write

ADC_RXSEL : PDMA ADC RX Selection This filed defines which PDMA channel is connected to the on-chip peripheral ADC RX. Software can configure the RX channel setting by ADC_RXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL
bits : 24 - 27 (4 bit)
access : read-write


PDMA_GCRISR

PDMA Global Interrupt Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_GCRISR PDMA_GCRISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTR0 INTR1 INTR2 INTR3 INTR4 INTR5 INTR6 INTR7 INTR8 INTR

INTR0 : Interrupt Pin Status of Channel 0 This bit is the Interrupt pin status of PDMA channel0. Note: This bit is read only
bits : 0 - 0 (1 bit)
access : read-only

INTR1 : Interrupt Pin Status of Channel 1 (Medium Density Only) This bit is the Interrupt pin status of PDMA channel1. Note: This bit is read only
bits : 1 - 1 (1 bit)
access : read-only

INTR2 : Interrupt Pin Status of Channel 2 (Medium Density Only) This bit is the Interrupt pin status of PDMA channel2. Note: This bit is read only
bits : 2 - 2 (1 bit)
access : read-only

INTR3 : Interrupt Pin Status of Channel 3 (Medium Density Only) This bit is the Interrupt pin status of PDMA channel3. Note: This bit is read only
bits : 3 - 3 (1 bit)
access : read-only

INTR4 : Interrupt Pin Status of Channel 4 (Medium Density Only) This bit is the Interrupt pin status of PDMA channel4. Note: This bit is read only
bits : 4 - 4 (1 bit)
access : read-only

INTR5 : Interrupt Pin Status of Channel 5 (Medium Density Only) This bit is the Interrupt pin status of PDMA channel5. Note: This bit is read only
bits : 5 - 5 (1 bit)
access : read-only

INTR6 : Interrupt Pin Status of Channel 6 (Medium Density Only) This bit is the Interrupt pin status of PDMA channel 6. Note: This bit is read only
bits : 6 - 6 (1 bit)
access : read-only

INTR7 : Interrupt Pin Status of Channel 7 (Medium Density Only) This bit is the Interrupt pin status of PDMA channel 7. Note: This bit is read only
bits : 7 - 7 (1 bit)
access : read-only

INTR8 : Interrupt Pin Status of Channel 4 (Medium Density Only) This bit is the Interrupt pin status of PDMA channel 8. Note: This bit is read only
bits : 8 - 8 (1 bit)
access : read-only

INTR : Interrupt Pin Status This bit is the Interrupt pin status of PDMA controller. Note: This bit is read only
bits : 31 - 31 (1 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.