PS2CON

PS2TXDATA3

PS2RXDATA

PS2STATUS

PS2INTID

PS2TXDATA0

PS2TXDATA1

PS2TXDATA2

PS2EN : Enable PS2 Device Enable PS2 device controller 1 = Enable 0 = Disable
bits : 0 - 0 (1 bit)
access : read-write

TXINTEN : Enable Transmit Interrupt 1 = Enable data transmit complete interrupt 0 = Disable data transmit complete interrupt
bits : 1 - 1 (1 bit)
access : read-write

RXINTEN : Enable Receive Interrupt 1 = Enable data receive complete interrupt 0 = Disable data receive complete interrupt
bits : 2 - 2 (1 bit)
access : read-write

TXFIFO_DEPTH : Transmit Data FIFO Depth There is 16 bytes buffer for data transmit. S/W can define the FIFO depth from 1 to 16 bytes depends on application. 0 = 1 byte 1 = 2 bytes ... 14 = 15 bytes 15 = 16 bytes
bits : 3 - 6 (4 bit)
access : read-write

ACK : Acknowledge Enable 1 = If parity error or stop bit is not received correctly, acknowledge bit will not be sent to host at 12th clock 0 = Always send acknowledge to host at 12th clock for host to device communication.
bits : 7 - 7 (1 bit)
access : read-write

CLRFIFO : Clear TX FIFO Write 1 to this bit to terminate device to host transmission. The TXEMPTY bit in PS2STATUS bit will be set to 1 and pointer BYTEIDEX is reset to 0 regardless there is residue data in buffer or not. The buffer content is not been cleared. 1 = Clear FIFO 0 = Not active
bits : 8 - 8 (1 bit)
access : read-write

OVERRIDE : Software Override PS2 CLK/DATA Pin State 1 = PS2CLK and PS2DATA pins are controlled by S/W 0 = PS2CLK and PS2DATA pins are controlled by internal state machine.
bits : 9 - 9 (1 bit)
access : read-write

FPS2CLK : Force PS2CLK Line It forces PS2CLK line high or low regardless of the internal state of the device controller if OVERRIDE is set to high. 1 = Force PS2DATA line high 0 = Force PS2DATA line low
bits : 10 - 10 (1 bit)
access : read-write

FPS2DAT : Force PS2DATA Line It forces PS2DATA high or low regardless of the internal state of the device controller if OVERRIDE is set to high. 1 = Force PS2DATA high 0 = Force PS2DATA low
bits : 11 - 11 (1 bit)
access : read-write

TXDATA : Transmit data Write data to this register starts device to host communication if bus is in IDLE state. S/W must enable PS2EN before writing data to TX buffer.
bits : 0 - 31 (32 bit)
access : read-write

PS2RXDATA : Received Data For host to device communication, after acknowledge bit is sent, the received data is copied from receive shift register to PS2RXDATA register. CPU must read this register before next byte reception complete, otherwise the data will be overwritten and RXOVF bit in PS2STATUS[6] will be set to 1.
bits : 0 - 7 (8 bit)
access : read-only

PS2CLK : CLK Pin State This bit reflects the status of the PS2CLK line after synchronizing.
bits : 0 - 0 (1 bit)
access : read-only

PS2DATA : DATA Pin State This bit reflects the status of the PS2DATA line after synchronizing and sampling.
bits : 1 - 1 (1 bit)
access : read-only

FRAMERR : Frame Error For host to device communication, if STOP bit (logic 1) is not received it is a frame error. If frame error occurs, DATA line may keep at low state after 12th clock. At this moment, S/w overrides PS2CLK to send clock till PS2DATA release to high state. After that, device sends a "Resend" command to host. 1 = Frame error occur 0 = No frame error Write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write

RXPARITY : Received Parity This bit reflects the parity bit for the last received data byte (odd parity). Read only bit.
bits : 3 - 3 (1 bit)
access : read-only

RXBUSY : Receive Busy This bit indicates that the PS2 device is currently receiving data. 0 = Idle. 1 = Currently receiving data. Read only bit.
bits : 4 - 4 (1 bit)
access : read-only

TXBUSY : Transmit Busy This bit indicates that the PS2 device is currently sending data. 0 = Idle. 1 = Currently sending data. Read only bit.
bits : 5 - 5 (1 bit)
access : read-only

RXOVF : RX Buffer Overwrite 1 = Data in PS2RXDATA register is overwritten by new coming data. 0 = No overwrite Write 1 to clear this bit.
bits : 6 - 6 (1 bit)
access : read-write

TXEMPTY : TX FIFO Empty When S/W writes any data to PS2TXDATA0-3 the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled. When transmitted data byte number is equal to FIFODEPTH then TXEMPTY bit is clear to 1. 1 = FIFO is empty 0 = There is data to be transmitted Read only bit.
bits : 7 - 7 (1 bit)
access : read-only

BYTEIDX : Byte Index It indicates which data byte in transmit data shift register. When all data in FIFO is transmitted and it will be cleared to 0. It is a read only bit. BYTEIDX DATA Transmit BYTEIDX DATA Transmit 0000 TXDATA0[7:0] 1000 TXDATA2[7:0] 0001 TXDATA0[15:8] 1001 TXDATA2[15:8] 0010 TXDATA0[23:16] 1010 TXDATA2[23:16] 0011 TXDATA0[31:24] 1011 TXDATA2[31:24] 0100 TXDATA1[7:0] 1100 TXDATA3[7:0] 0101 TXDATA1[15:8] 1101 TXDATA3[15:8] 0110 TXDATA1[23:16] 1110 TXDATA3[23:16] 0111 TXDATA1[31:24] 1111 TXDATA3[31:24]
bits : 8 - 11 (4 bit)
access : read-only

RXINT : Receive Interrupt This bit is set to 1 when acknowledge bit is sent for Host to device communication. Interrupt occurs if RXINTEN bit is set to 1. 1 = Receive interrupt occurs 0 = No interrupt Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

TXINT : Transmit Interrupt This bit is set to 1 after STOP bit is transmitted. Interrupt occur if TXINTEN bit is set to 1. 1 = Transmit interrupt occurs 0 = No interrupt Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

TXDATA : Transmit data Write data to this register starts device to host communication if bus is in IDLE state. S/W must enable PS2EN before writing data to TX buffer.
bits : 0 - 31 (32 bit)
access : read-write

TXDATA : Transmit data Write data to this register starts device to host communication if bus is in IDLE state. S/W must enable PS2EN before writing data to TX buffer.
bits : 0 - 31 (32 bit)
access : read-write

TXDATA : Transmit data Write data to this register starts device to host communication if bus is in IDLE state. S/W must enable PS2EN before writing data to TX buffer.
bits : 0 - 31 (32 bit)
access : read-write