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address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
RTC Initiation Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Active : RTC Active Status (Read only), 0: RTC is at reset state 1: RTC is at normal active state.
bits : 0 - 0 (1 bit)
access : read-only
INIR : RTC Initiation When chip is power on, RTC timer counter is at unknown state because RTC timer counter reset is individual with chip reset; user has to write a number (0x a5eb1357) to INIR to reset RTC controller to initialize RTC controller.
bits : 0 - 31 (32 bit)
access : write-only
Calendar Loading Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
_1DAY : 1-Day Calendar Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write
_10DAY : 10-Day Calendar Digit (0~3)
bits : 4 - 5 (2 bit)
access : read-write
_1MON : 1-Month Calendar Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write
_10MON : 10-Month Calendar Digit (0~1)
bits : 12 - 12 (1 bit)
access : read-write
_1YEAR : 1-Year Calendar Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write
_10YEAR : 10-Year Calendar Digit (0~9)
bits : 20 - 23 (4 bit)
access : read-write
Time Scale Selection Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
_24H_12H : 24-Hour / 12-Hour Time Scale Selection It indicate that TLR and TAR are in 24-hour time mode or 12-hour time mode 1 = select 24-hour time scale 0 = select 12-hour time scale with AM and PM indication 24-hour time scale 12-hour time scale 24-hour time scale 12-hour time scale (PM time + 20) 00 12(AM12) 12 32(PM12) 01 01(AM01) 13 21(PM01) 02 02(AM02) 14 22(PM02) 03 03(AM03) 15 23(PM03) 04 04(AM04) 16 24(PM04) 05 05(AM05) 17 25(PM05) 06 06(AM06) 18 26(PM06) 07 07(AM07) 19 27(PM07) 08 08(AM08) 20 28(PM08) 09 09(AM09) 21 29(PM09) 10 10(AM10) 22 30(PM10) 11 11(AM11) 23 31(PM11)
bits : 0 - 0 (1 bit)
access : read-write
Day of the Week Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DWR : Day of the Week Register Value Day of the Week 0 Sunday 1 Monday 2 Tuesday 3 Wednesday 4 Thursday 5 Friday 6 Saturday
bits : 0 - 2 (3 bit)
access : read-write
Time Alarm Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
_1SEC : 1 Sec Time Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write
_10SEC : 10 Sec Time Digit of Alarm Setting (0~5)
bits : 4 - 6 (3 bit)
access : read-write
_1MIN : 1 Min Time Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write
_10MIN : 10 Min Time Digit of Alarm Setting (0~5)
bits : 12 - 14 (3 bit)
access : read-write
_1HR : 1 Hour Time Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write
_10HR : 10 Hour Time Digit of Alarm Setting (0~2)
bits : 20 - 21 (2 bit)
access : read-write
Calendar Alarm Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
_1DAY : 1-Day Calendar Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write
_10DAY : 10-Day Calendar Digit of Alarm Setting (0~3)
bits : 4 - 5 (2 bit)
access : read-write
_1MON : 1-Month Calendar Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write
_10MON : 10-Month Calendar Digit of Alarm Setting (0~1)
bits : 12 - 12 (1 bit)
access : read-write
_1YEAR : 1-Year Calendar Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write
_10YEAR : 10-Year Calendar Digit of Alarm Setting (0~9)
bits : 20 - 23 (4 bit)
access : read-write
RTC Leap year Indicator Register
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LIR : Leap Year Indication REGISTER (Real only). 1 = It indicate that this year is leap year 0 = It indicate that this year is not a leap year
bits : 0 - 0 (1 bit)
access : read-only
RTC Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AIER : Alarm Interrupt Enable 1 = RTC Alarm Interrupt is enabled 0 = RTC Alarm Interrupt is disabled
bits : 0 - 0 (1 bit)
access : read-write
TIER : Time Tick Interrupt Enable 1 = RTC Time Tick Interrupt is enabled 0 = RTC Time Tick Interrupt is disabled
bits : 1 - 1 (1 bit)
access : read-write
RTC Interrupt Indicator Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AIF : RTC Alarm Interrupt Flag When RTC Alarm Interrupt is enabled (RIER.AIER=1), RTC controller will set AIF to high once the RTC real time counters TLR and CLR reach the alarm setting time registers TAR and CAR. This bit is software clear by writing 1 to it. 1 = Indicates RTC Alarm Interrupt is requested if RIER.AIER=1. 0 = Indicates RTC Alarm Interrupt condition never occurred.
bits : 0 - 0 (1 bit)
access : read-write
TIF : RTC Time Tick Interrupt Flag When RTC Time Tick Interrupt is enabled (RIER.TIER=1), RTC controller will set TIF to high periodically in the period selected by TTR[2:0]. This bit is software clear by writing 1 to it. 1 = Indicates RTC Time Tick Interrupt is requested if RIER.TIER=1. 0 = Indicates RTC Time Tick Interrupt condition never occurred.
bits : 1 - 1 (1 bit)
access : read-write
RTC Time Tick Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TTR : Time Tick Register The RTC time tick period for Periodic Time Tick Interrupt request. TTR[2:0] Time tick (second) 0 1 1 1/2 2 1/4 3 1/8 4 1/16 5 1/32 6 1/64 7 1/128 Note: This register can be read back after the RTC register access enable bit ENF(AER[16]) is active.
bits : 0 - 2 (3 bit)
access : read-write
TWKE : RTC Timer Wakeup CPU Function Enable Bit If TWKE is set before CPU is in power-down mode, when a RTC Time Tick occurs, CPU will be wakened up by RTC controller. 1 = Enable the Wakeup function that CPU can be waken up from power-down mode by Time Tick. 0 = Disable Wakeup CPU function by Time Tick. Note: 1. Tick timer setting follows TTR[2:0] description. 2. The CPU can also be wakeup by alarm match occur.
bits : 3 - 3 (1 bit)
access : read-write
RTC Access Enable Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AER : RTC Register Access Enable Password (Write only) 0xA965 = Enable RTC access Others = Disable RTC access
bits : 0 - 15 (16 bit)
access : write-only
ENF : RTC Register Access Enable Flag (Read only) 1 = RTC register read/write enable 0 = RTC register read/write disable This bit will be set after AER[15:0] register is load a 0xA965, and be clear automatically 512 RTC clock or AER[15:0] is not 0xA965.Register\AER.ENF 1 0 INIR R/W R/W AER R/W R/W FCR R/W - TLR R/W R CLR R/W R TSSR R/W R/W DWR R/W R TAR R/W - CAR R/W - LIR R R RIER R/W R/W RIIR R/C R/C TTR R/W -
bits : 16 - 16 (1 bit)
access : read-only
RTC Frequency Compensation Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACTION : Fraction Part Formula = (fraction part of detected value) x 60 Note: Digit in FCR must be expressed as hexadecimal number. Refer to 5.8.4.4 for the examples.
bits : 0 - 5 (6 bit)
access : read-write
INTEGER : Integer Part Integer part of detected value FCR[11:8] Integer part of detected value FCR[11:8] 32776 1111 32768 0111 32775 1110 32767 0110 32774 1101 32766 0101 32773 1100 32765 0100 32772 1011 32764 0011 32771 1010 32763 0010 32770 1001 32762 0001 32769 1000 32761 0000
bits : 8 - 11 (4 bit)
access : read-write
Time Loading Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
_1SEC : 1 Sec Time Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write
_10SEC : 10 Sec Time Digit (0~5)
bits : 4 - 6 (3 bit)
access : read-write
_1MIN : 1 Min Time Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write
_10MIN : 10 Min Time Digit (0~5)
bits : 12 - 14 (3 bit)
access : read-write
_1HR : 1 Hour Time Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write
_10HR : 10 Hour Time Digit (0~2)
bits : 20 - 21 (2 bit)
access : read-write
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