SYST_CSR

NVIC_ISER

SYST_RVR

SYST_CVR

NVIC_ICER

NVIC_ISPR

NVIC_ICPR

NVIC_IPR0

NVIC_IPR1

NVIC_IPR2

NVIC_IPR3

NVIC_IPR4

NVIC_IPR5

NVIC_IPR6

NVIC_IPR7

CPUID

ICSR

AIRCR

SCR

SHPR2

SHPR3

ENABLE : 1 : the counter will operate in a multi-shot manner. 0 : the counter is disabled
bits : 0 - 0 (1 bit)
access : read-write

TICKINT : 1 : counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended. 0 : counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred.
bits : 1 - 1 (1 bit)
access : read-write

CLKSRC : 1 : core clock used for SysTick. 0 : clock source is (optional) external reference clock
bits : 2 - 2 (1 bit)
access : read-write

COUNTFLAG : Returns 1 if timer counted to 0 since last time this register was read. COUNTFLAG is set by a count transition from 1 to 0. COUNTFLAG is cleared on read or by a write to the Current Value register.
bits : 16 - 16 (1 bit)
access : read-only

SETENA : Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Writing 1 will enable the associated interrupt. Writing 0 has no effect. The register reads back with the current enable state.
bits : 0 - 31 (32 bit)
access : read-write

RELOAD : Value to load into the Current Value register when the counter reaches 0.
bits : 0 - 23 (24 bit)
access : read-write

CURRENT : Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (see SysTick Reload Value register).
bits : 0 - 23 (24 bit)
access : read-write

CLRENA : Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Writing 1 will disable the associated interrupt. Writing 0 has no effect. The register reads back with the current enable state.
bits : 0 - 31 (32 bit)
access : read-write

SETPEND : Writing 1 to a bit pends the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Writing 0 has no effect. The register reads back with the current pending state.
bits : 0 - 31 (32 bit)
access : read-write

CLRPEND : Writing 1 to a bit un-pends the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). Writing 0 has no effect. The register reads back with the current pending state.
bits : 0 - 31 (32 bit)
access : read-write

PRI_0 : Priority of IRQ0 "0" denotes the highest priority and "3" denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_1 : Priority of IRQ1 "0" denotes the highest priority and "3" denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_2 : Priority of IRQ2 "0" denotes the highest priority and "3" denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_3 : Priority of IRQ3 "0" denotes the highest priority and "3" denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_4 : Priority of IRQ4 "0" denotes the highest priority and "3" denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_5 : Priority of IRQ5 "0" denotes the highest priority and "3" denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_6 : Priority of IRQ6 "0" denotes the highest priority and "3" denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_7 : Priority of IRQ7 "0" denotes the highest priority and "3" denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_8 : Priority of IRQ8 "0" denotes the highest priority and "3" denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_9 : Priority of IRQ9 "0" denotes the highest priority and "3" denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_10 : Priority of IRQ10 "0" denotes the highest priority and "3" denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_11 : Priority of IRQ11 "0" denotes the highest priority and "3" denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_12 : Priority of IRQ12 "0" denotes the highest priority and "3" denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_13 : Priority of IRQ13 "0" denotes the highest priority and "3" denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_14 : Priority of IRQ14 "0" denotes the highest priority and "3" denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_15 : Priority of IRQ15 "0" denotes the highest priority and "3" denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_16 : Priority of IRQ16 "0" denotes the highest priority and "3" denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_17 : Priority of IRQ17 "0" denotes the highest priority and "3" denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_18 : Priority of IRQ18 "0" denotes the highest priority and "3" denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_19 : Priority of IRQ19 "0" denotes the highest priority and "3" denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_20 : Priority of IRQ20 "0" denotes the highest priority and "3" denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_21 : Priority of IRQ21 "0" denotes the highest priority and "3" denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_22 : Priority of IRQ22 "0" denotes the highest priority and "3" denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_23 : Priority of IRQ23 "0" denotes the highest priority and "3" denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_24 : Priority of IRQ24 "0" denotes the highest priority and "3" denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_25 : Priority of IRQ25 "0" denotes the highest priority and "3" denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_26 : Priority of IRQ26 "0" denotes the highest priority and "3" denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_27 : Priority of IRQ27 "0" denotes the highest priority and "3" denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_28 : Priority of IRQ28 "0" denotes the highest priority and "3" denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_29 : Priority of IRQ29 "0" denotes the highest priority and "3" denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_30 : Priority of IRQ30 "0" denotes the highest priority and "3" denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_31 : Priority of IRQ31 "0" denotes the highest priority and "3" denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

REVESION : Reads as 0x0
bits : 0 - 3 (4 bit)
access : read-only

PARTNO : Reads as 0xC20
bits : 4 - 15 (12 bit)
access : read-only

PART : Reads as 0xC for ARMv6-M parts
bits : 16 - 19 (4 bit)
access : read-only

IMPLEMENTER : Implementer code assigned by ARM. ( ARM = 0x41)
bits : 24 - 31 (8 bit)
access : read-only

VECTACTIVE : 0 = Thread mode Value > 1 = the exception number for the current executing exception.This is a read only bit.
bits : 0 - 8 (9 bit)
access : read-only

VECTPENDING : Indicates the exception number for the highest priority pending exception. The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. A value of zero indicates no pending exceptions. This is a read only bit.
bits : 12 - 20 (9 bit)
access : read-only

ISRPENDING : Indicates if an external configurable (NVIC generated) interrupt is pending. This is a read only bit.
bits : 22 - 22 (1 bit)
access : read-only

ISRPREEMPT : If set, a pending exception will be serviced on exit from the debug halt state. This is a read only bit.
bits : 23 - 23 (1 bit)
access : read-only

PENDSTCLR : Write 1 to clear a pending SysTick. This is a write only bit.
bits : 25 - 25 (1 bit)
access : write-only

PENDSTSET : Set a pending SysTick. Reads back with current state (1 if Pending, 0 if not).
bits : 26 - 26 (1 bit)
access : read-write

PENDSVCLR : Write 1 to clear a pending PendSV interrupt. This is a write only bit.
bits : 27 - 27 (1 bit)
access : write-only

PENDSVSET : Set a pending PendSV interrupt. This is normally used to request a context switch. Reads back with current state (1 if Pending, 0 if not).
bits : 28 - 28 (1 bit)
access : read-write

NMIPENDSET : Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. Reads back with current state (1 if Pending, 0 if not).
bits : 31 - 31 (1 bit)
access : read-write

VECTCLRACTIVE : Set this bit to 1 will clears all active state information for fixed and configurable exceptions. The bit is a write only bit and can only be written when the core is halted. Note: It is the debugger's responsibility to re-initialize the stack.
bits : 1 - 1 (1 bit)
access : write-only

SYSRESETREQ : Writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested. The bit is a write only bit and self-clears as part of the reset sequence.
bits : 2 - 2 (1 bit)
access : write-only

VECTORKEY : When write this register, this field should be 0x05FA, otherwise the write action will be unpredictable.
bits : 16 - 31 (16 bit)
access : read-write

SLEEPONEXIT : When set to 1, the core can enter a sleep state on an exception return to Thread mode. This is the mode and exception level entered at reset, the base level of execution.
bits : 1 - 1 (1 bit)
access : read-write

SLEEPDEEP : A qualifying hint that indicates waking from sleep might take longer.
bits : 2 - 2 (1 bit)
access : read-write

SEVONPEND : When enabled, interrupt transitions from Inactive to Pending are included in the list of wakeup events for the WFE instruction.
bits : 4 - 4 (1 bit)
access : read-write

PRI_11 : Priority of system handler 11 SVCall "0" denotes the highest priority and "3" denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_14 : Priority of system handler 14 PendSV "0" denotes the highest priority and "3" denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_15 : Priority of system handler 15 SysTick "0" denotes the highest priority and "3" denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write