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USB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x90 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xA4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

INTEN

ATTR

FLDET

BUFSEG

BUFSEG0

MXPLD0

CFG0

CFGP0

BUFSEG1

MXPLD1

CFG1

CFGP1

INTSTS

BUFSEG2

MXPLD2

CFG2

CFGP2

BUFSEG3

MXPLD3

CFG3

CFGP3

BUFSEG4

MXPLD4

CFG4

CFGP4

BUFSEG5

MXPLD5

CFG5

CFGP5

FADDR

DRVSE0

PDMA

EPSTS


INTEN

Interrupt Enable Flag
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUS_IE USB_IE FLDET_IE WAKEUP_IE WAKEUP_EN INNAK_EN

BUS_IE : 1/0: Enable/disable BUS event interrupt.
bits : 0 - 0 (1 bit)
access : read-write

USB_IE : 1/0: Enable/disable USB event interrupt.
bits : 1 - 1 (1 bit)
access : read-write

FLDET_IE : 1/0: Enable/disable Floating detect Interrupt
bits : 2 - 2 (1 bit)
access : read-write

WAKEUP_IE : 1/0: Enable/disable Wakeup Interrupt.
bits : 3 - 3 (1 bit)
access : read-write

WAKEUP_EN : 1/0: Enable/Disable USB wakeup function
bits : 8 - 8 (1 bit)
access : read-write

INNAK_EN : 1 = The NAK status is updated into the endpoint status register, USB_EPSTS, when it is set to 1 and there is NAK response in IN token. It also enable the interrupt event when the device responds NAK after receiving IN token. 0 = The NAK status doesn't be updated into the endpoint status register when it was set to 0. It also disable the interrupt event when device responds NAK after receiving IN token
bits : 15 - 15 (1 bit)
access : write-only


ATTR

Bus state and attribution
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATTR ATTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBRST SUSPEND RESUME TIMEOUT PHY_EN RWAKEUP USB_EN DPPU_EN PWRDN BYTEM

USBRST : 1: Bus reset when SE0(single-ended 0) more than 2.5uS. 0: Bus no reset.
bits : 0 - 0 (1 bit)
access : read-only

SUSPEND : 1: Bus idle more than 3mS, either cable is plugged off or host is sleeping. 0: Bus no suspend.
bits : 1 - 1 (1 bit)
access : read-only

RESUME : 1: Resume from suspension 0: No bus resume.
bits : 2 - 2 (1 bit)
access : read-only

TIMEOUT : 1: No response more than 18 bits time 0: No time out.
bits : 3 - 3 (1 bit)
access : read-only

PHY_EN : 1: Enable PHY transceiver function. 0: Disable PHY transceiver function.
bits : 4 - 4 (1 bit)
access : read-write

RWAKEUP : 1: Force USB bus to K state, used for remote wake-up. 0: Release the USB bus from K state.
bits : 5 - 5 (1 bit)
access : read-write

USB_EN : 1: Enable USB controller. 0: Disable USB controller.
bits : 7 - 7 (1 bit)
access : read-write

DPPU_EN : Pull-up resistor on USB_DP enable bit 1: Enable 0: Disable
bits : 8 - 8 (1 bit)
access : read-write

PWRDN : 1: Turn-on related circuit of PHY transceiver 0: power-down related circuit of PHY transceiver
bits : 9 - 9 (1 bit)
access : read-write

BYTEM : 1: Byte Mode. The size of the transfer from CPU to USB SRAM can be Byte only. 0: Word Mode. The size of the transfer from CPU to USB SRAM can be Word. only
bits : 10 - 10 (1 bit)
access : read-write


FLDET

Device Floating Detected
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FLDET FLDET read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLDET

FLDET : 1: When the controller is attached into the BUS, this bit will be set as 1 0: The controller didn't attached into the USB host
bits : 0 - 0 (1 bit)
access : read-only


BUFSEG

Buffer Segmentation
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUFSEG BUFSEG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFSEG

BUFSEG : It is used to indicate the offset address for the Setup token with the USB SRAM starting address. The effective starting address is USB_SRAM address + { BUFSEG[8:3], 3'b000} Where the USB_SRAM address = 0x40060100h. Note: It is used for Setup token only.
bits : 3 - 8 (6 bit)
access : read-write


BUFSEG0

Buffer Segmentation of endpoint 0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUFSEG0 BUFSEG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFSEG0

BUFSEG0 : It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is: USB_SRAM address + { BUFSEG0[8:3], 3'b000} Where the USB_SRAM address = 0x40060100h. Refer to section 5.4.4.7 for the endpoint SRAM structure and its description.
bits : 3 - 8 (6 bit)
access : read-write


MXPLD0

Maximal payload of endpoint 0
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MXPLD0 MXPLD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MXPLD

MXPLD : It is used to define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. (1). When the register is written by CPU, For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. (2). When the register is read by CPU, For IN token, the value of MXPLD is indicated the data length be transmitted to host. For OUT token, the value of MXPLD is indicated the actual data length receiving from host. Note that once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
bits : 0 - 8 (9 bit)
access : read-write


CFG0

Configuration of endpoint 0
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG0 CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP_NUM ISOCH STATE DSQ_SYNC CSTALL

EP_NUM : These bits are used to define the endpoint number of the current endpoint.
bits : 0 - 3 (4 bit)
access : read-write

ISOCH : This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1: Isochronous endpoint 0: No Isochronous endpoint
bits : 4 - 4 (1 bit)
access : read-write

STATE : 00 = Endpoint is disabled 01 = OUT endpoint 10 = IN endpoint 11 = Undefined
bits : 5 - 6 (2 bit)
access : read-write

DSQ_SYNC : 1 = DATA1 PID 0 = DATA0 PID It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. H/W will toggle automatically in IN token base on the bit.
bits : 7 - 7 (1 bit)
access : read-write

CSTALL : 1 = Clear the device to response STALL handshake in setup stage 0 = Disable the device to clear the STALL handshake in setup stage
bits : 9 - 9 (1 bit)
access : read-write


CFGP0

stall control register and In/out ready clear flag of endpoint 0
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGP0 CFGP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRRDY SSTALL

CLRRDY : When the MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it is auto clear to 0. For IN token, write 1 is used to clear the IN token had ready to transmit the data to USB. For OUT token, write 1 is used to clear the OUT token had ready to receive the data from USB. This bit is write 1 only and it is always 0 when it was read back.
bits : 0 - 0 (1 bit)
access : write-only

SSTALL : 1 = Set the device to respond STALL automatically 0 = Disable the device to response STALL
bits : 1 - 1 (1 bit)
access : read-write


BUFSEG1

Buffer Segmentation of endpoint 1
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUFSEG1 BUFSEG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFSEG1

BUFSEG1 : It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is: USB_SRAM address + { BUFSEG1[8:3], 3'b000} Where the USB_SRAM address = 0x40060100h. Refer to section 5.4.4.7 for the endpoint SRAM structure and its description.
bits : 3 - 8 (6 bit)
access : read-write


MXPLD1

Maximal payload of endpoint 1
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MXPLD1 MXPLD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MXPLD

MXPLD : It is used to define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. (1). When the register is written by CPU, For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. (2). When the register is read by CPU, For IN token, the value of MXPLD is indicated the data length be transmitted to host. For OUT token, the value of MXPLD is indicated the actual data length receiving from host. Note that once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
bits : 0 - 8 (9 bit)
access : read-write


CFG1

Configuration of endpoint 1
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG1 CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP_NUM ISOCH STATE DSQ_SYNC CSTALL

EP_NUM : These bits are used to define the endpoint number of the current endpoint.
bits : 0 - 3 (4 bit)
access : read-write

ISOCH : This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1: Isochronous endpoint 0: No Isochronous endpoint
bits : 4 - 4 (1 bit)
access : read-write

STATE : 00 = Endpoint is disabled 01 = OUT endpoint 10 = IN endpoint 11 = Undefined
bits : 5 - 6 (2 bit)
access : read-write

DSQ_SYNC : 1 = DATA1 PID 0 = DATA0 PID It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. H/W will toggle automatically in IN token base on the bit.
bits : 7 - 7 (1 bit)
access : read-write

CSTALL : 1 = Clear the device to response STALL handshake in setup stage 0 = Disable the device to clear the STALL handshake in setup stage
bits : 9 - 9 (1 bit)
access : read-write


CFGP1

stall control register and In/out ready clear flag of endpoint 1
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGP1 CFGP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRRDY SSTALL

CLRRDY : When the MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it is auto clear to 0. For IN token, write 1 is used to clear the IN token had ready to transmit the data to USB. For OUT token, write 1 is used to clear the OUT token had ready to receive the data from USB. This bit is write 1 only and it is always 0 when it was read back.
bits : 0 - 0 (1 bit)
access : write-only

SSTALL : 1 = Set the device to respond STALL automatically 0 = Disable the device to response STALL
bits : 1 - 1 (1 bit)
access : read-write


INTSTS

Interrupt Event Flag
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSTS INTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUS_STS USB_STS FLDET_STS WAKEUP_STS EPEVT0 EPEVT1 EPEVT2 EPEVT3 EPEVT4 EPEVT5 SETUP

BUS_STS : The BUS event means that there is one of the suspense or the resume function in the bus. 1 = Bus event occurred; check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USB_INTSTS[0]. 0 = No any BUS event is occurred
bits : 0 - 0 (1 bit)
access : read-write

USB_STS : The USB event includes the Setup Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus. 1 = USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[1] or EPSTS0~5 and SETUP (USB_INTSTS[31]) 0 = No any USB event is occurred
bits : 1 - 1 (1 bit)
access : read-write

FLDET_STS : 1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USB_INTSTS[2]. 0 = There is not attached/detached event in the USB
bits : 2 - 2 (1 bit)
access : read-write

WAKEUP_STS : 1 = Wakeup event occurred, cleared by write 1 to USB_INTSTS[3] 0 = No Wakeup event is occurred
bits : 3 - 3 (1 bit)
access : read-write

EPEVT0 : 1 = USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[16] or USB_INTSTS[1] 0 = No event occurred in endpoint 0
bits : 16 - 16 (1 bit)
access : read-write

EPEVT1 : 1 = USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[17] or USB_INTSTS[1] 0 = No event occurred in endpoint 1
bits : 17 - 17 (1 bit)
access : read-write

EPEVT2 : 1 = USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[18] or USB_INTSTS[1] 0 = No event occurred in endpoint 2
bits : 18 - 18 (1 bit)
access : read-write

EPEVT3 : 1 = USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[19] or USB_INTSTS[1] 0 = No event occurred in endpoint 3
bits : 19 - 19 (1 bit)
access : read-write

EPEVT4 : 1 = USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[20] or USB_INTSTS[1] 0 = No event occurred in endpoint 4
bits : 20 - 20 (1 bit)
access : read-write

EPEVT5 : 1 = USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[21] or USB_INTSTS[1] 0 = No event occurred in endpoint 5
bits : 21 - 21 (1 bit)
access : read-write

SETUP : 1 = Setup event occurred, cleared by write 1 to USB_INTSTS[31] 0 = No Setup event
bits : 31 - 31 (1 bit)
access : read-write


BUFSEG2

Buffer Segmentation of endpoint 2
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUFSEG2 BUFSEG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFSEG2

BUFSEG2 : It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is: USB_SRAM address + { BUFSEG2[8:3], 3'b000} Where the USB_SRAM address = 0x40060100h. Refer to section 5.4.4.7 for the endpoint SRAM structure and its description.
bits : 3 - 8 (6 bit)
access : read-write


MXPLD2

Maximal payload of endpoint 2
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MXPLD2 MXPLD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MXPLD

MXPLD : It is used to define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. (1). When the register is written by CPU, For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. (2). When the register is read by CPU, For IN token, the value of MXPLD is indicated the data length be transmitted to host. For OUT token, the value of MXPLD is indicated the actual data length receiving from host. Note that once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
bits : 0 - 8 (9 bit)
access : read-write


CFG2

Configuration of endpoint 2
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG2 CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP_NUM ISOCH STATE DSQ_SYNC CSTALL

EP_NUM : These bits are used to define the endpoint number of the current endpoint.
bits : 0 - 3 (4 bit)
access : read-write

ISOCH : This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1: Isochronous endpoint 0: No Isochronous endpoint
bits : 4 - 4 (1 bit)
access : read-write

STATE : 00 = Endpoint is disabled 01 = OUT endpoint 10 = IN endpoint 11 = Undefined
bits : 5 - 6 (2 bit)
access : read-write

DSQ_SYNC : 1 = DATA1 PID 0 = DATA0 PID It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. H/W will toggle automatically in IN token base on the bit.
bits : 7 - 7 (1 bit)
access : read-write

CSTALL : 1 = Clear the device to response STALL handshake in setup stage 0 = Disable the device to clear the STALL handshake in setup stage
bits : 9 - 9 (1 bit)
access : read-write


CFGP2

stall control register and In/out ready clear flag of endpoint 2
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGP2 CFGP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRRDY SSTALL

CLRRDY : When the MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it is auto clear to 0. For IN token, write 1 is used to clear the IN token had ready to transmit the data to USB. For OUT token, write 1 is used to clear the OUT token had ready to receive the data from USB. This bit is write 1 only and it is always 0 when it was read back.
bits : 0 - 0 (1 bit)
access : write-only

SSTALL : 1 = Set the device to respond STALL automatically 0 = Disable the device to response STALL
bits : 1 - 1 (1 bit)
access : read-write


BUFSEG3

Buffer Segmentation of endpoint 3
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUFSEG3 BUFSEG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFSEG3

BUFSEG3 : It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is: USB_SRAM address + { BUFSEG3[8:3], 3'b000} Where the USB_SRAM address = 0x40060100h. Refer to section 5.4.4.7 for the endpoint SRAM structure and its description.
bits : 3 - 8 (6 bit)
access : read-write


MXPLD3

Maximal payload of endpoint 3
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MXPLD3 MXPLD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MXPLD

MXPLD : It is used to define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. (1). When the register is written by CPU, For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. (2). When the register is read by CPU, For IN token, the value of MXPLD is indicated the data length be transmitted to host. For OUT token, the value of MXPLD is indicated the actual data length receiving from host. Note that once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
bits : 0 - 8 (9 bit)
access : read-write


CFG3

Configuration of endpoint 3
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG3 CFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP_NUM ISOCH STATE DSQ_SYNC CSTALL

EP_NUM : These bits are used to define the endpoint number of the current endpoint.
bits : 0 - 3 (4 bit)
access : read-write

ISOCH : This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1: Isochronous endpoint 0: No Isochronous endpoint
bits : 4 - 4 (1 bit)
access : read-write

STATE : 00 = Endpoint is disabled 01 = OUT endpoint 10 = IN endpoint 11 = Undefined
bits : 5 - 6 (2 bit)
access : read-write

DSQ_SYNC : 1 = DATA1 PID 0 = DATA0 PID It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. H/W will toggle automatically in IN token base on the bit.
bits : 7 - 7 (1 bit)
access : read-write

CSTALL : 1 = Clear the device to response STALL handshake in setup stage 0 = Disable the device to clear the STALL handshake in setup stage
bits : 9 - 9 (1 bit)
access : read-write


CFGP3

stall control register and In/out ready clear flag of endpoint 3
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGP3 CFGP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRRDY SSTALL

CLRRDY : When the MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it is auto clear to 0. For IN token, write 1 is used to clear the IN token had ready to transmit the data to USB. For OUT token, write 1 is used to clear the OUT token had ready to receive the data from USB. This bit is write 1 only and it is always 0 when it was read back.
bits : 0 - 0 (1 bit)
access : write-only

SSTALL : 1 = Set the device to respond STALL automatically 0 = Disable the device to response STALL
bits : 1 - 1 (1 bit)
access : read-write


BUFSEG4

Buffer Segmentation of endpoint 4
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUFSEG4 BUFSEG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFSEG4

BUFSEG4 : It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is: USB_SRAM address + { BUFSEG4[8:3], 3'b000} Where the USB_SRAM address = 0x40060100h. Refer to section 5.4.4.7 for the endpoint SRAM structure and its description.
bits : 3 - 8 (6 bit)
access : read-write


MXPLD4

Maximal payload of endpoint 4
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MXPLD4 MXPLD4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MXPLD

MXPLD : It is used to define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. (1). When the register is written by CPU, For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. (2). When the register is read by CPU, For IN token, the value of MXPLD is indicated the data length be transmitted to host. For OUT token, the value of MXPLD is indicated the actual data length receiving from host. Note that once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
bits : 0 - 8 (9 bit)
access : read-write


CFG4

Configuration of endpoint 4
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG4 CFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP_NUM ISOCH STATE DSQ_SYNC CSTALL

EP_NUM : These bits are used to define the endpoint number of the current endpoint.
bits : 0 - 3 (4 bit)
access : read-write

ISOCH : This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1: Isochronous endpoint 0: No Isochronous endpoint
bits : 4 - 4 (1 bit)
access : read-write

STATE : 00 = Endpoint is disabled 01 = OUT endpoint 10 = IN endpoint 11 = Undefined
bits : 5 - 6 (2 bit)
access : read-write

DSQ_SYNC : 1 = DATA1 PID 0 = DATA0 PID It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. H/W will toggle automatically in IN token base on the bit.
bits : 7 - 7 (1 bit)
access : read-write

CSTALL : 1 = Clear the device to response STALL handshake in setup stage 0 = Disable the device to clear the STALL handshake in setup stage
bits : 9 - 9 (1 bit)
access : read-write


CFGP4

stall control register and In/out ready clear flag of endpoint 4
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGP4 CFGP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRRDY SSTALL

CLRRDY : When the MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it is auto clear to 0. For IN token, write 1 is used to clear the IN token had ready to transmit the data to USB. For OUT token, write 1 is used to clear the OUT token had ready to receive the data from USB. This bit is write 1 only and it is always 0 when it was read back.
bits : 0 - 0 (1 bit)
access : write-only

SSTALL : 1 = Set the device to respond STALL automatically 0 = Disable the device to response STALL
bits : 1 - 1 (1 bit)
access : read-write


BUFSEG5

Buffer Segmentation of endpoint 5
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUFSEG5 BUFSEG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFSEG5

BUFSEG5 : It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is: USB_SRAM address + { BUFSEG5[8:3], 3'b000} Where the USB_SRAM address = 0x40060100h. Refer to section 5.4.4.7 for the endpoint SRAM structure and its description.
bits : 3 - 8 (6 bit)
access : read-write


MXPLD5

Maximal payload of endpoint 5
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MXPLD5 MXPLD5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MXPLD

MXPLD : It is used to define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. (1). When the register is written by CPU, For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. (2). When the register is read by CPU, For IN token, the value of MXPLD is indicated the data length be transmitted to host. For OUT token, the value of MXPLD is indicated the actual data length receiving from host. Note that once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
bits : 0 - 8 (9 bit)
access : read-write


CFG5

Configuration of endpoint 5
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG5 CFG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP_NUM ISOCH STATE DSQ_SYNC CSTALL

EP_NUM : These bits are used to define the endpoint number of the current endpoint.
bits : 0 - 3 (4 bit)
access : read-write

ISOCH : This bit is used to set the endpoint as Isochronous endpoint, no handshake. 1: Isochronous endpoint 0: No Isochronous endpoint
bits : 4 - 4 (1 bit)
access : read-write

STATE : 00 = Endpoint is disabled 01 = OUT endpoint 10 = IN endpoint 11 = Undefined
bits : 5 - 6 (2 bit)
access : read-write

DSQ_SYNC : 1 = DATA1 PID 0 = DATA0 PID It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. H/W will toggle automatically in IN token base on the bit.
bits : 7 - 7 (1 bit)
access : read-write

CSTALL : 1 = Clear the device to response STALL handshake in setup stage 0 = Disable the device to clear the STALL handshake in setup stage
bits : 9 - 9 (1 bit)
access : read-write


CFGP5

In ready clear flag of endpoint 5
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGP5 CFGP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRRDY SSTALL

CLRRDY : When the MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it is auto clear to 0. For IN token, write 1 is used to clear the IN token had ready to transmit the data to USB. For OUT token, write 1 is used to clear the OUT token had ready to receive the data from USB. This bit is write 1 only and it is always 0 when it was read back.
bits : 0 - 0 (1 bit)
access : write-only

SSTALL : 1 = Set the device to respond STALL automatically 0 = Disable the device to response STALL
bits : 1 - 1 (1 bit)
access : read-write


FADDR

Function Address
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FADDR FADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FADDR

FADDR : Function Address of this USB device.
bits : 0 - 6 (7 bit)
access : read-write


DRVSE0

Drive Single Ended Zero (SE0) in USB Bus
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRVSE0 DRVSE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRVSE0

DRVSE0 : The Single Ended Zero (SE0) is when both lines (USB_DP and USB_DM) are being pulled low. 1 = Force USB PHY transceiver to drive SE0 0 = None
bits : 0 - 0 (1 bit)
access : read-write


PDMA

New description for register
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA PDMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMA_RW PDMA_EN

PDMA_RW : 1 = The USB PDMA read data from USB buffer to memory 0 = The USB PDMA write data from memory to USB buffer
bits : 0 - 0 (1 bit)
access : read-write

PDMA_EN : 1 = The PDMA function in USB is enabled 0 = The PDMA function in USB is disabled This bit will be automatically cleared after PDMA transfer done
bits : 1 - 1 (1 bit)
access : read-write


EPSTS

System state
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPSTS EPSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVERRUN EPSTS0 EPSTS1 EPSTS2 EPSTS3 EPSTS4 EPSTS5

OVERRUN : It indicates that the received data is over the maximum payload number or not. 1 = It indicates that the Out Data more than the Max Payload in MXPLD register or the Setup Data more than 8 Bytes 0 = No overrun
bits : 7 - 7 (1 bit)
access : read-only

EPSTS0 : These bits are used to indicate the current status of this endpoint 000 = In ACK 001 = In NAK 010 = Out Packet Data0 ACK 110 = Out Packet Data1 ACK 011 = Setup ACK 111 = Isochronous transfer end
bits : 8 - 10 (3 bit)
access : read-only

EPSTS1 : These bits are used to indicate the current status of this endpoint 000 = In ACK 001 = In NAK 010 = Out Packet Data0 ACK 110 = Out Packet Data1 ACK 011 = Setup ACK 111 = Isochronous transfer end
bits : 11 - 13 (3 bit)
access : read-only

EPSTS2 : These bits are used to indicate the current status of this endpoint 000 = In ACK 001 = In NAK 010 = Out Packet Data0 ACK 110 = Out Packet Data1 ACK 011 = Setup ACK 111 = Isochronous transfer end
bits : 14 - 16 (3 bit)
access : read-only

EPSTS3 : These bits are used to indicate the current status of this endpoint 000 = In ACK 001 = In NAK 010 = Out Packet Data0 ACK 110 = Out Packet Data1 ACK 011 = Setup ACK 111 = Isochronous transfer end
bits : 17 - 19 (3 bit)
access : read-only

EPSTS4 : These bits are used to indicate the current status of this endpoint 000 = In ACK 001 = In NAK 010 = Out Packet Data0 ACK 110 = Out Packet Data1 ACK 011 = Setup ACK 111 = Isochronous transfer end
bits : 20 - 22 (3 bit)
access : read-only

EPSTS5 : These bits are used to indicate the current status of this endpoint 000 = In ACK 001 = In NAK 010 = Out Packet Data0 ACK 110 = Out Packet Data1 ACK 011 = Setup ACK 111 = Isochronous transfer end
bits : 23 - 25 (3 bit)
access : read-only



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