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CT32B0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected

Registers

IR

PC

MCR

MR0

MR1

MR2

MR3

EMR

TCR

PWMC

TC

PR


IR

Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IR IR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR0INT MR1INT MR2INT MR3INT CR0INT RESERVED

MR0INT : Interrupt flag for match channel 0.
bits : 0 - 0 (1 bit)

MR1INT : Interrupt flag for match channel 1.
bits : 1 - 2 (2 bit)

MR2INT : Interrupt flag for match channel 2.
bits : 2 - 4 (3 bit)

MR3INT : Interrupt flag for match channel 3.
bits : 3 - 6 (4 bit)

CR0INT : Interrupt flag for capture channel 0 event.
bits : 4 - 8 (5 bit)

RESERVED : Reserved
bits : 5 - 36 (32 bit)


PC

Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC PC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PC

PC : Prescale counter value.
bits : 0 - 31 (32 bit)


MCR

Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR0I MR0R MR0S MR1I MR1R MR1S MR2I MR2R MR2S MR3I MR3R MR3S RESERVED

MR0I : Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

1 : Enabled

Enabled

0 : Disabled

Disabled

End of enumeration elements list.

MR0R : Reset on MR0: the TC will be reset if MR0 matches it.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

1 : Enabled

Enabled

0 : Disabled

Disabled

End of enumeration elements list.

MR0S : Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

1 : Enabled

Enabled

0 : Disabled

Disabled

End of enumeration elements list.

MR1I : Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
bits : 3 - 6 (4 bit)

Enumeration: ENUM

1 : Enabled

Enabled

0 : Disabled

Disabled

End of enumeration elements list.

MR1R : Reset on MR1: the TC will be reset if MR1 matches it.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

1 : Enabled

Enabled

0 : Disabled

Disabled

End of enumeration elements list.

MR1S : Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

1 : Enabled

Enabled

0 : Disabled

Disabled

End of enumeration elements list.

MR2I : Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
bits : 6 - 12 (7 bit)

Enumeration: ENUM

1 : Enabled

Enabled

0 : Disabled

Disabled

End of enumeration elements list.

MR2R : Reset on MR2: the TC will be reset if MR2 matches it.
bits : 7 - 14 (8 bit)

Enumeration: ENUM

1 : Enabled

Enabled

0 : Disabled

Disabled

End of enumeration elements list.

MR2S : Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
bits : 8 - 16 (9 bit)

Enumeration: ENUM

1 : Enabled

Enabled

0 : Disabled

Disabled

End of enumeration elements list.

MR3I : Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
bits : 9 - 18 (10 bit)

Enumeration: ENUM

1 : Enabled

Enabled

0 : Disabled

Disabled

End of enumeration elements list.

MR3R : Reset on MR3: the TC will be reset if MR3 matches it.
bits : 10 - 20 (11 bit)

Enumeration: ENUM

1 : Enabled

Enabled

0 : Disabled

Disabled

End of enumeration elements list.

MR3S : Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
bits : 11 - 22 (12 bit)

Enumeration: ENUM

1 : Enabled

Enabled

0 : Disabled

Disabled

End of enumeration elements list.

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 12 - 43 (32 bit)


MR0

Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate aninterrupt every time MR matches the TC.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR0 MR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH

MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)


MR1

Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate aninterrupt every time MR matches the TC.
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR1 MR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH

MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)


MR2

Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate aninterrupt every time MR matches the TC.
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR2 MR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH

MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)


MR3

Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate aninterrupt every time MR matches the TC.
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR3 MR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH

MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)


EMR

External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0].
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EMR EMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM0 EM1 EM2 EM3 EMC0 EMC1 EMC2 EMC3 RESERVED

EM0 : External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bits : 0 - 0 (1 bit)

EM1 : External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bits : 1 - 2 (2 bit)

EM2 : External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bits : 2 - 4 (3 bit)

EM3 : External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bits : 3 - 6 (4 bit)

EMC0 : External Match Control 0. Determines the functionality of External Match 0.
bits : 4 - 9 (6 bit)

Enumeration: ENUM

0x0 : DONOTHING

Do Nothing.

0x1 : CLEAR

Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out).

0x2 : SET

Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out).

0x3 : TOGGLE

Toggle the corresponding External Match bit/output.

End of enumeration elements list.

EMC1 : External Match Control 1. Determines the functionality of External Match 1.
bits : 6 - 13 (8 bit)

Enumeration: ENUM

0x0 : DONOTHING

Do Nothing.

0x1 : CLEAR

Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out).

0x2 : SET

Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out).

0x3 : TOGGLE

Toggle the corresponding External Match bit/output.

End of enumeration elements list.

EMC2 : External Match Control 2. Determines the functionality of External Match 2.
bits : 8 - 17 (10 bit)

Enumeration: ENUM

0x0 : DONOTHING

Do Nothing.

0x1 : CLEAR

Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out).

0x2 : SET

Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out).

0x3 : TOGGLE

Toggle the corresponding External Match bit/output.

End of enumeration elements list.

EMC3 : External Match Control 3. Determines the functionality of External Match 3.
bits : 10 - 21 (12 bit)

Enumeration: ENUM

0x0 : DONOTHING

Do Nothing.

0x1 : CLEAR

Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out).

0x2 : SET

Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out).

0x3 : TOGGLE

Toggle the corresponding External Match bit/output.

End of enumeration elements list.

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 12 - 43 (32 bit)


TCR

Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN CRST RESERVED

CEN : Counter Enable When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
bits : 0 - 0 (1 bit)

CRST : Counter Reset When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
bits : 1 - 2 (2 bit)

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 2 - 33 (32 bit)


PWMC

PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0].
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMC PWMC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMEN0 PWMEN1 PWMEN2 PWMEN3 RESERVED

PWMEN0 : When one, PWM mode is enabled for CT32Bn_MAT0. When zero, CT32Bn_MAT0 is controlled by EM0.
bits : 0 - 0 (1 bit)

PWMEN1 : When one, PWM mode is enabled for CT32Bn_MAT1. When zero, CT32Bn_MAT1 is controlled by EM1.
bits : 1 - 2 (2 bit)

PWMEN2 : When one, PWM mode is enabled for CT32Bn_MAT2. When zero, CT32Bn_MAT2 is controlled by EM2.
bits : 2 - 4 (3 bit)

PWMEN3 : When one, PWM mode is enabled for CT32Bn_MAT3. When zero, CT32Bn_MAT3 is controlled by EM3. Note: It is recommended to use match channel 3 to set the PWM cycle.
bits : 3 - 6 (4 bit)

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 4 - 35 (32 bit)


TC

Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC TC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC

TC : Timer counter value.
bits : 0 - 31 (32 bit)


PR

Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PR PR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PR

PR : Prescale counter max value.
bits : 0 - 31 (32 bit)



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