SYSMEMREMAP

PIOPORCAP0

BODCTRL

SYSTCKCAL

SYSOSCCTRL

STARTAPRP0

STARTERP0

STARTRSRP0CLR

STARTSRP0

PDSLEEPCFG

PDAWAKECFG

PDRUNCFG

WDTOSCCTRL

IRCCTRL

SYSRSTSTAT

DEVICE_ID

PRESETCTRL

SYSPLLCLKSEL

SYSPLLCLKUEN

MAINCLKSEL

MAINCLKUEN

SYSAHBCLKDIV

SYSPLLCTRL

SYSAHBCLKCTRL

SSP0CLKDIV

UARTCLKDIV

SYSPLLSTAT

WDTCLKSEL

WDTCLKUEN

WDTCLKDIV

CLKOUTCLKSEL

CLKOUTUEN

CLKOUTCLKDIV

MAP : System memory remap
bits : 0 - 1 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 2 - 33 (32 bit)

CAPPIO0_0 : Raw reset status input PIO0_0
bits : 0 - 0 (1 bit)

CAPPIO0_8 : Raw reset status input PIO0_8
bits : 8 - 16 (9 bit)

CAPPIO0_9 : Raw reset status input PIO0_9
bits : 9 - 18 (10 bit)

CAPPIO0_10 : Raw reset status input PIO0_10
bits : 10 - 20 (11 bit)

CAPPIO0_11 : Raw reset status input PIO0_11
bits : 11 - 22 (12 bit)

CAPPIO1_0 : Raw reset status input PIO1_0
bits : 12 - 24 (13 bit)

CAPPIO1_1 : Raw reset status input PIO1_1
bits : 13 - 26 (14 bit)

CAPPIO1_2 : Raw reset status input PIO1_2
bits : 14 - 28 (15 bit)

CAPPIO1_3 : Raw reset status input PIO1_3
bits : 15 - 30 (16 bit)

RESERVED : Reserved.
bits : 16 - 33 (18 bit)

CAPPIO1_6 : Raw reset status input PIO1_6
bits : 18 - 36 (19 bit)

CAPPIO1_7 : Raw reset status input PIO1_7
bits : 19 - 38 (20 bit)

RESERVED : Reserved.
bits : 20 - 51 (32 bit)

RESERVED : Reserved.
bits : 20 - 51 (32 bit)

BODRSTLEV : BOD reset level
bits : 0 - 1 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

BODINTVAL : BOD interrupt level
bits : 2 - 5 (4 bit)

Enumeration: ENUM

End of enumeration elements list.

BODRSTENA : BOD reset enable
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 5 - 36 (32 bit)

CAL : System tick timer calibration value
bits : 0 - 25 (26 bit)

RESERVED : Reserved
bits : 26 - 57 (32 bit)

BYPASS : Bypass system oscillator
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

FREQRANGE : Determines frequency range for Low-power oscillator.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 2 - 33 (32 bit)

APRPIO0_0 : Edge select for start logic input PIO0_0
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

APRPIO0_8 : Edge select for start logic input PIO0_8
bits : 8 - 16 (9 bit)

Enumeration: ENUM

End of enumeration elements list.

APRPIO0_9 : Edge select for start logic input PIO0_9
bits : 9 - 18 (10 bit)

Enumeration: ENUM

End of enumeration elements list.

APRPIO0_10 : Edge select for start logic input PIO0_10
bits : 10 - 20 (11 bit)

Enumeration: ENUM

End of enumeration elements list.

APRPIO0_11 : Edge select for start logic input PIO0_11
bits : 11 - 22 (12 bit)

Enumeration: ENUM

End of enumeration elements list.

APRPIO1_0 : Edge select for start logic input PIO1_0.
bits : 12 - 24 (13 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 13 - 44 (32 bit)

RESERVED : Reserved
bits : 13 - 44 (32 bit)

ERPIO0_0 : Enable start signal for start logic input PIO0_0
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

ERPIO0_8 : Enable start signal for start logic input PIO0_8
bits : 8 - 16 (9 bit)

Enumeration: ENUM

End of enumeration elements list.

ERPIO0_9 : Enable start signal for start logic input PIO0_9
bits : 9 - 18 (10 bit)

Enumeration: ENUM

End of enumeration elements list.

ERPIO0_10 : Enable start signal for start logic input PIO0_10
bits : 10 - 20 (11 bit)

Enumeration: ENUM

End of enumeration elements list.

ERPIO0_11 : Enable start signal for start logic input PIO0_11
bits : 11 - 22 (12 bit)

Enumeration: ENUM

End of enumeration elements list.

ERPIO1_0 : Enable start signal for start logic input PIO1_0
bits : 12 - 24 (13 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Do not set reserved bits in this register to one.
bits : 13 - 44 (32 bit)

RESERVED : Reserved. Do not set reserved bits in this register to one.
bits : 13 - 44 (32 bit)

RSRPIO0_0 : Start signal reset for start logic input PIO0_0
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RSRPIO0_8 : Start signal reset for start logic input PIO0_8
bits : 8 - 16 (9 bit)

Enumeration: ENUM

End of enumeration elements list.

RSRPIO0_9 : Start signal reset for start logic input PIO0_9
bits : 9 - 18 (10 bit)

Enumeration: ENUM

End of enumeration elements list.

RSRPIO0_10 : Start signal reset for start logic input PIO0_10
bits : 10 - 20 (11 bit)

Enumeration: ENUM

End of enumeration elements list.

RSRPIO0_11 : Start signal reset for start logic input PIO0_11
bits : 11 - 22 (12 bit)

Enumeration: ENUM

End of enumeration elements list.

RSRPIO1_0 : Start signal reset for start logic input PIO1_0
bits : 12 - 24 (13 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 13 - 44 (32 bit)

RESERVED : Reserved
bits : 13 - 44 (32 bit)

SRPIO0_0 : Start signal status for start logic input 0PIO0_0
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

SRPIO0_8 : Start signal status for start logic input PIO0_8
bits : 8 - 16 (9 bit)

Enumeration: ENUM

End of enumeration elements list.

SRPIO0_9 : Start signal status for start logic input PIO0_9
bits : 9 - 18 (10 bit)

Enumeration: ENUM

End of enumeration elements list.

SRPIO0_10 : Start signal status for start logic input PIO0_10
bits : 10 - 20 (11 bit)

Enumeration: ENUM

End of enumeration elements list.

SRPIO0_11 : Start signal status for start logic input PIO0_11
bits : 11 - 22 (12 bit)

Enumeration: ENUM

End of enumeration elements list.

SRPIO1_0 : Start signal status for start logic input PIO1_0
bits : 12 - 24 (13 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 13 - 44 (32 bit)

RESERVED : Reserved
bits : 13 - 44 (32 bit)

BOD_PD : BOD power-down control in Deep-sleep mode, see Table 35.
bits : 3 - 6 (4 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Always write these bits as 11.
bits : 4 - 9 (6 bit)

WDTOSC_PD : Watchdog oscillator power control in Deep-sleep mode, see Table 35.
bits : 6 - 12 (7 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Always write this bit as 1.
bits : 7 - 14 (8 bit)

RESERVED : Reserved. Always write these bits as 000.
bits : 8 - 18 (11 bit)

RESERVED : Reserved. Always write these bits as 11.
bits : 11 - 23 (13 bit)

RESERVED : Reserved
bits : 13 - 44 (32 bit)

RESERVED : Reserved
bits : 13 - 44 (32 bit)

IRCOUT_PD : IRC oscillator output wake-up configuration
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

IRC_PD : IRC oscillator power-down wake-up configuration
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

FLASH_PD : Flash wake-up configuration
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

BOD_PD : BOD wake-up configuration
bits : 3 - 6 (4 bit)

Enumeration: ENUM

End of enumeration elements list.

ADC_PD : ADC wake-up configuration
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

SYSOSC_PD : System oscillator wake-up configuration
bits : 5 - 10 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

WDTOSC_PD : Watchdog oscillator wake-up configuration
bits : 6 - 12 (7 bit)

Enumeration: ENUM

End of enumeration elements list.

SYSPLL_PD : System PLL wake-up configuration
bits : 7 - 14 (8 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Always write this bit as 0.
bits : 9 - 18 (10 bit)

RESERVED : Reserved. Always write this bit as 1.
bits : 10 - 20 (11 bit)

RESERVED : Reserved. Always write this bit as 1.
bits : 11 - 22 (12 bit)

RESERVED : Reserved. Always write this bit as 0.
bits : 12 - 24 (13 bit)

RESERVED : Reserved. Always write these bits as 111.
bits : 13 - 28 (16 bit)

RESERVED : Reserved
bits : 16 - 47 (32 bit)

RESERVED : Reserved
bits : 16 - 47 (32 bit)

IRCOUT_PD : IRC oscillator output power-down
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

IRC_PD : IRC oscillator power-down
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

FLASH_PD : Flash power-down
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

BOD_PD : BOD power-down
bits : 3 - 6 (4 bit)

Enumeration: ENUM

End of enumeration elements list.

ADC_PD : ADC power-down
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

SYSOSC_PD : System oscillator power-down
bits : 5 - 10 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

WDTOSC_PD : Watchdog oscillator power-down
bits : 6 - 12 (7 bit)

Enumeration: ENUM

End of enumeration elements list.

SYSPLL_PD : System PLL power-down
bits : 7 - 14 (8 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Always write this bit as 0.
bits : 9 - 18 (10 bit)

RESERVED : Reserved. Always write this bit as 1.
bits : 10 - 20 (11 bit)

RESERVED : Reserved. Always write this bit as 1.
bits : 11 - 22 (12 bit)

RESERVED : Reserved. Always write this bit as 0.
bits : 12 - 24 (13 bit)

RESERVED : Reserved. Always write these bits as 111.
bits : 13 - 28 (16 bit)

RESERVED : Reserved
bits : 16 - 47 (32 bit)

RESERVED : Reserved
bits : 16 - 47 (32 bit)

DIVSEL : Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64
bits : 0 - 4 (5 bit)

FREQSEL : Select watchdog oscillator analog output frequency (Fclkana).
bits : 5 - 13 (9 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 9 - 40 (32 bit)

TRIM : Trim value
bits : 0 - 7 (8 bit)

RESERVED : Reserved
bits : 9 - 40 (32 bit)

POR : POR reset status
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

EXTRST : Status of the external RESET pin
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

WDT : Status of the Watchdog reset
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

BOD : Status of the Brown-out detect reset
bits : 3 - 6 (4 bit)

Enumeration: ENUM

End of enumeration elements list.

SYSRST : Status of the software system reset
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 5 - 36 (32 bit)

DEVICEID : Part ID numbers for LPC1102/04 parts LPC1102 = 0x2500 102B LPC1104 = 0x2548 102B
bits : 0 - 31 (32 bit)

SSP0_RST_N : SPI0 reset control
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 1 - 32 (32 bit)

SEL : System PLL clock source
bits : 0 - 1 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 2 - 33 (32 bit)

ENA : Enable system PLL clock source update
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 1 - 32 (32 bit)

SEL : Clock source for main clock
bits : 0 - 1 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 2 - 33 (32 bit)

ENA : Enable main clock source update
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 1 - 32 (32 bit)

DIV : System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.
bits : 0 - 7 (8 bit)

RESERVED : Reserved
bits : 8 - 39 (32 bit)

MSEL : Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ration M = 32
bits : 0 - 4 (5 bit)

PSEL : Post divider ratio P. The division ratio is 2 x P.
bits : 5 - 11 (7 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Do not write ones to reserved bits.
bits : 7 - 38 (32 bit)

SYS : Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M0 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

ROM : Enables clock for ROM.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

RAM : Enables clock for RAM.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

FLASHREG : Enables clock for flash register interface.
bits : 3 - 6 (4 bit)

Enumeration: ENUM

End of enumeration elements list.

FLASHARRAY : Enables clock for flash array access.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

GPIO : Enables clock for GPIO.
bits : 6 - 12 (7 bit)

Enumeration: ENUM

End of enumeration elements list.

CT16B0 : Enables clock for 16-bit counter/timer 0.
bits : 7 - 14 (8 bit)

Enumeration: ENUM

End of enumeration elements list.

CT16B1 : Enables clock for 16-bit counter/timer 1.
bits : 8 - 16 (9 bit)

Enumeration: ENUM

End of enumeration elements list.

CT32B0 : Enables clock for 32-bit counter/timer 0.
bits : 9 - 18 (10 bit)

Enumeration: ENUM

End of enumeration elements list.

CT32B1 : Enables clock for 32-bit counter/timer 1.
bits : 10 - 20 (11 bit)

Enumeration: ENUM

End of enumeration elements list.

SSP0 : Enables clock for SPI0.
bits : 11 - 22 (12 bit)

Enumeration: ENUM

End of enumeration elements list.

UART : Enables clock for UART.
bits : 12 - 24 (13 bit)

Enumeration: ENUM

End of enumeration elements list.

ADC : Enables clock for ADC.
bits : 13 - 26 (14 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 14 - 28 (15 bit)

WDT : Enables clock for WDT.
bits : 15 - 30 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

IOCON : Enables clock for I/O configuration block.
bits : 16 - 32 (17 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 17 - 48 (32 bit)

RESERVED : Reserved
bits : 17 - 48 (32 bit)

DIV : SPI0_PCLK clock divider values 0: Disable SPI0_PCLK. 1: Divide by 1. to 255: Divide by 255.
bits : 0 - 7 (8 bit)

RESERVED : Reserved
bits : 8 - 39 (32 bit)

DIV : UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255.
bits : 0 - 7 (8 bit)

RESERVED : Reserved
bits : 8 - 39 (32 bit)

LOCK : PLL lock status
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 1 - 32 (32 bit)

SEL : WDT clock source
bits : 0 - 1 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 2 - 33 (32 bit)

ENA : Enable WDT clock source update
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 1 - 32 (32 bit)

DIV : WDT clock divider values 0: Disable WDCLK. 1: Divide by 1. to 255: Divide by 255.
bits : 0 - 7 (8 bit)

RESERVED : Reserved
bits : 8 - 39 (32 bit)

SEL : CLKOUT clock source
bits : 0 - 1 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 2 - 33 (32 bit)

ENA : Enable CLKOUT clock source update
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 1 - 32 (32 bit)

DIV : Clock output divider values 0: Disable CLKOUT. 1: Divide by 1. to 255: Divide by 255.
bits : 0 - 7 (8 bit)

RESERVED : Reserved
bits : 8 - 39 (32 bit)