Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected
A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are 0 (as after Reset) channel 0 is selected automatically.
bits : 0 - 7 (8 bit)
CLKDIV : The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.
bits : 8 - 23 (16 bit)
BURST : Burst mode
bits : 16 - 32 (17 bit)
Enumeration: ENUM
0 : SOFTWARE_CONTROLLED_
Software-controlled mode: Conversions are software-controlled and require 11 clocks.
1 : HARDWARE_SCAN_MODE_
Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. If bit 20 in this register is set (single-burst mode), hardware clears this bit automatically after one set of conversions on all of the selected channels.
End of enumeration elements list.
CLKS : This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
bits : 17 - 36 (20 bit)
Enumeration: ENUM
0x0 : 11_CLOCKS
11 clocks / 10 bits
0x1 : 10_CLOCKS
10 clocks / 9 bits
0x2 : 9_CLOCKS
9 clocks / 8 bits
0x3 : 8_CLOCKS
8 clocks / 7 bits
0x4 : 7_CLOCKS
7 clocks / 6 bits
0x5 : 6_CLOCK
6 clocks / 5 bits
0x6 : 5_CLOCKS
5 clocks / 4 bits
0x7 : 4_CLOCKS
4 clocks / 3 bits
End of enumeration elements list.
SINGLEBURST : Single-burst mode
bits : 20 - 40 (21 bit)
Enumeration: ENUM
0 : CONTINUOUS_BURST
Continuous. Burst mode can only be terminated via a software write to clear bit 16 in this register.
1 : SINGLE_BURST
Single-burst. When the burst mode is selected by writing a 1 to bit 16 in this register, the ADC cycles through a single set of conversions on the selection of channels specified in the SEL field. Once the conversion has been completed on each selected channel, bit 16 is automatically cleared and the conversions stop until a new trigger event occurs.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 21 - 43 (23 bit)
START : When the BURST bit is 0, these bits control whether/when an A/D conversion is started. All other values are reserved.
bits : 23 - 49 (27 bit)
Enumeration: ENUM
0x0 : NO_START_THIS_VALUE
No start (this value should be used when clearing PDN to 0).
0x2 : START_CONVERSION_NOW
Start conversion now.
0xE : START_CONVERSION_WHE
Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1].
0xE : START_CONVERSION_WHE
Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1].
0xE : START_CONVERSION_WHE
Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1].
0xE : START_CONVERSION_WHE
Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1].
0xE : START_CONVERSION_WHE
Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1].
0xE : START_CONVERSION_WHE
Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1].
0xE : START_CONVERSION_WHE
Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1].
End of enumeration elements list.
EDGE : This bit is significant only when the START field contains 0100-1110. In these cases:
bits : 27 - 54 (28 bit)
Enumeration: ENUM
1 : START_CONVERSION_ON_
Start conversion on a falling edge on the selected signal.
1 : START_CONVERSION_ON_
Start conversion on a falling edge on the selected signal.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 28 - 59 (32 bit)
A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Reserved. These bits always read as zeroes.
bits : 0 - 5 (6 bit)
V_VREF : When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.
bits : 6 - 21 (16 bit)
RESERVED : Reserved. These bits always read as zeroes. They allow accumulation of successive A/D values without AND-masking for at least 256 values without overflow into the CHN field.
bits : 16 - 45 (30 bit)
OVERRUN : This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the LS bits.This bit is cleared by reading this register.
bits : 30 - 60 (31 bit)
DONE : This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
bits : 31 - 62 (32 bit)
A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Reserved. These bits always read as zeroes.
bits : 0 - 5 (6 bit)
V_VREF : When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.
bits : 6 - 21 (16 bit)
RESERVED : Reserved. These bits always read as zeroes. They allow accumulation of successive A/D values without AND-masking for at least 256 values without overflow into the CHN field.
bits : 16 - 45 (30 bit)
OVERRUN : This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the LS bits.This bit is cleared by reading this register.
bits : 30 - 60 (31 bit)
DONE : This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
bits : 31 - 62 (32 bit)
A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Reserved. These bits always read as zeroes.
bits : 0 - 5 (6 bit)
V_VREF : When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.
bits : 6 - 21 (16 bit)
RESERVED : Reserved. These bits always read as zeroes. They allow accumulation of successive A/D values without AND-masking for at least 256 values without overflow into the CHN field.
bits : 16 - 45 (30 bit)
OVERRUN : This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the LS bits.This bit is cleared by reading this register.
bits : 30 - 60 (31 bit)
DONE : This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
bits : 31 - 62 (32 bit)
A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Reserved. These bits always read as zeroes.
bits : 0 - 5 (6 bit)
V_VREF : When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.
bits : 6 - 21 (16 bit)
RESERVED : Reserved. These bits always read as zeroes. They allow accumulation of successive A/D values without AND-masking for at least 256 values without overflow into the CHN field.
bits : 16 - 45 (30 bit)
OVERRUN : This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the LS bits.This bit is cleared by reading this register.
bits : 30 - 60 (31 bit)
DONE : This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
bits : 31 - 62 (32 bit)
A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Reserved. These bits always read as zeroes.
bits : 0 - 5 (6 bit)
V_VREF : When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.
bits : 6 - 21 (16 bit)
RESERVED : Reserved. These bits always read as zeroes. They allow accumulation of successive A/D values without AND-masking for at least 256 values without overflow into the CHN field.
bits : 16 - 45 (30 bit)
OVERRUN : This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the LS bits.This bit is cleared by reading this register.
bits : 30 - 60 (31 bit)
DONE : This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
bits : 31 - 62 (32 bit)
A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Reserved. These bits always read as zeroes.
bits : 0 - 5 (6 bit)
V_VREF : When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.
bits : 6 - 21 (16 bit)
RESERVED : Reserved. These bits always read as zeroes. They allow accumulation of successive A/D values without AND-masking for at least 256 values without overflow into the CHN field.
bits : 16 - 45 (30 bit)
OVERRUN : This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the LS bits.This bit is cleared by reading this register.
bits : 30 - 60 (31 bit)
DONE : This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
bits : 31 - 62 (32 bit)
A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Reserved. These bits always read as zeroes.
bits : 0 - 5 (6 bit)
V_VREF : When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.
bits : 6 - 21 (16 bit)
RESERVED : Reserved. These bits always read as zeroes. They allow accumulation of successive A/D values without AND-masking for at least 256 values without overflow into the CHN field.
bits : 16 - 45 (30 bit)
OVERRUN : This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the LS bits.This bit is cleared by reading this register.
bits : 30 - 60 (31 bit)
DONE : This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
bits : 31 - 62 (32 bit)
A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Reserved. These bits always read as zeroes.
bits : 0 - 5 (6 bit)
V_VREF : When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.
bits : 6 - 21 (16 bit)
RESERVED : Reserved. These bits always read as zeroes. They allow accumulation of successive A/D values without AND-masking for at least 256 values without overflow into the CHN field.
bits : 16 - 45 (30 bit)
OVERRUN : This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the LS bits.This bit is cleared by reading this register.
bits : 30 - 60 (31 bit)
DONE : This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
bits : 31 - 62 (32 bit)
A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag.
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DONE : These bits mirror the DONE status flags that appear in the result register for each A/D channel.
bits : 0 - 7 (8 bit)
OVERRUN : These bits mirror the OVERRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously.
bits : 8 - 23 (16 bit)
ADINT : This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.
bits : 16 - 32 (17 bit)
RESERVED : Reserved. Always 0.
bits : 17 - 48 (32 bit)
A/D Global Data Register. Contains the result of the most recent A/D conversion.
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
V_VREF : When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.
bits : 6 - 21 (16 bit)
RESERVED : Reserved. These bits always read as zeroes. They allow accumulation of successive A/D values without AND-masking, for at least 256 values without overflow into the CHN field.
bits : 16 - 39 (24 bit)
RESERVED : Reserved. These bits always read as zeroes. They allow accumulation of successive A/D values without AND-masking, for at least 256 values without overflow into the CHN field.
bits : 16 - 39 (24 bit)
CHN : These bits contain the channel from which the LS bits were converted.
bits : 24 - 50 (27 bit)
RESERVED : Reserved. These bits always read as zeroes.
bits : 27 - 56 (30 bit)
OVERRUN : This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the LS bits. In non-FIFO operation, this bit is cleared by reading this register.
bits : 30 - 60 (31 bit)
DONE : This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.
bits : 31 - 62 (32 bit)
A/D Select Register. Selects between external pins and internal sources.
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Reserved. Always write zeroes to these bits.
bits : 0 - 9 (10 bit)
AD5SEL : This field selects the source signal for channel 5.
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : AD5_PIN
AD5 pin
0x1 : NO_CONNECTION_OR_LOA
No connection or load
0x2 : CORE_VOLTAGE_REGULAT
Core voltage regulator output (1.2 to 1.8V)
0x3 : RESERVED_DO_NOT_PRO
Reserved. Do not program this value.
End of enumeration elements list.
AD6SEL : This field selects the source signal for channel 6.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : AD6_PIN
AD6 pin
0x1 : NO_CONNECTION_OR_LOA
No connection or load
0x2 : INTERNAL_VOLTAGE_REF
Internal voltage reference
0x3 : RESERVED_DO_NOT_PRO
Reserved. Do not program this value.
End of enumeration elements list.
AD7SEL : This field selects the source signal for channel 7.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : AD7_PIN
AD7 pin
0x1 : NO_CONNECTION_OR_LOA
No connection or load
0x2 : TEMPERATURE_SENSOR
Temperature sensor
0x3 : RESERVED_DO_NOT_PRO
Reserved. Do not program this value.
End of enumeration elements list.
RESERVED : Reserved. Always write zeroes to these bits.
bits : 16 - 47 (32 bit)
A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADINTEN : These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.
bits : 0 - 7 (8 bit)
ADGINTEN : When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts.
bits : 8 - 16 (9 bit)
RESERVED : Reserved. Always 0.
bits : 9 - 40 (32 bit)
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