\n
address_offset : 0x0 Bytes (0x0)
size : 0xFFFFFF byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x0 Bytes (0x0)
size : 0xFFFFFF byte (0x0)
mem_usage : registers
protection :
Port n data register for pins PIOn_0 to PIOn_11
address_offset : 0x3FFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
bits : 0 - 0 (1 bit)
DATA1 : Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
bits : 1 - 2 (2 bit)
DATA2 : Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
bits : 2 - 4 (3 bit)
DATA3 : Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
bits : 3 - 6 (4 bit)
DATA4 : Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
bits : 4 - 8 (5 bit)
DATA5 : Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
bits : 5 - 10 (6 bit)
DATA6 : Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
bits : 6 - 12 (7 bit)
DATA7 : Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
bits : 7 - 14 (8 bit)
DATA8 : Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
bits : 8 - 16 (9 bit)
DATA9 : Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
bits : 9 - 18 (10 bit)
DATA10 : Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
bits : 10 - 20 (11 bit)
DATA11 : Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.
bits : 11 - 22 (12 bit)
RESERVED : Reserved
bits : 12 - 43 (32 bit)
Data direction register for port n
address_offset : 0x8000 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO0 : Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
bits : 0 - 0 (1 bit)
IO1 : Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
bits : 1 - 2 (2 bit)
IO2 : Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
bits : 2 - 4 (3 bit)
IO3 : Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
bits : 3 - 6 (4 bit)
IO4 : Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
bits : 4 - 8 (5 bit)
IO5 : Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
bits : 5 - 10 (6 bit)
IO6 : Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
bits : 6 - 12 (7 bit)
IO7 : Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
bits : 7 - 14 (8 bit)
IO8 : Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
bits : 8 - 16 (9 bit)
IO9 : Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
bits : 9 - 18 (10 bit)
IO10 : Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
bits : 10 - 20 (11 bit)
IO11 : Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
bits : 11 - 22 (12 bit)
RESERVED : Reserved
bits : 12 - 43 (32 bit)
Interrupt sense register for port n
address_offset : 0x8004 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENSE0 : Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
bits : 0 - 0 (1 bit)
ISENSE1 : Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
bits : 1 - 2 (2 bit)
ISENSE2 : Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
bits : 2 - 4 (3 bit)
ISENSE3 : Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
bits : 3 - 6 (4 bit)
ISENSE4 : Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
bits : 4 - 8 (5 bit)
ISENSE5 : Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
bits : 5 - 10 (6 bit)
ISENSE6 : Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
bits : 6 - 12 (7 bit)
ISENSE7 : Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
bits : 7 - 14 (8 bit)
ISENSE8 : Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
bits : 8 - 16 (9 bit)
ISENSE9 : Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
bits : 9 - 18 (10 bit)
ISENSE10 : Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
bits : 10 - 20 (11 bit)
ISENSE11 : Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
bits : 11 - 22 (12 bit)
RESERVED : Reserved
bits : 12 - 43 (32 bit)
Interrupt both edges register for port n
address_offset : 0x8008 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IBE0 : Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
bits : 0 - 0 (1 bit)
IBE1 : Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
bits : 1 - 2 (2 bit)
IBE2 : Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
bits : 2 - 4 (3 bit)
IBE3 : Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
bits : 3 - 6 (4 bit)
IBE4 : Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
bits : 4 - 8 (5 bit)
IBE5 : Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
bits : 5 - 10 (6 bit)
IBE6 : Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
bits : 6 - 12 (7 bit)
IBE7 : Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
bits : 7 - 14 (8 bit)
IBE8 : Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
bits : 8 - 16 (9 bit)
IBE9 : Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
bits : 9 - 18 (10 bit)
IBE10 : Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
bits : 10 - 20 (11 bit)
IBE11 : Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
bits : 11 - 22 (12 bit)
RESERVED : Reserved
bits : 12 - 43 (32 bit)
Interrupt event register for port n
address_offset : 0x800C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IEV0 : Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
bits : 0 - 0 (1 bit)
IEV1 : Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
bits : 1 - 2 (2 bit)
IEV2 : Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
bits : 2 - 4 (3 bit)
IEV3 : Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
bits : 3 - 6 (4 bit)
IEV4 : Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
bits : 4 - 8 (5 bit)
IEV5 : Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
bits : 5 - 10 (6 bit)
IEV6 : Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
bits : 6 - 12 (7 bit)
IEV7 : Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
bits : 7 - 14 (8 bit)
IEV8 : Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
bits : 8 - 16 (9 bit)
IEV9 : Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
bits : 9 - 18 (10 bit)
IEV10 : Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
bits : 10 - 20 (11 bit)
IEV11 : Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
bits : 11 - 22 (12 bit)
RESERVED : Reserved
bits : 12 - 43 (32 bit)
Interrupt mask register for port n
address_offset : 0x8010 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK0 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
bits : 0 - 0 (1 bit)
MASK1 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
bits : 1 - 2 (2 bit)
MASK2 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
bits : 2 - 4 (3 bit)
MASK3 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
bits : 3 - 6 (4 bit)
MASK4 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
bits : 4 - 8 (5 bit)
MASK5 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
bits : 5 - 10 (6 bit)
MASK6 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
bits : 6 - 12 (7 bit)
MASK7 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
bits : 7 - 14 (8 bit)
MASK8 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
bits : 8 - 16 (9 bit)
MASK9 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
bits : 9 - 18 (10 bit)
MASK10 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
bits : 10 - 20 (11 bit)
MASK11 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
bits : 11 - 22 (12 bit)
RESERVED : Reserved
bits : 12 - 43 (32 bit)
Raw interrupt status register for port n
address_offset : 0x8014 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RAWST0 : Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
bits : 0 - 0 (1 bit)
RAWST1 : Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
bits : 1 - 2 (2 bit)
RAWST2 : Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
bits : 2 - 4 (3 bit)
RAWST3 : Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
bits : 3 - 6 (4 bit)
RAWST4 : Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
bits : 4 - 8 (5 bit)
RAWST5 : Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
bits : 5 - 10 (6 bit)
RAWST6 : Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
bits : 6 - 12 (7 bit)
RAWST7 : Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
bits : 7 - 14 (8 bit)
RAWST8 : Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
bits : 8 - 16 (9 bit)
RAWST9 : Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
bits : 9 - 18 (10 bit)
RAWST10 : Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
bits : 10 - 20 (11 bit)
RAWST11 : Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
bits : 11 - 22 (12 bit)
RESERVED : Reserved
bits : 12 - 43 (32 bit)
Masked interrupt status register for port n
address_offset : 0x8018 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MASK0 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
bits : 0 - 0 (1 bit)
MASK1 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
bits : 1 - 2 (2 bit)
MASK2 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
bits : 2 - 4 (3 bit)
MASK3 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
bits : 3 - 6 (4 bit)
MASK4 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
bits : 4 - 8 (5 bit)
MASK5 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
bits : 5 - 10 (6 bit)
MASK6 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
bits : 6 - 12 (7 bit)
MASK7 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
bits : 7 - 14 (8 bit)
MASK8 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
bits : 8 - 16 (9 bit)
MASK9 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
bits : 9 - 18 (10 bit)
MASK10 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
bits : 10 - 20 (11 bit)
MASK11 : Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
bits : 11 - 22 (12 bit)
RESERVED : Reserved
bits : 12 - 43 (32 bit)
Interrupt clear register for port n
address_offset : 0x801C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR0 : Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
bits : 0 - 0 (1 bit)
CLR1 : Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
bits : 1 - 2 (2 bit)
CLR2 : Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
bits : 2 - 4 (3 bit)
CLR3 : Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
bits : 3 - 6 (4 bit)
CLR4 : Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
bits : 4 - 8 (5 bit)
CLR5 : Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
bits : 5 - 10 (6 bit)
CLR6 : Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
bits : 6 - 12 (7 bit)
CLR7 : Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
bits : 7 - 14 (8 bit)
CLR8 : Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
bits : 8 - 16 (9 bit)
CLR9 : Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
bits : 9 - 18 (10 bit)
CLR10 : Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
bits : 10 - 20 (11 bit)
CLR11 : Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
bits : 11 - 22 (12 bit)
RESERVED : Reserved
bits : 12 - 43 (32 bit)
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