\n
address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected
Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0INT : Interrupt flag for match channel 0.
bits : 0 - 0 (1 bit)
MR1INT : Interrupt flag for match channel 1.
bits : 1 - 2 (2 bit)
MR2INT : Interrupt flag for match channel 2.
bits : 2 - 4 (3 bit)
MR3INT : Interrupt flag for match channel 3.
bits : 3 - 6 (4 bit)
CR0INT : Interrupt flag for capture channel 0 event.
bits : 4 - 8 (5 bit)
CR1INT : Interrupt flag for capture channel 1 event.
bits : 5 - 10 (6 bit)
CR2INT : Interrupt flag for capture channel 2 event.
bits : 6 - 12 (7 bit)
RESERVED : Reserved
bits : 7 - 38 (32 bit)
Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC : Prescale counter value.
bits : 0 - 31 (32 bit)
Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0I : Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR0R : Reset on MR0: the TC will be reset if MR0 matches it.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR0S : Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR1I : Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR1R : Reset on MR1: the TC will be reset if MR1 matches it.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR1S : Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR2I : Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR2R : Reset on MR2: the TC will be reset if MR2 matches it.
bits : 7 - 14 (8 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR2S : Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
bits : 8 - 16 (9 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR3I : Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
bits : 9 - 18 (10 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR3R : Reset on MR3: the TC will be reset if MR3 matches it.
bits : 10 - 20 (11 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR3S : Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
bits : 11 - 22 (12 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 12 - 43 (32 bit)
Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAP0RE : Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
1 : ENABLED
Enabled.
0 : DISABLED
Disabled.
End of enumeration elements list.
CAP0FE : Falling edge of capture channel 0:: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
1 : ENABLED
Enabled.
0 : DISABLED
Disabled.
End of enumeration elements list.
CAP0I : Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
1 : ENABLED
Enabled.
0 : DISABLED
Disabled.
End of enumeration elements list.
CAP1RE : Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
1 : ENABLED
Enabled.
0 : DISABLED
Disabled.
End of enumeration elements list.
CAP1FE : Falling edge of capture channel 1:: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
1 : ENABLED
Enabled.
0 : DISABLED
Disabled.
End of enumeration elements list.
CAP1I : Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
1 : ENABLED
Enabled.
0 : DISABLED
Disabled.
End of enumeration elements list.
CAP2RE : Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
1 : ENABLED
Enabled.
0 : DISABLED
Disabled.
End of enumeration elements list.
CAP2FE : Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC.
bits : 7 - 14 (8 bit)
Enumeration: ENUM
1 : ENABLED
Enabled.
0 : DISABLED
Disabled.
End of enumeration elements list.
CAP2I : Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
bits : 8 - 16 (9 bit)
Enumeration: ENUM
1 : ENABLED
Enabled.
0 : DISABLED
Disabled.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 9 - 40 (32 bit)
Capture Register. CR is loaded with the value of TC when there is an event on the CAP input.
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP : Timer counter capture value.
bits : 0 - 31 (32 bit)
Capture Register. CR is loaded with the value of TC when there is an event on the CAP input.
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP : Timer counter capture value.
bits : 0 - 31 (32 bit)
Capture Register. CR is loaded with the value of TC when there is an event on the CAP input.
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP : Timer counter capture value.
bits : 0 - 31 (32 bit)
External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0].
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM0 : External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bits : 0 - 0 (1 bit)
EM1 : External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bits : 1 - 2 (2 bit)
EM2 : External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bits : 2 - 4 (3 bit)
EM3 : External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bits : 3 - 6 (4 bit)
EMC0 : External Match Control 0. Determines the functionality of External Match 0.
bits : 4 - 9 (6 bit)
Enumeration: ENUM
0x0 : NOP
Do Nothing.
0x1 : CLEAR
Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out).
0x2 : SET
Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out).
0x3 : TOGGLE
Toggle the corresponding External Match bit/output.
End of enumeration elements list.
EMC1 : External Match Control 1. Determines the functionality of External Match 1.
bits : 6 - 13 (8 bit)
Enumeration: ENUM
0x0 : NOP
Do Nothing.
0x1 : CLEAR
Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out).
0x2 : SET
Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out).
0x3 : TOGGLE
Toggle the corresponding External Match bit/output.
End of enumeration elements list.
EMC2 : External Match Control 2. Determines the functionality of External Match 2.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : NOP
Do Nothing.
0x1 : CLEAR
Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out).
0x2 : SET
Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out).
0x3 : TOGGLE
Toggle the corresponding External Match bit/output.
End of enumeration elements list.
EMC3 : External Match Control 3. Determines the functionality of External Match 3.
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : NOP
Do Nothing.
0x1 : CLEAR
Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out).
0x2 : SET
Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out).
0x3 : TOGGLE
Toggle the corresponding External Match bit/output.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 12 - 43 (32 bit)
Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Counter enable.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
The counters are disabled.
1 : ENABLED
The Timer Counter and Prescale Counter are enabled for counting.
End of enumeration elements list.
CRST : Counter reset.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : NOP
Do nothing.
1 : RESET
The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 2 - 33 (32 bit)
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTM : Counter/Timer Mode. This field selects which rising PCLK edges can increment the Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.
bits : 0 - 1 (2 bit)
Enumeration: ENUM
0x0 : TIMER_MODE
Timer Mode. Increments every rising PCLK edge
0x1 : COUNTER_MODE_RISING
Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
0x2 : COUNTER_MODE_FALLING
Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
0x3 : COUNTER_MODE_DUAL_ED
Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
End of enumeration elements list.
CIS : Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Value 0x3 is reserved.
bits : 2 - 5 (4 bit)
Enumeration: ENUM
0x0 : CAPTURE_CHANNEL_0
Capture channel 0.
0x1 : CAPTURE_CHANNEL_1
Capture channel 1.
0x2 : CAPTURE_CHANNEL_2
Capture channel 2.
End of enumeration elements list.
ENCC : Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.
bits : 4 - 8 (5 bit)
SELCC : Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.
bits : 5 - 12 (8 bit)
Enumeration: ENUM
0x0 : CAP0RISING
Rising Edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
0x1 : CAP0FALLING
Falling Edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
0x2 : CAP1RISING
Rising Edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
0x3 : CAP1FALLING
Falling Edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
0x4 : CAP2RISING
Rising Edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
0x5 : CAP2FALLING
Falling Edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)
PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0].
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMEN0 : PWM mode enable for channel0.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : EM0
CT32Bn_MAT0 is controlled by EM0.
1 : PWM
PWM mode is enabled for CT32Bn_MAT0.
End of enumeration elements list.
PWMEN1 : PWM mode enable for channel1.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : EM1
CT32Bn_MAT01 is controlled by EM1.
1 : PWM
PWM mode is enabled for CT32Bn_MAT1.
End of enumeration elements list.
PWMEN2 : PWM mode enable for channel2.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : EM2
CT32Bn_MAT2 is controlled by EM2.
1 : PWM
PWM mode is enabled for CT32Bn_MAT2.
End of enumeration elements list.
PWMEN3 : PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : EM3
CT32Bn_MAT3 is controlled by EM3.
1 : PWM
PWM mode is enabled for CT132Bn_MAT3.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 4 - 35 (32 bit)
Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCVAL : Timer counter value.
bits : 0 - 31 (32 bit)
Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCVAL : Prescaler value.
bits : 0 - 31 (32 bit)
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