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CEC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CFGR

CSR

TXD

RXD

OAR

PRES

ESR


CFGR

configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PE IE BTEM BPEM

PE : Peripheral enable
bits : 0 - 0 (1 bit)

IE : Interrupt enable
bits : 1 - 1 (1 bit)

BTEM : Bit timing error mode
bits : 2 - 2 (1 bit)

BPEM : Bit period error mode
bits : 3 - 3 (1 bit)


CSR

CEC control and status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSOM TEOM TERR TBTRF RSOM REOM RERR RBTF

TSOM : Tx start of message
bits : 0 - 0 (1 bit)

TEOM : Tx end of message
bits : 1 - 1 (1 bit)

TERR : Tx error
bits : 2 - 2 (1 bit)

TBTRF : Tx byte transfer request or block transfer finished
bits : 3 - 3 (1 bit)

RSOM : Rx start of message
bits : 4 - 4 (1 bit)

REOM : Rx end of message
bits : 5 - 5 (1 bit)

RERR : Rx error
bits : 6 - 6 (1 bit)

RBTF : Rx byte/block transfer finished
bits : 7 - 7 (1 bit)


TXD

CEC Tx data register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXD TXD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXD

TXD : Tx Data register
bits : 0 - 7 (8 bit)


RXD

CEC Rx data register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXD RXD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXD

RXD : Rx data
bits : 0 - 7 (8 bit)


OAR

CEC own address register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OAR OAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OA

OA : Own address
bits : 0 - 3 (4 bit)


PRES

Rx Data Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRES PRES read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESC

PRESC : CEC Rx Data Register
bits : 0 - 13 (14 bit)


ESR

CEC error status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ESR ESR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTE BPE RBTFE SBE ACKE LINE TBTFE

BTE : Bit timing error
bits : 0 - 0 (1 bit)

BPE : Bit period error
bits : 1 - 1 (1 bit)

RBTFE : Rx block transfer finished error
bits : 2 - 2 (1 bit)

SBE : Start bit error
bits : 3 - 3 (1 bit)

ACKE : Block acknowledge error
bits : 4 - 4 (1 bit)

LINE : Line error
bits : 5 - 5 (1 bit)

TBTFE : Tx block transfer finished error
bits : 6 - 6 (1 bit)



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