Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected
Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0INT : Interrupt flag for match channel 0.
bits : 0 - 0 (1 bit)
MR1INT : Interrupt flag for match channel 1.
bits : 1 - 2 (2 bit)
MR2INT : Interrupt flag for match channel 2.
bits : 2 - 4 (3 bit)
MR3INT : Interrupt flag for match channel 3.
bits : 3 - 6 (4 bit)
CR0INT : Interrupt flag for capture channel 0 event.
bits : 4 - 8 (5 bit)
CR1INT : Interrupt flag for capture channel 1 event.
bits : 5 - 10 (6 bit)
RESERVED : Reserved
bits : 6 - 37 (32 bit)
Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC : Prescale counter value.
bits : 0 - 31 (32 bit)
Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0I : Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR0R : Reset on MR0: the TC will be reset if MR0 matches it.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR0S : Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR1I : Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR1R : Reset on MR1: the TC will be reset if MR1 matches it.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR1S : Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR2I : Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR2R : Reset on MR2: the TC will be reset if MR2 matches it.
bits : 7 - 14 (8 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR2S : Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
bits : 8 - 16 (9 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR3I : Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
bits : 9 - 18 (10 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR3R : Reset on MR3: the TC will be reset if MR3 matches it.
bits : 10 - 20 (11 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
MR3S : Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
bits : 11 - 22 (12 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 12 - 43 (32 bit)
Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAP0RE : Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
CAP0FE : Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
CAP0I : Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
CAP1RE : Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
CAP1FE : Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
CAP1I : Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
1 : ENABLED
Enabled
0 : DISABLED
Disabled
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 6 - 37 (32 bit)
Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0].
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM0 : External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bits : 0 - 0 (1 bit)
EM1 : External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bits : 1 - 2 (2 bit)
EM2 : External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bits : 2 - 4 (3 bit)
EM3 : External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bits : 3 - 6 (4 bit)
EMC0 : External Match Control 0. Determines the functionality of External Match 0.
bits : 4 - 9 (6 bit)
Enumeration: ENUM
0x0 : DO_NOTHING_
Do Nothing.
0x1 : CLEAR_THE_CORRESPOND
Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out).
0x2 : SET_THE_CORRESPONDIN
Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out).
0x3 : TOGGLE_THE_CORRESPON
Toggle the corresponding External Match bit/output.
End of enumeration elements list.
EMC1 : External Match Control 1. Determines the functionality of External Match 1.
bits : 6 - 13 (8 bit)
Enumeration: ENUM
0x0 : DO_NOTHING_
Do Nothing.
0x1 : CLEAR_THE_CORRESPOND
Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out).
0x2 : SET_THE_CORRESPONDIN
Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out).
0x3 : TOGGLE_THE_CORRESPON
Toggle the corresponding External Match bit/output.
End of enumeration elements list.
EMC2 : External Match Control 2. Determines the functionality of External Match 2.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : DO_NOTHING_
Do Nothing.
0x1 : CLEAR_THE_CORRESPOND
Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out).
0x2 : SET_THE_CORRESPONDIN
Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out).
0x3 : TOGGLE_THE_CORRESPON
Toggle the corresponding External Match bit/output.
End of enumeration elements list.
EMC3 : External Match Control 3. Determines the functionality of External Match 3.
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : DO_NOTHING_
Do Nothing.
0x1 : CLEAR_THE_CORRESPOND
Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out).
0x2 : SET_THE_CORRESPONDIN
Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out).
0x3 : TOGGLE_THE_CORRESPON
Toggle the corresponding External Match bit/output.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 12 - 43 (32 bit)
Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
bits : 0 - 0 (1 bit)
CRST : When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
bits : 1 - 2 (2 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 2 - 33 (32 bit)
Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.
address_offset : 0x58 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP : Timer counter capture value.
bits : 0 - 31 (32 bit)
Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTM : Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge
bits : 0 - 1 (2 bit)
Enumeration: ENUM
0x0 : TIMER_MODE_EVERY_RI
Timer Mode: every rising PCLK edge
0x1 : COUNTER_MODE_TC_IS_
Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.
0x2 : COUNTER_MODE_TC_IS_
Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.
0x2 : COUNTER_MODE_TC_IS_
Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.
End of enumeration elements list.
CIS : Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:
bits : 2 - 5 (4 bit)
Enumeration: ENUM
0x0 : CT32BN_CAP0
CT32Bn_CAP0
0x1 : CT32BN_CAP1
CT32Bn_CAP1
0x2 : RESERVED
Reserved
0x3 : RESERVED_NOTE_IF_CO
Reserved Note: If Counter mode is selected in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000.
End of enumeration elements list.
ENCC : Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.
bits : 4 - 8 (5 bit)
SELCC : When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.
bits : 5 - 12 (8 bit)
Enumeration: ENUM
0x0 : RISING_EDGE_OF_CAP0_
Rising Edge of CAP0 clears the timer (if bit 4 is set).
0x1 : FALLING_EDGE_OF_CAP0
Falling Edge of CAP0 clears the timer (if bit 4 is set).
0x2 : RISING_EDGE_OF_CAP1_
Rising Edge of CAP1 clears the timer (if bit 4 is set).
0x3 : FALLING_EDGE_OF_CAP1
Falling Edge of CAP1 clears the timer (if bit 4 is set).
0x4 : RESERVED_
Reserved.
0x5 : RESERVED_
Reserved.
0x6 : RESERVED_
Reserved.
0x6 : RESERVED_
Reserved.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)
PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0].
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMEN0 : PWM channel 0 enable
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : CT32BN_MAT0_IS_CONTR
CT32Bn_MAT0 is controlled by EM0.
1 : PWM_MODE_IS_ENABLED_
PWM mode is enabled for CT32Bn_MAT0.
End of enumeration elements list.
PWMEN1 : PWM channel 1 enable
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : CT32BN_MAT1_IS_CONTR
CT32Bn_MAT1 is controlled by EM1.
1 : PWM_MODE_IS_ENABLED_
PWM mode is enabled for CT32Bn_MAT1.
End of enumeration elements list.
PWMEN2 : PWM channel 2 enable
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : CT32BN_MAT2_IS_CONTR
CT32Bn_MAT2 is controlled by EM2.
1 : PWM_MODE_IS_ENABLED_
PWM mode is enabled for CT32Bn_MAT2.
End of enumeration elements list.
PWMEN3 : PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : CT32BN_MAT3_IS_CONTR
CT32Bn_MAT3 is controlled by EM3.
1 : PWM_MODE_IS_ENABLED_
PWM mode is enabled for CT32Bn_MAT3.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 4 - 35 (32 bit)
Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Timer counter value.
bits : 0 - 31 (32 bit)
Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.
address_offset : 0x88 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP : Timer counter capture value.
bits : 0 - 31 (32 bit)
Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PR : Prescale value.
bits : 0 - 31 (32 bit)
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