Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected
CAN control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : Initialization
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NORMAL_OPERATION_
Normal operation.
1 : INITIALIZATION
Initialization is started. On reset, software needs to initialize the CAN controller.
End of enumeration elements list.
IE : Module interrupt enable
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLE_CAN_INTERRUP
Disable CAN interrupts. The interrupt line is always HIGH.
1 : ENABLE_CAN_INTERRUPT
Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared.
End of enumeration elements list.
SIE : Status change interrupt enable
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : DISABLE_STATUS_CHANG
Disable status change interrupts. No status change interrupt will be generated.
1 : ENABLE_STATUS_CHANGE
Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
End of enumeration elements list.
EIE : Error interrupt enable
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : DISABLE_ERROR_INTERR
Disable error interrupt. No error status interrupt will be generated.
1 : ENABLE_ERROR_INTERRU
Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt.
End of enumeration elements list.
RESERVED : reserved
bits : 4 - 8 (5 bit)
RESERVED : reserved
bits : 4 - 8 (5 bit)
DAR : Disable automatic retransmission
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : ENABLED
Automatic retransmission of disturbed messages enabled.
1 : DISABLED
Automatic retransmission disabled.
End of enumeration elements list.
CCE : Configuration change enable
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : NOACCESS
The CPU has no write access to the bit timing register.
1 : ACCESS
The CPU has write access to the CANBT register while the INIT bit is one.
End of enumeration elements list.
TEST : Test mode enable
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : NORMAL_OPERATION_
Normal operation.
1 : TEST_MODE_
Test mode.
End of enumeration elements list.
Interrupt register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTID : 0x0000 = No interrupt is pending. 0x0001 - 0x0020 = Number of message object which caused the interrupt. 0x0021 - 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 - 0xFFFF = Unused
bits : 0 - 15 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Transmission request 1
address_offset : 0x100 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXRQST_16_1 : Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done.
bits : 0 - 15 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Transmission request 2
address_offset : 0x104 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXRQST_32_17 : Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done.
bits : 0 - 15 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Message interface 1 message control
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLC_3_0 : Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 - 1000 = Data frame has 0 - 8 data bytes. 1001 - 1111 = Data frame has 8 data bytes.
bits : 0 - 3 (4 bit)
RESERVED : reserved
bits : 4 - 10 (7 bit)
RESERVED : reserved
bits : 4 - 10 (7 bit)
EOB : End of buffer
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : FIFO
Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer.
1 : SINGELAST
Single message object or last message object of a FIFO buffer.
End of enumeration elements list.
TXRQST : Transmit request
bits : 8 - 16 (9 bit)
Enumeration: ENUM
0 : NOWAIT
This message object is not waiting for transmission.
1 : WAIT
The transmission of this message object is requested and is not yet done
End of enumeration elements list.
RMTEN : Remote enable
bits : 9 - 18 (10 bit)
Enumeration: ENUM
0 : NOCHANGE
At the reception of a remote frame, TXRQST is left unchanged.
1 : SET
At the reception of a remote frame, TXRQST is set.
End of enumeration elements list.
RXIE : Receive interrupt enable
bits : 10 - 20 (11 bit)
Enumeration: ENUM
0 : NOCHANGE
INTPND will be left unchanged after successful reception of a frame.
1 : SET
INTPND will be set after successful reception of a frame.
End of enumeration elements list.
TXIE : Transmit interrupt enable
bits : 11 - 22 (12 bit)
Enumeration: ENUM
0 : NOCHANGE
The INTPND bit will be left unchanged after a successful transmission of a frame.
1 : SET
INTPND will be set after a successful transmission of a frame.
End of enumeration elements list.
UMASK : Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.
bits : 12 - 24 (13 bit)
Enumeration: ENUM
0 : IGNORE
Mask ignored.
1 : USEMASK
Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering.
End of enumeration elements list.
INTPND : Interrupt pending
bits : 13 - 26 (14 bit)
Enumeration: ENUM
0 : NOINTSOURCE
This message object is not the source of an interrupt.
1 : INTSOURCE
This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
End of enumeration elements list.
MSGLST : Message lost (only valid for message objects in the direction receive).
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : NOLOST
No message lost since this bit was reset last by the CPU.
1 : NEWMESSAGE
The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message.
End of enumeration elements list.
NEWDAT : New data
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : NONEWDATA
No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU.
1 : NEWDATA
The message handler or the CPU has written new data into the data portion of this message object.
End of enumeration elements list.
Message interface 1 data A1
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Data byte 0
bits : 0 - 7 (8 bit)
DATA1 : Data byte 1
bits : 8 - 23 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Message interface 1 data A2
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA2 : Data byte 2
bits : 0 - 7 (8 bit)
DATA3 : Data byte 3
bits : 8 - 23 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
New data 1
address_offset : 0x120 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NEWDAT_16_1 : New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object.
bits : 0 - 15 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
New data 2
address_offset : 0x124 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NEWDAT_32_17 : New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object.
bits : 0 - 15 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Message interface 1 data B1
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA4 : Data byte 4
bits : 0 - 7 (8 bit)
DATA5 : Data byte 5
bits : 8 - 23 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Message interface 1 data B2
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA6 : Data byte 6
bits : 0 - 7 (8 bit)
DATA7 : Data byte 7
bits : 8 - 23 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Test register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Reserved
bits : 0 - 1 (2 bit)
RESERVED : Reserved
bits : 0 - 1 (2 bit)
BASIC : Basic mode
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : BASIC_MODE_DISABLED_
Basic mode disabled.
1 : TXRX
IF1 registers used as TX buffer, IF2 registers used as RX buffer.
End of enumeration elements list.
SILENT : Silent mode
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NORMAL_OPERATION_
Normal operation.
1 : SILENT
The module is in silent mode.
End of enumeration elements list.
LBACK : Loop back mode
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : DISABLED
Loop back mode is disabled.
1 : ENABLED
Loop back mode is enabled.
End of enumeration elements list.
TX : Control of CAN_TXD pins
bits : 5 - 11 (7 bit)
Enumeration: ENUM
0x0 : LEVEL
Level at the CAN_TXD pin is controlled by the CAN controller. This is the value at reset.
0x1 : TXD
The sample point can be monitored at the CAN_TXD pin.
0x2 : LOW
CAN_TXD pin is driven LOW/dominant.
0x3 : HIGH
CAN_TXD pin is driven HIGH/recessive.
End of enumeration elements list.
RX : Monitors the actual value of the CAN_RXD pin.
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : RECESSIVE
The CAN bus is recessive (CAN_RXD = 1).
1 : DORMANT
The CAN bus is dominant (CAN_RXD = 0).
End of enumeration elements list.
Interrupt pending 1
address_offset : 0x140 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTPND_16_1 : Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt.
bits : 0 - 15 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Interrupt pending 2
address_offset : 0x144 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTPND_32_17 : Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt.
bits : 0 - 15 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Message valid 1
address_offset : 0x160 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MSGVAL_16_1 : Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler.
bits : 0 - 15 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Message valid 2
address_offset : 0x164 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MSGVAL_32_17 : Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler.
bits : 0 - 15 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Baud rate prescaler extension register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRPE : Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0 to 15.
bits : 0 - 3 (4 bit)
RESERVED : Reserved
bits : 4 - 35 (32 bit)
Can clock divider register
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIVVAL : Clock divider value. CAN_CLK = PCLK/(CLKDIVVAL +1) 0000: CAN_CLK = PCLK divided by 1. 0001: CAN_CLK = PCLK divided by 2. 0010: CAN_CLK = PCLK divided by 3 0010: CAN_CLK = PCLK divided by 4. ... 1111: CAN_CLK = PCLK divided by 16.
bits : 0 - 3 (4 bit)
RESERVED : reserved
bits : 4 - 35 (32 bit)
Status register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEC : Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates.
bits : 0 - 2 (3 bit)
Enumeration: ENUM
0x0 : NO_ERROR_
No error.
0x1 : STUFF_ERROR
Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
0x2 : FORM_ERROR
Form error: A fixed format part of a received frame has the wrong format.
0x3 : ACKERROR
AckError: The message this CAN core transmitted was not acknowledged.
0x4 : BIT1ERROR
Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant.
0x5 : BIT0ERROR
Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed).
0x6 : CRCERROR
CRCError: The CRC checksum was incorrect in the message received.
0x7 : UNUSED
Unused: No CAN bus event was detected (written by the CPU).
End of enumeration elements list.
TXOK : Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOTRANSMIT
Since this bit was reset by the CPU, no message has been successfully transmitted.
1 : TRANSMIT
Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node).
End of enumeration elements list.
RXOK : Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NOTRANSMIT
Since this bit was last reset by the CPU, no message has been successfully transmitted.
1 : TRANSMIT
Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering.
End of enumeration elements list.
EPASS : Error passive
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : ACTIVE
The CAN controller is in the error active state.
1 : PASSIVE
The CAN controller is in the error passive state as defined in the CAN 2.0 specification.
End of enumeration elements list.
EWARN : Warning status
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : BELOWWARNINGLIM
Both error counters are below the error warning limit of 96.
1 : WARNINGLIM
At least one of the error counters in the EML has reached the error warning limit of 96.
End of enumeration elements list.
BOFF : Busoff status
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : NOTBUSOFF
The CAN module is not in busoff.
1 : BUSOFF
The CAN controller is in busoff state.
End of enumeration elements list.
RESERVED : reserved
bits : 8 - 39 (32 bit)
Message interface command request
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MN : Message number 0x01 - 0x20 = Valid message numbers. The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 - 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]
bits : 0 - 5 (6 bit)
RESERVED : reserved
bits : 6 - 20 (15 bit)
RESERVED : reserved
bits : 6 - 20 (15 bit)
BUSY : BUSY flag
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : ZERO
Set to zero by hardware when read/write action to this Command request register has finished.
1 : ONE
Set to one by hardware when writing to this Command request register.
End of enumeration elements list.
Message interface command mask - write direction
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_B : Access data bytes 4-7
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DATA_BYTES_4_7_UNCHA
Data bytes 4-7 unchanged.
1 : TRANSFER_DATA_BYTES_
Transfer data bytes 4-7 to message object.
End of enumeration elements list.
DATA_A : Access data bytes 0-3
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DATA_BYTES_0_3_UNCHA
Data bytes 0-3 unchanged.
1 : TRANSFER_DATA_BYTES_
Transfer data bytes 0-3 to message object.
End of enumeration elements list.
TXRQST : Access transmission request bit
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NO_TRANSMISSION_REQU
No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored.
1 : REQUEST_A_TRANSMISSI
Request a transmission. Set the TXRQST bit IF1/2_MCTRL.
End of enumeration elements list.
CLRINTPND : This bit is ignored in the write direction.
bits : 3 - 6 (4 bit)
CTRL : Access control bits
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : UNCHANGED
Control bits unchanged.
1 : TRANSFER_CONTROL_BIT
Transfer control bits to message object
End of enumeration elements list.
ARB : Access arbitration bits
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : UNCHANGED
Arbitration bits unchanged.
1 : TRANSFER_IDENTIFIER
Transfer Identifier, DIR, XTD, and MSGVAL bits to message object.
End of enumeration elements list.
MASK : Access mask bits
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : UNCHANGED
Mask bits unchanged.
1 : TRANSFER_IDENTIFIER_
Transfer Identifier MASK + MDIR + MXTD to message object.
End of enumeration elements list.
WR_RD : Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ.
bits : 7 - 14 (8 bit)
RESERVED : reserved
bits : 8 - 39 (32 bit)
Message interface command mask - read direction
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : CANIF%s_CMDMSK_W
reset_Mask : 0x0
DATA_B : Access data bytes 4-7
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : UNCHANGED
Data bytes 4-7 unchanged.
1 : TRANSFER_DATA_BYTES_
Transfer data bytes 4-7 to IFx message buffer register.
End of enumeration elements list.
DATA_A : Access data bytes 0-3
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : UNCHANGED
Data bytes 0-3 unchanged.
1 : TRANSFER_DATA_BYTES_
Transfer data bytes 0-3 to IFx message buffer.
End of enumeration elements list.
NEWDAT : Access new data bit
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : UNCHANGED
NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits.
1 : CLEAR_NEWDAT_BIT_IN_
Clear NEWDAT bit in the message object.
End of enumeration elements list.
CLRINTPND : Clear interrupt pending bit.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : UNCHANGED
INTPND bit remains unchanged.
1 : CLEAR_INTPND_BIT_IN_
Clear INTPND bit in the message object.
End of enumeration elements list.
CTRL : Access control bits
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : UNCHANGED
Control bits unchanged.
1 : TRANSFER_CONTROL_BIT
Transfer control bits to IFx message buffer.
End of enumeration elements list.
ARB : Access arbitration bits
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : UNCHANGED
Arbitration bits unchanged.
1 : TRANSFER_IDENTIFIER
Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register.
End of enumeration elements list.
MASK : Access mask bits
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : UNCHANGED
Mask bits unchanged.
1 : TRANSFER_IDENTIFIER_
Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register.
End of enumeration elements list.
WR_RD : Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ.
bits : 7 - 14 (8 bit)
RESERVED : reserved
bits : 8 - 39 (32 bit)
Message interface 1 mask 1
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSK_15_0 : Identifier mask
bits : 0 - 15 (16 bit)
Enumeration: ENUM
0 : NOINHIBIT
The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering.
1 : ACCEPTANCEFILTERING
The corresponding identifier bit is used for acceptance filtering.
End of enumeration elements list.
RESERVED : reserved
bits : 16 - 47 (32 bit)
Message interface 1 mask 2
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSK_28_16 : Identifier mask
bits : 0 - 12 (13 bit)
Enumeration: ENUM
0 : NOINHIBIT
The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering.
1 : ACCEPTANCEFILTERING
The corresponding identifier bit is used for acceptance filtering.
End of enumeration elements list.
RESERVED : Reserved
bits : 13 - 26 (14 bit)
RESERVED : Reserved
bits : 13 - 26 (14 bit)
MDIR : Mask message direction
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : NOEFFECT
The message direction bit (DIR) has no effect on acceptance filtering.
1 : ACCEPTANCEFILTERING
The message direction bit (DIR) is used for acceptance filtering.
End of enumeration elements list.
MXTD : Mask extend identifier
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : NOEFFECT
The extended identifier bit (XTD) has no effect on acceptance filtering.
1 : ACCEPTANCEFILTERING
The extended identifier bit (XTD) is used for acceptance filtering.
End of enumeration elements list.
Message interface 1 arbitration 1
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_15_0 : Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)
bits : 0 - 15 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Message interface 1 arbitration 2
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_28_16 : Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)
bits : 0 - 12 (13 bit)
DIR : Message direction
bits : 13 - 26 (14 bit)
Enumeration: ENUM
0 : RECEIVE
Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
1 : TRANSMIT
Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one).
End of enumeration elements list.
XTD : Extend identifier
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : 11_BIT_STANDARD_
The 11-bit standard identifier will be used for this message object.
1 : 29_BIT_EXTENDED_
The 29-bit extended identifier will be used for this message object.
End of enumeration elements list.
MSGVAL : Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : IGNORE
The message object is ignored by the message handler.
1 : CONFIGURED
The message object is configured and should be considered by the message handler.
End of enumeration elements list.
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Message interface 1 message control
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLC_3_0 : Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 - 1000 = Data frame has 0 - 8 data bytes. 1001 - 1111 = Data frame has 8 data bytes.
bits : 0 - 3 (4 bit)
RESERVED : reserved
bits : 4 - 10 (7 bit)
RESERVED : reserved
bits : 4 - 10 (7 bit)
EOB : End of buffer
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : FIFO
Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer.
1 : SINGELAST
Single message object or last message object of a FIFO buffer.
End of enumeration elements list.
TXRQST : Transmit request
bits : 8 - 16 (9 bit)
Enumeration: ENUM
0 : NOWAIT
This message object is not waiting for transmission.
1 : WAIT
The transmission of this message object is requested and is not yet done
End of enumeration elements list.
RMTEN : Remote enable
bits : 9 - 18 (10 bit)
Enumeration: ENUM
0 : NOCHANGE
At the reception of a remote frame, TXRQST is left unchanged.
1 : SET
At the reception of a remote frame, TXRQST is set.
End of enumeration elements list.
RXIE : Receive interrupt enable
bits : 10 - 20 (11 bit)
Enumeration: ENUM
0 : NOCHANGE
INTPND will be left unchanged after successful reception of a frame.
1 : SET
INTPND will be set after successful reception of a frame.
End of enumeration elements list.
TXIE : Transmit interrupt enable
bits : 11 - 22 (12 bit)
Enumeration: ENUM
0 : NOCHANGE
The INTPND bit will be left unchanged after a successful transmission of a frame.
1 : SET
INTPND will be set after a successful transmission of a frame.
End of enumeration elements list.
UMASK : Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.
bits : 12 - 24 (13 bit)
Enumeration: ENUM
0 : IGNORE
Mask ignored.
1 : USEMASK
Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering.
End of enumeration elements list.
INTPND : Interrupt pending
bits : 13 - 26 (14 bit)
Enumeration: ENUM
0 : NOINTSOURCE
This message object is not the source of an interrupt.
1 : INTSOURCE
This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
End of enumeration elements list.
MSGLST : Message lost (only valid for message objects in the direction receive).
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : NOLOST
No message lost since this bit was reset last by the CPU.
1 : NEWMESSAGE
The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message.
End of enumeration elements list.
NEWDAT : New data
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : NONEWDATA
No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU.
1 : NEWDATA
The message handler or the CPU has written new data into the data portion of this message object.
End of enumeration elements list.
Message interface 1 data A1
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Data byte 0
bits : 0 - 7 (8 bit)
DATA1 : Data byte 1
bits : 8 - 23 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Error counter
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEC_7_0 : Transmit error counter Current value of the transmit error counter (maximum value 255)
bits : 0 - 7 (8 bit)
REC_6_0 : Receive error counter Current value of the receive error counter (maximum value 127).
bits : 8 - 22 (15 bit)
RP : Receive error passive
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : BELOWERRORPASSIVE
The receive counter is below the error passive level.
1 : ERRORPASSIVE
The receive counter has reached the error passive level as defined in the CAN2.0 specification.
End of enumeration elements list.
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Message interface 1 data A2
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA2 : Data byte 2
bits : 0 - 7 (8 bit)
DATA3 : Data byte 3
bits : 8 - 23 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Message interface 1 data B1
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA4 : Data byte 4
bits : 0 - 7 (8 bit)
DATA5 : Data byte 5
bits : 8 - 23 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Message interface 1 data B2
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA6 : Data byte 6
bits : 0 - 7 (8 bit)
DATA7 : Data byte 7
bits : 8 - 23 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Bit timing register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRP : Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63.[1]
bits : 0 - 5 (6 bit)
SJW : (Re)synchronization jump width Valid programmed values are 0 to 3.[1]
bits : 6 - 13 (8 bit)
TSEG1 : Time segment before the sample point Valid values are 1 to 15.[1]
bits : 8 - 19 (12 bit)
TSEG2 : Time segment after the sample point Valid values are 0 to 7.[1]
bits : 12 - 26 (15 bit)
RESERVED : Reserved
bits : 15 - 46 (32 bit)
Message interface command request
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MN : Message number 0x01 - 0x20 = Valid message numbers. The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 - 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]
bits : 0 - 5 (6 bit)
RESERVED : reserved
bits : 6 - 20 (15 bit)
RESERVED : reserved
bits : 6 - 20 (15 bit)
BUSY : BUSY flag
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : ZERO
Set to zero by hardware when read/write action to this Command request register has finished.
1 : ONE
Set to one by hardware when writing to this Command request register.
End of enumeration elements list.
Message interface command mask - write direction
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_B : Access data bytes 4-7
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DATA_BYTES_4_7_UNCHA
Data bytes 4-7 unchanged.
1 : TRANSFER_DATA_BYTES_
Transfer data bytes 4-7 to message object.
End of enumeration elements list.
DATA_A : Access data bytes 0-3
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DATA_BYTES_0_3_UNCHA
Data bytes 0-3 unchanged.
1 : TRANSFER_DATA_BYTES_
Transfer data bytes 0-3 to message object.
End of enumeration elements list.
TXRQST : Access transmission request bit
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NO_TRANSMISSION_REQU
No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored.
1 : REQUEST_A_TRANSMISSI
Request a transmission. Set the TXRQST bit IF1/2_MCTRL.
End of enumeration elements list.
CLRINTPND : This bit is ignored in the write direction.
bits : 3 - 6 (4 bit)
CTRL : Access control bits
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : UNCHANGED
Control bits unchanged.
1 : TRANSFER_CONTROL_BIT
Transfer control bits to message object
End of enumeration elements list.
ARB : Access arbitration bits
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : UNCHANGED
Arbitration bits unchanged.
1 : TRANSFER_IDENTIFIER
Transfer Identifier, DIR, XTD, and MSGVAL bits to message object.
End of enumeration elements list.
MASK : Access mask bits
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : UNCHANGED
Mask bits unchanged.
1 : TRANSFER_IDENTIFIER_
Transfer Identifier MASK + MDIR + MXTD to message object.
End of enumeration elements list.
WR_RD : Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ.
bits : 7 - 14 (8 bit)
RESERVED : reserved
bits : 8 - 39 (32 bit)
Message interface command mask - read direction
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : CANIF%s_CMDMSK_W
reset_Mask : 0x0
DATA_B : Access data bytes 4-7
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : UNCHANGED
Data bytes 4-7 unchanged.
1 : TRANSFER_DATA_BYTES_
Transfer data bytes 4-7 to IFx message buffer register.
End of enumeration elements list.
DATA_A : Access data bytes 0-3
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : UNCHANGED
Data bytes 0-3 unchanged.
1 : TRANSFER_DATA_BYTES_
Transfer data bytes 0-3 to IFx message buffer.
End of enumeration elements list.
NEWDAT : Access new data bit
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : UNCHANGED
NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits.
1 : CLEAR_NEWDAT_BIT_IN_
Clear NEWDAT bit in the message object.
End of enumeration elements list.
CLRINTPND : Clear interrupt pending bit.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : UNCHANGED
INTPND bit remains unchanged.
1 : CLEAR_INTPND_BIT_IN_
Clear INTPND bit in the message object.
End of enumeration elements list.
CTRL : Access control bits
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : UNCHANGED
Control bits unchanged.
1 : TRANSFER_CONTROL_BIT
Transfer control bits to IFx message buffer.
End of enumeration elements list.
ARB : Access arbitration bits
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : UNCHANGED
Arbitration bits unchanged.
1 : TRANSFER_IDENTIFIER
Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register.
End of enumeration elements list.
MASK : Access mask bits
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : UNCHANGED
Mask bits unchanged.
1 : TRANSFER_IDENTIFIER_
Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register.
End of enumeration elements list.
WR_RD : Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ.
bits : 7 - 14 (8 bit)
RESERVED : reserved
bits : 8 - 39 (32 bit)
Message interface 1 mask 1
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSK_15_0 : Identifier mask
bits : 0 - 15 (16 bit)
Enumeration: ENUM
0 : NOINHIBIT
The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering.
1 : ACCEPTANCEFILTERING
The corresponding identifier bit is used for acceptance filtering.
End of enumeration elements list.
RESERVED : reserved
bits : 16 - 47 (32 bit)
Message interface 1 mask 2
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSK_28_16 : Identifier mask
bits : 0 - 12 (13 bit)
Enumeration: ENUM
0 : NOINHIBIT
The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering.
1 : ACCEPTANCEFILTERING
The corresponding identifier bit is used for acceptance filtering.
End of enumeration elements list.
RESERVED : Reserved
bits : 13 - 26 (14 bit)
RESERVED : Reserved
bits : 13 - 26 (14 bit)
MDIR : Mask message direction
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : NOEFFECT
The message direction bit (DIR) has no effect on acceptance filtering.
1 : ACCEPTANCEFILTERING
The message direction bit (DIR) is used for acceptance filtering.
End of enumeration elements list.
MXTD : Mask extend identifier
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : NOEFFECT
The extended identifier bit (XTD) has no effect on acceptance filtering.
1 : ACCEPTANCEFILTERING
The extended identifier bit (XTD) is used for acceptance filtering.
End of enumeration elements list.
Message interface 1 arbitration 1
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_15_0 : Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)
bits : 0 - 15 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Message interface 1 arbitration 2
address_offset : 0xFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_28_16 : Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)
bits : 0 - 12 (13 bit)
DIR : Message direction
bits : 13 - 26 (14 bit)
Enumeration: ENUM
0 : RECEIVE
Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
1 : TRANSMIT
Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one).
End of enumeration elements list.
XTD : Extend identifier
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : 11_BIT_STANDARD_
The 11-bit standard identifier will be used for this message object.
1 : 29_BIT_EXTENDED_
The 29-bit extended identifier will be used for this message object.
End of enumeration elements list.
MSGVAL : Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : IGNORE
The message object is ignored by the message handler.
1 : CONFIGURED
The message object is configured and should be considered by the message handler.
End of enumeration elements list.
RESERVED : Reserved
bits : 16 - 47 (32 bit)
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