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FMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected

Registers

FLASHCFG

FMSSTART

FMSSTOP

FMSW0

FMSW1

FMSW2

FMSW3

FMSTAT

FMSTATCLR


FLASHCFG

Flash configuration register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLASHCFG FLASHCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASHTIM RESERVED

FLASHTIM : Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
bits : 0 - 1 (2 bit)

Enumeration: ENUM

0x0 : 1_SYSTEM_CLOCK_FLASH

1 system clock flash access time (for system clock frequencies of up to 20 MHz).

0x1 : 2_SYSTEM_CLOCKS_FLAS

2 system clocks flash access time (for system clock frequencies of up to 40 MHz).

0x2 : 3_SYSTEM_CLOCKS_FLAS

3 system clocks flash access time (for system clock frequencies of up to 72 MHz).

0x3 : RESERVED_

Reserved.

End of enumeration elements list.

RESERVED : Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read.
bits : 2 - 33 (32 bit)


FMSSTART

Signature start address register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMSSTART FMSSTART read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START RESERVED

START : Signature generation start address (corresponds to AHB byte address bits[20:4]).
bits : 0 - 16 (17 bit)

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 17 - 48 (32 bit)


FMSSTOP

Signature stop-address register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMSSTOP FMSSTOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOP SIG_START RESERVED

STOP : BIST stop address divided by 16 (corresponds to AHB byte address [20:4]).
bits : 0 - 16 (17 bit)

SIG_START : Start control bit for signature generation.
bits : 17 - 34 (18 bit)

Enumeration: ENUM

0 : SIGNATURE_GENERATION

Signature generation is stopped

1 : INITIATE_SIGNATURE_G

Initiate signature generation

End of enumeration elements list.

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 18 - 49 (32 bit)


FMSW0

Word 0 [31:0]
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FMSW0 FMSW0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW0_31_0

SW0_31_0 : Word 0 of 128-bit signature (bits 31 to 0).
bits : 0 - 31 (32 bit)


FMSW1

Word 1 [63:32]
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FMSW1 FMSW1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW1_63_32

SW1_63_32 : Word 1 of 128-bit signature (bits 63 to 32).
bits : 0 - 31 (32 bit)


FMSW2

Word 2 [95:64]
address_offset : 0x34 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FMSW2 FMSW2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW2_95_64

SW2_95_64 : Word 2 of 128-bit signature (bits 95 to 64).
bits : 0 - 31 (32 bit)


FMSW3

Word 3 [127:96]
address_offset : 0x38 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FMSW3 FMSW3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW3_127_96

SW3_127_96 : Word 3 of 128-bit signature (bits 127 to 96).
bits : 0 - 31 (32 bit)


FMSTAT

Signature generation status register
address_offset : 0xFE0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FMSTAT FMSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_DONE RESERVED RESERVED

SIG_DONE : When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag.
bits : 2 - 4 (3 bit)

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 3 - 34 (32 bit)

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 3 - 34 (32 bit)


FMSTATCLR

Signature generation status clear register
address_offset : 0xFE8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FMSTATCLR FMSTATCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_DONE_CLR RESERVED RESERVED

SIG_DONE_CLR : Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register.
bits : 2 - 4 (3 bit)

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 3 - 34 (32 bit)

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 3 - 34 (32 bit)



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