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address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected
Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDEN : Watchdog enable bit. This bit is Set Only. See Table 652.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : STOP
The watchdog timer is stopped.
1 : RUN
The watchdog timer is running.
End of enumeration elements list.
WDRESET : Watchdog reset enable bit. This bit is Set Only. See Table 652.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : NORESET
A watchdog timeout will not cause a chip reset.
1 : RESET
A watchdog timeout will cause a chip reset.
End of enumeration elements list.
WDTOF : Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. See Section WDTOF.
bits : 2 - 4 (3 bit)
WDINT : Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. See Section WDINT.
bits : 3 - 6 (4 bit)
WDPROTECT : Watchdog update mode. This bit is Set Only. See Section WDPROTECT.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : CHANGE
The watchdog reload value (WDTC) can be changed at any time.
1 : CHANGE_W_CNT
The watchdog reload value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. Note: this mode is intended for use only when WDRESET =1.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 5 - 12 (8 bit)
Watchdog Warning Interrupt compare value.
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WARNINT : Watchdog warning interrupt compare value.
bits : 0 - 9 (10 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 41 (32 bit)
Watchdog Window compare value.
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WINDOW : Watchdog window value.
bits : 0 - 23 (24 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 55 (32 bit)
Watchdog timer constant register. The value in this register determines the time-out value.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Count : Watchdog time-out interval.
bits : 0 - 23 (24 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 55 (32 bit)
Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.
address_offset : 0x8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
Feed : Feed value should be 0xAA followed by 0x55.
bits : 0 - 7 (8 bit)
Watchdog timer value register. This register reads out the current value of the Watchdog timer.
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Count : Counter timer value.
bits : 0 - 23 (24 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 55 (32 bit)
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