Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected
SCT configuration register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UNIFY : SCT operation
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : 16_BIT
16-bit.The SCT operates as two 16-bit counters named L and H.
1 : 32_BIT
32-bit. The SCT operates as a unified 32-bit counter.
End of enumeration elements list.
CLKMODE : SCT clock mode
bits : 1 - 3 (3 bit)
Enumeration: ENUM
0x0 : BUS_CLOCK
Bus clock. The bus clock clocks the SCT and prescalers.
0x1 : PRESCALED_BUS_CLOCK
Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode.
0x2 : SCT_INPUT
SCT Input. The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode.
: RESERVED
Reserved.
End of enumeration elements list.
CKSEL : SCT clock select
bits : 3 - 9 (7 bit)
Enumeration: ENUM
0xE : RISING_EDGES_ON_INPU
Rising edges on input 7.
0xF : FALLING_EDGES_ON_INP
Falling edges on input 7.
0xE : RISING_EDGES_ON_INPU
Rising edges on input 7.
0xF : FALLING_EDGES_ON_INP
Falling edges on input 7.
0xE : RISING_EDGES_ON_INPU
Rising edges on input 7.
0xF : FALLING_EDGES_ON_INP
Falling edges on input 7.
0xE : RISING_EDGES_ON_INPU
Rising edges on input 7.
0xF : FALLING_EDGES_ON_INP
Falling edges on input 7.
0xE : RISING_EDGES_ON_INPU
Rising edges on input 7.
0xF : FALLING_EDGES_ON_INP
Falling edges on input 7.
0xE : RISING_EDGES_ON_INPU
Rising edges on input 7.
0xF : FALLING_EDGES_ON_INP
Falling edges on input 7.
0xE : RISING_EDGES_ON_INPU
Rising edges on input 7.
0xF : FALLING_EDGES_ON_INP
Falling edges on input 7.
0xE : RISING_EDGES_ON_INPU
Rising edges on input 7.
0xF : FALLING_EDGES_ON_INP
Falling edges on input 7.
End of enumeration elements list.
NORELAOD_L : A 1 in this bit prevents the lower match and fractional match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
bits : 7 - 14 (8 bit)
NORELOAD_H : A 1 in this bit prevents the higher match and fractional match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.
bits : 8 - 16 (9 bit)
INSYNC : Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used.
bits : 9 - 25 (17 bit)
AUTOLIMIT_L : A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
bits : 17 - 34 (18 bit)
AUTOLIMIT_H : A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.
bits : 18 - 36 (19 bit)
RESERVED : Reserved
bits : 19 - 50 (32 bit)
SCT stop condition register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOPMSK_L : If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
bits : 0 - 15 (16 bit)
STOPMSK_H : If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).
bits : 16 - 47 (32 bit)
SCT match value register of match channels 0 to 15 REGMOD0 to REGMODE15 = 0
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
MATCH_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 47 (32 bit)
SCT capture register of capture channel 0 to 15 REGMOD0 to REGMODE15 = 1
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCH%s
reset_Mask : 0x0
CAP_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
CAP_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 47 (32 bit)
SCT match value register of match channels 0 to 15 REGMOD0 to REGMODE15 = 0
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
MATCH_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 47 (32 bit)
SCT capture register of capture channel 0 to 15 REGMOD0 to REGMODE15 = 1
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCH%s
reset_Mask : 0x0
CAP_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
CAP_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 47 (32 bit)
SCT match value register of match channels 0 to 15 REGMOD0 to REGMODE15 = 0
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
MATCH_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 47 (32 bit)
SCT capture register of capture channel 0 to 15 REGMOD0 to REGMODE15 = 1
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCH%s
reset_Mask : 0x0
CAP_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
CAP_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 47 (32 bit)
SCT match value register of match channels 0 to 15 REGMOD0 to REGMODE15 = 0
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
MATCH_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 47 (32 bit)
SCT capture register of capture channel 0 to 15 REGMOD0 to REGMODE15 = 1
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCH%s
reset_Mask : 0x0
CAP_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
CAP_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 47 (32 bit)
SCT match value register of match channels 0 to 15 REGMOD0 to REGMODE15 = 0
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
MATCH_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 47 (32 bit)
SCT capture register of capture channel 0 to 15 REGMOD0 to REGMODE15 = 1
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCH%s
reset_Mask : 0x0
CAP_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
CAP_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 47 (32 bit)
SCT match value register of match channels 0 to 15 REGMOD0 to REGMODE15 = 0
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
MATCH_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 47 (32 bit)
SCT capture register of capture channel 0 to 15 REGMOD0 to REGMODE15 = 1
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCH%s
reset_Mask : 0x0
CAP_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
CAP_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 47 (32 bit)
SCT match value register of match channels 0 to 15 REGMOD0 to REGMODE15 = 0
address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
MATCH_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 47 (32 bit)
SCT capture register of capture channel 0 to 15 REGMOD0 to REGMODE15 = 1
address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCH%s
reset_Mask : 0x0
CAP_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
CAP_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 47 (32 bit)
SCT match value register of match channels 0 to 15 REGMOD0 to REGMODE15 = 0
address_offset : 0x11C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
MATCH_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 47 (32 bit)
SCT capture register of capture channel 0 to 15 REGMOD0 to REGMODE15 = 1
address_offset : 0x11C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCH%s
reset_Mask : 0x0
CAP_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
CAP_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 47 (32 bit)
SCT match value register of match channels 0 to 15 REGMOD0 to REGMODE15 = 0
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
MATCH_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 47 (32 bit)
SCT capture register of capture channel 0 to 15 REGMOD0 to REGMODE15 = 1
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCH%s
reset_Mask : 0x0
CAP_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
CAP_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 47 (32 bit)
SCT match value register of match channels 0 to 15 REGMOD0 to REGMODE15 = 0
address_offset : 0x124 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
MATCH_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 47 (32 bit)
SCT capture register of capture channel 0 to 15 REGMOD0 to REGMODE15 = 1
address_offset : 0x124 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCH%s
reset_Mask : 0x0
CAP_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
CAP_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 47 (32 bit)
SCT match value register of match channels 0 to 15 REGMOD0 to REGMODE15 = 0
address_offset : 0x128 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
MATCH_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 47 (32 bit)
SCT capture register of capture channel 0 to 15 REGMOD0 to REGMODE15 = 1
address_offset : 0x128 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCH%s
reset_Mask : 0x0
CAP_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
CAP_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 47 (32 bit)
SCT match value register of match channels 0 to 15 REGMOD0 to REGMODE15 = 0
address_offset : 0x12C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
MATCH_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 47 (32 bit)
SCT capture register of capture channel 0 to 15 REGMOD0 to REGMODE15 = 1
address_offset : 0x12C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCH%s
reset_Mask : 0x0
CAP_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
CAP_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 47 (32 bit)
SCT match value register of match channels 0 to 15 REGMOD0 to REGMODE15 = 0
address_offset : 0x130 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
MATCH_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 47 (32 bit)
SCT capture register of capture channel 0 to 15 REGMOD0 to REGMODE15 = 1
address_offset : 0x130 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCH%s
reset_Mask : 0x0
CAP_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
CAP_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 47 (32 bit)
SCT match value register of match channels 0 to 15 REGMOD0 to REGMODE15 = 0
address_offset : 0x134 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
MATCH_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 47 (32 bit)
SCT capture register of capture channel 0 to 15 REGMOD0 to REGMODE15 = 1
address_offset : 0x134 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCH%s
reset_Mask : 0x0
CAP_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
CAP_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 47 (32 bit)
SCT match value register of match channels 0 to 15 REGMOD0 to REGMODE15 = 0
address_offset : 0x138 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
MATCH_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 47 (32 bit)
SCT capture register of capture channel 0 to 15 REGMOD0 to REGMODE15 = 1
address_offset : 0x138 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCH%s
reset_Mask : 0x0
CAP_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
CAP_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 47 (32 bit)
SCT match value register of match channels 0 to 15 REGMOD0 to REGMODE15 = 0
address_offset : 0x13C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
MATCH_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 47 (32 bit)
SCT capture register of capture channel 0 to 15 REGMOD0 to REGMODE15 = 1
address_offset : 0x13C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCH%s
reset_Mask : 0x0
CAP_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
CAP_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 47 (32 bit)
SCT start condition register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTMSK_L : If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
bits : 0 - 15 (16 bit)
STARTMSK_H : If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).
bits : 16 - 47 (32 bit)
Fractional match registers 0 to 5 for SCT match value registers 0 to 5.
address_offset : 0x140 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACMAT_L : When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register.
bits : 0 - 3 (4 bit)
FRACMAT_H : When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5).
bits : 16 - 35 (20 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
Fractional match registers 0 to 5 for SCT match value registers 0 to 5.
address_offset : 0x144 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACMAT_L : When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register.
bits : 0 - 3 (4 bit)
FRACMAT_H : When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5).
bits : 16 - 35 (20 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
Fractional match registers 0 to 5 for SCT match value registers 0 to 5.
address_offset : 0x148 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACMAT_L : When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register.
bits : 0 - 3 (4 bit)
FRACMAT_H : When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5).
bits : 16 - 35 (20 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
Fractional match registers 0 to 5 for SCT match value registers 0 to 5.
address_offset : 0x14C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACMAT_L : When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register.
bits : 0 - 3 (4 bit)
FRACMAT_H : When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5).
bits : 16 - 35 (20 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
Fractional match registers 0 to 5 for SCT match value registers 0 to 5.
address_offset : 0x150 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACMAT_L : When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register.
bits : 0 - 3 (4 bit)
FRACMAT_H : When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5).
bits : 16 - 35 (20 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
Fractional match registers 0 to 5 for SCT match value registers 0 to 5.
address_offset : 0x154 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACMAT_L : When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register.
bits : 0 - 3 (4 bit)
FRACMAT_H : When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5).
bits : 16 - 35 (20 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
SCT dither condition register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DITHMSK_L : If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit low counter or the unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle.
bits : 0 - 15 (16 bit)
DITHMSK_H : If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit high counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle.
bits : 16 - 47 (32 bit)
SCT match reload value register 0 to 15 REGMOD0 = 0 to REGMODE15 = 0
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_L : When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
RELOAD_H : When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 47 (32 bit)
SCT capture control register 0 to 15 REGMOD0 = 1 to REGMODE15 = 1
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCHREL%s
reset_Mask : 0x0
CAPCON_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 15 (16 bit)
CAPCON_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31).
bits : 16 - 47 (32 bit)
SCT match reload value register 0 to 15 REGMOD0 = 0 to REGMODE15 = 0
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_L : When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
RELOAD_H : When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 47 (32 bit)
SCT capture control register 0 to 15 REGMOD0 = 1 to REGMODE15 = 1
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCHREL%s
reset_Mask : 0x0
CAPCON_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 15 (16 bit)
CAPCON_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31).
bits : 16 - 47 (32 bit)
SCT match reload value register 0 to 15 REGMOD0 = 0 to REGMODE15 = 0
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_L : When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
RELOAD_H : When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 47 (32 bit)
SCT capture control register 0 to 15 REGMOD0 = 1 to REGMODE15 = 1
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCHREL%s
reset_Mask : 0x0
CAPCON_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 15 (16 bit)
CAPCON_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31).
bits : 16 - 47 (32 bit)
SCT match reload value register 0 to 15 REGMOD0 = 0 to REGMODE15 = 0
address_offset : 0x20C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_L : When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
RELOAD_H : When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 47 (32 bit)
SCT capture control register 0 to 15 REGMOD0 = 1 to REGMODE15 = 1
address_offset : 0x20C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCHREL%s
reset_Mask : 0x0
CAPCON_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 15 (16 bit)
CAPCON_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31).
bits : 16 - 47 (32 bit)
SCT match reload value register 0 to 15 REGMOD0 = 0 to REGMODE15 = 0
address_offset : 0x210 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_L : When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
RELOAD_H : When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 47 (32 bit)
SCT capture control register 0 to 15 REGMOD0 = 1 to REGMODE15 = 1
address_offset : 0x210 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCHREL%s
reset_Mask : 0x0
CAPCON_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 15 (16 bit)
CAPCON_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31).
bits : 16 - 47 (32 bit)
SCT match reload value register 0 to 15 REGMOD0 = 0 to REGMODE15 = 0
address_offset : 0x214 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_L : When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
RELOAD_H : When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 47 (32 bit)
SCT capture control register 0 to 15 REGMOD0 = 1 to REGMODE15 = 1
address_offset : 0x214 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCHREL%s
reset_Mask : 0x0
CAPCON_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 15 (16 bit)
CAPCON_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31).
bits : 16 - 47 (32 bit)
SCT match reload value register 0 to 15 REGMOD0 = 0 to REGMODE15 = 0
address_offset : 0x218 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_L : When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
RELOAD_H : When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 47 (32 bit)
SCT capture control register 0 to 15 REGMOD0 = 1 to REGMODE15 = 1
address_offset : 0x218 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCHREL%s
reset_Mask : 0x0
CAPCON_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 15 (16 bit)
CAPCON_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31).
bits : 16 - 47 (32 bit)
SCT match reload value register 0 to 15 REGMOD0 = 0 to REGMODE15 = 0
address_offset : 0x21C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_L : When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
RELOAD_H : When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 47 (32 bit)
SCT capture control register 0 to 15 REGMOD0 = 1 to REGMODE15 = 1
address_offset : 0x21C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCHREL%s
reset_Mask : 0x0
CAPCON_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 15 (16 bit)
CAPCON_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31).
bits : 16 - 47 (32 bit)
SCT match reload value register 0 to 15 REGMOD0 = 0 to REGMODE15 = 0
address_offset : 0x220 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_L : When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
RELOAD_H : When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 47 (32 bit)
SCT capture control register 0 to 15 REGMOD0 = 1 to REGMODE15 = 1
address_offset : 0x220 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCHREL%s
reset_Mask : 0x0
CAPCON_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 15 (16 bit)
CAPCON_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31).
bits : 16 - 47 (32 bit)
SCT match reload value register 0 to 15 REGMOD0 = 0 to REGMODE15 = 0
address_offset : 0x224 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_L : When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
RELOAD_H : When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 47 (32 bit)
SCT capture control register 0 to 15 REGMOD0 = 1 to REGMODE15 = 1
address_offset : 0x224 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCHREL%s
reset_Mask : 0x0
CAPCON_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 15 (16 bit)
CAPCON_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31).
bits : 16 - 47 (32 bit)
SCT match reload value register 0 to 15 REGMOD0 = 0 to REGMODE15 = 0
address_offset : 0x228 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_L : When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
RELOAD_H : When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 47 (32 bit)
SCT capture control register 0 to 15 REGMOD0 = 1 to REGMODE15 = 1
address_offset : 0x228 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCHREL%s
reset_Mask : 0x0
CAPCON_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 15 (16 bit)
CAPCON_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31).
bits : 16 - 47 (32 bit)
SCT match reload value register 0 to 15 REGMOD0 = 0 to REGMODE15 = 0
address_offset : 0x22C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_L : When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
RELOAD_H : When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 47 (32 bit)
SCT capture control register 0 to 15 REGMOD0 = 1 to REGMODE15 = 1
address_offset : 0x22C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCHREL%s
reset_Mask : 0x0
CAPCON_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 15 (16 bit)
CAPCON_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31).
bits : 16 - 47 (32 bit)
SCT match reload value register 0 to 15 REGMOD0 = 0 to REGMODE15 = 0
address_offset : 0x230 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_L : When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
RELOAD_H : When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 47 (32 bit)
SCT capture control register 0 to 15 REGMOD0 = 1 to REGMODE15 = 1
address_offset : 0x230 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCHREL%s
reset_Mask : 0x0
CAPCON_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 15 (16 bit)
CAPCON_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31).
bits : 16 - 47 (32 bit)
SCT match reload value register 0 to 15 REGMOD0 = 0 to REGMODE15 = 0
address_offset : 0x234 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_L : When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
RELOAD_H : When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 47 (32 bit)
SCT capture control register 0 to 15 REGMOD0 = 1 to REGMODE15 = 1
address_offset : 0x234 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCHREL%s
reset_Mask : 0x0
CAPCON_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 15 (16 bit)
CAPCON_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31).
bits : 16 - 47 (32 bit)
SCT match reload value register 0 to 15 REGMOD0 = 0 to REGMODE15 = 0
address_offset : 0x238 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_L : When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
RELOAD_H : When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 47 (32 bit)
SCT capture control register 0 to 15 REGMOD0 = 1 to REGMODE15 = 1
address_offset : 0x238 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCHREL%s
reset_Mask : 0x0
CAPCON_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 15 (16 bit)
CAPCON_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31).
bits : 16 - 47 (32 bit)
SCT match reload value register 0 to 15 REGMOD0 = 0 to REGMODE15 = 0
address_offset : 0x23C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD_L : When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
RELOAD_H : When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 47 (32 bit)
SCT capture control register 0 to 15 REGMOD0 = 1 to REGMODE15 = 1
address_offset : 0x23C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : MATCHREL%s
reset_Mask : 0x0
CAPCON_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 15 (16 bit)
CAPCON_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31).
bits : 16 - 47 (32 bit)
Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5.
address_offset : 0x240 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELFRAC_L : When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register.
bits : 0 - 3 (4 bit)
RELFRAC_H : When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register.
bits : 16 - 35 (20 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5.
address_offset : 0x244 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELFRAC_L : When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register.
bits : 0 - 3 (4 bit)
RELFRAC_H : When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register.
bits : 16 - 35 (20 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5.
address_offset : 0x248 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELFRAC_L : When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register.
bits : 0 - 3 (4 bit)
RELFRAC_H : When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register.
bits : 16 - 35 (20 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5.
address_offset : 0x24C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELFRAC_L : When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register.
bits : 0 - 3 (4 bit)
RELFRAC_H : When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register.
bits : 16 - 35 (20 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5.
address_offset : 0x250 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELFRAC_L : When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register.
bits : 0 - 3 (4 bit)
RELFRAC_H : When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register.
bits : 16 - 35 (20 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5.
address_offset : 0x254 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELFRAC_L : When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register.
bits : 0 - 3 (4 bit)
RELFRAC_H : When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register.
bits : 16 - 35 (20 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
SCT event state register 0
address_offset : 0x300 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSK0 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 0 - 0 (1 bit)
STATEMSK1 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 1 - 2 (2 bit)
STATEMSK2 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 2 - 4 (3 bit)
STATEMSK3 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 3 - 6 (4 bit)
STATEMSK4 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 4 - 8 (5 bit)
STATEMSK5 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 5 - 10 (6 bit)
STATEMSK6 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 6 - 12 (7 bit)
STATEMSK7 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 7 - 14 (8 bit)
STATEMSK8 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 8 - 16 (9 bit)
STATEMSK9 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 9 - 18 (10 bit)
STATEMSK10 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 10 - 20 (11 bit)
STATEMSK11 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 11 - 22 (12 bit)
STATEMSK12 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 12 - 24 (13 bit)
STATEMSK13 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 13 - 26 (14 bit)
STATEMSK14 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 14 - 28 (15 bit)
STATEMSK15 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 15 - 30 (16 bit)
STATEMSK16 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 16 - 32 (17 bit)
STATEMSK17 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 17 - 34 (18 bit)
STATEMSK18 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 18 - 36 (19 bit)
STATEMSK19 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 19 - 38 (20 bit)
STATEMSK20 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 20 - 40 (21 bit)
STATEMSK21 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 21 - 42 (22 bit)
STATEMSK22 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 22 - 44 (23 bit)
STATEMSK23 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 23 - 46 (24 bit)
STATEMSK24 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 24 - 48 (25 bit)
STATEMSK25 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 25 - 50 (26 bit)
STATEMSK26 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 26 - 52 (27 bit)
STATEMSK27 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 27 - 54 (28 bit)
STATEMSK28 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 28 - 56 (29 bit)
STATEMSK29 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 29 - 58 (30 bit)
STATEMSK30 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 30 - 60 (31 bit)
STATEMSK31 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 31 - 62 (32 bit)
SCT event control register 0
address_offset : 0x304 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : L_STATE
L state. Selects the L state and the L match register selected by MATCHSEL.
1 : H_STATE
H state. Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : INPUT
Input. Selects the input selected by IOSEL.
1 : OUTPUT
Output. Selects the output selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 15 (10 bit)
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : STATEV_VALUE_IS_ADDE
STATEV value is added into STATE (the carry-out is ignored).
1 : STATEV_VALUE_IS_LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 34 (20 bit)
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 40 (21 bit)
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 43 (23 bit)
Enumeration: ENUM
0x0 : DIRECTION_INDEPENDEN
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
RESERVED : Reserved
bits : 23 - 54 (32 bit)
SCT event state register 0
address_offset : 0x308 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSK0 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 0 - 0 (1 bit)
STATEMSK1 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 1 - 2 (2 bit)
STATEMSK2 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 2 - 4 (3 bit)
STATEMSK3 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 3 - 6 (4 bit)
STATEMSK4 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 4 - 8 (5 bit)
STATEMSK5 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 5 - 10 (6 bit)
STATEMSK6 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 6 - 12 (7 bit)
STATEMSK7 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 7 - 14 (8 bit)
STATEMSK8 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 8 - 16 (9 bit)
STATEMSK9 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 9 - 18 (10 bit)
STATEMSK10 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 10 - 20 (11 bit)
STATEMSK11 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 11 - 22 (12 bit)
STATEMSK12 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 12 - 24 (13 bit)
STATEMSK13 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 13 - 26 (14 bit)
STATEMSK14 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 14 - 28 (15 bit)
STATEMSK15 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 15 - 30 (16 bit)
STATEMSK16 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 16 - 32 (17 bit)
STATEMSK17 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 17 - 34 (18 bit)
STATEMSK18 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 18 - 36 (19 bit)
STATEMSK19 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 19 - 38 (20 bit)
STATEMSK20 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 20 - 40 (21 bit)
STATEMSK21 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 21 - 42 (22 bit)
STATEMSK22 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 22 - 44 (23 bit)
STATEMSK23 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 23 - 46 (24 bit)
STATEMSK24 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 24 - 48 (25 bit)
STATEMSK25 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 25 - 50 (26 bit)
STATEMSK26 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 26 - 52 (27 bit)
STATEMSK27 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 27 - 54 (28 bit)
STATEMSK28 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 28 - 56 (29 bit)
STATEMSK29 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 29 - 58 (30 bit)
STATEMSK30 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 30 - 60 (31 bit)
STATEMSK31 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 31 - 62 (32 bit)
SCT event control register 0
address_offset : 0x30C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : L_STATE
L state. Selects the L state and the L match register selected by MATCHSEL.
1 : H_STATE
H state. Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : INPUT
Input. Selects the input selected by IOSEL.
1 : OUTPUT
Output. Selects the output selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 15 (10 bit)
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : STATEV_VALUE_IS_ADDE
STATEV value is added into STATE (the carry-out is ignored).
1 : STATEV_VALUE_IS_LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 34 (20 bit)
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 40 (21 bit)
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 43 (23 bit)
Enumeration: ENUM
0x0 : DIRECTION_INDEPENDEN
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
RESERVED : Reserved
bits : 23 - 54 (32 bit)
SCT event state register 0
address_offset : 0x310 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSK0 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 0 - 0 (1 bit)
STATEMSK1 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 1 - 2 (2 bit)
STATEMSK2 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 2 - 4 (3 bit)
STATEMSK3 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 3 - 6 (4 bit)
STATEMSK4 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 4 - 8 (5 bit)
STATEMSK5 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 5 - 10 (6 bit)
STATEMSK6 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 6 - 12 (7 bit)
STATEMSK7 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 7 - 14 (8 bit)
STATEMSK8 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 8 - 16 (9 bit)
STATEMSK9 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 9 - 18 (10 bit)
STATEMSK10 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 10 - 20 (11 bit)
STATEMSK11 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 11 - 22 (12 bit)
STATEMSK12 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 12 - 24 (13 bit)
STATEMSK13 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 13 - 26 (14 bit)
STATEMSK14 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 14 - 28 (15 bit)
STATEMSK15 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 15 - 30 (16 bit)
STATEMSK16 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 16 - 32 (17 bit)
STATEMSK17 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 17 - 34 (18 bit)
STATEMSK18 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 18 - 36 (19 bit)
STATEMSK19 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 19 - 38 (20 bit)
STATEMSK20 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 20 - 40 (21 bit)
STATEMSK21 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 21 - 42 (22 bit)
STATEMSK22 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 22 - 44 (23 bit)
STATEMSK23 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 23 - 46 (24 bit)
STATEMSK24 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 24 - 48 (25 bit)
STATEMSK25 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 25 - 50 (26 bit)
STATEMSK26 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 26 - 52 (27 bit)
STATEMSK27 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 27 - 54 (28 bit)
STATEMSK28 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 28 - 56 (29 bit)
STATEMSK29 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 29 - 58 (30 bit)
STATEMSK30 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 30 - 60 (31 bit)
STATEMSK31 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 31 - 62 (32 bit)
SCT event control register 0
address_offset : 0x314 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : L_STATE
L state. Selects the L state and the L match register selected by MATCHSEL.
1 : H_STATE
H state. Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : INPUT
Input. Selects the input selected by IOSEL.
1 : OUTPUT
Output. Selects the output selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 15 (10 bit)
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : STATEV_VALUE_IS_ADDE
STATEV value is added into STATE (the carry-out is ignored).
1 : STATEV_VALUE_IS_LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 34 (20 bit)
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 40 (21 bit)
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 43 (23 bit)
Enumeration: ENUM
0x0 : DIRECTION_INDEPENDEN
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
RESERVED : Reserved
bits : 23 - 54 (32 bit)
SCT event state register 0
address_offset : 0x318 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSK0 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 0 - 0 (1 bit)
STATEMSK1 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 1 - 2 (2 bit)
STATEMSK2 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 2 - 4 (3 bit)
STATEMSK3 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 3 - 6 (4 bit)
STATEMSK4 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 4 - 8 (5 bit)
STATEMSK5 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 5 - 10 (6 bit)
STATEMSK6 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 6 - 12 (7 bit)
STATEMSK7 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 7 - 14 (8 bit)
STATEMSK8 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 8 - 16 (9 bit)
STATEMSK9 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 9 - 18 (10 bit)
STATEMSK10 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 10 - 20 (11 bit)
STATEMSK11 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 11 - 22 (12 bit)
STATEMSK12 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 12 - 24 (13 bit)
STATEMSK13 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 13 - 26 (14 bit)
STATEMSK14 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 14 - 28 (15 bit)
STATEMSK15 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 15 - 30 (16 bit)
STATEMSK16 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 16 - 32 (17 bit)
STATEMSK17 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 17 - 34 (18 bit)
STATEMSK18 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 18 - 36 (19 bit)
STATEMSK19 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 19 - 38 (20 bit)
STATEMSK20 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 20 - 40 (21 bit)
STATEMSK21 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 21 - 42 (22 bit)
STATEMSK22 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 22 - 44 (23 bit)
STATEMSK23 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 23 - 46 (24 bit)
STATEMSK24 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 24 - 48 (25 bit)
STATEMSK25 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 25 - 50 (26 bit)
STATEMSK26 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 26 - 52 (27 bit)
STATEMSK27 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 27 - 54 (28 bit)
STATEMSK28 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 28 - 56 (29 bit)
STATEMSK29 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 29 - 58 (30 bit)
STATEMSK30 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 30 - 60 (31 bit)
STATEMSK31 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 31 - 62 (32 bit)
SCT event control register 0
address_offset : 0x31C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : L_STATE
L state. Selects the L state and the L match register selected by MATCHSEL.
1 : H_STATE
H state. Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : INPUT
Input. Selects the input selected by IOSEL.
1 : OUTPUT
Output. Selects the output selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 15 (10 bit)
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : STATEV_VALUE_IS_ADDE
STATEV value is added into STATE (the carry-out is ignored).
1 : STATEV_VALUE_IS_LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 34 (20 bit)
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 40 (21 bit)
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 43 (23 bit)
Enumeration: ENUM
0x0 : DIRECTION_INDEPENDEN
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
RESERVED : Reserved
bits : 23 - 54 (32 bit)
SCT event state register 0
address_offset : 0x320 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSK0 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 0 - 0 (1 bit)
STATEMSK1 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 1 - 2 (2 bit)
STATEMSK2 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 2 - 4 (3 bit)
STATEMSK3 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 3 - 6 (4 bit)
STATEMSK4 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 4 - 8 (5 bit)
STATEMSK5 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 5 - 10 (6 bit)
STATEMSK6 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 6 - 12 (7 bit)
STATEMSK7 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 7 - 14 (8 bit)
STATEMSK8 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 8 - 16 (9 bit)
STATEMSK9 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 9 - 18 (10 bit)
STATEMSK10 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 10 - 20 (11 bit)
STATEMSK11 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 11 - 22 (12 bit)
STATEMSK12 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 12 - 24 (13 bit)
STATEMSK13 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 13 - 26 (14 bit)
STATEMSK14 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 14 - 28 (15 bit)
STATEMSK15 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 15 - 30 (16 bit)
STATEMSK16 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 16 - 32 (17 bit)
STATEMSK17 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 17 - 34 (18 bit)
STATEMSK18 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 18 - 36 (19 bit)
STATEMSK19 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 19 - 38 (20 bit)
STATEMSK20 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 20 - 40 (21 bit)
STATEMSK21 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 21 - 42 (22 bit)
STATEMSK22 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 22 - 44 (23 bit)
STATEMSK23 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 23 - 46 (24 bit)
STATEMSK24 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 24 - 48 (25 bit)
STATEMSK25 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 25 - 50 (26 bit)
STATEMSK26 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 26 - 52 (27 bit)
STATEMSK27 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 27 - 54 (28 bit)
STATEMSK28 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 28 - 56 (29 bit)
STATEMSK29 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 29 - 58 (30 bit)
STATEMSK30 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 30 - 60 (31 bit)
STATEMSK31 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 31 - 62 (32 bit)
SCT event control register 0
address_offset : 0x324 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : L_STATE
L state. Selects the L state and the L match register selected by MATCHSEL.
1 : H_STATE
H state. Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : INPUT
Input. Selects the input selected by IOSEL.
1 : OUTPUT
Output. Selects the output selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 15 (10 bit)
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : STATEV_VALUE_IS_ADDE
STATEV value is added into STATE (the carry-out is ignored).
1 : STATEV_VALUE_IS_LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 34 (20 bit)
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 40 (21 bit)
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 43 (23 bit)
Enumeration: ENUM
0x0 : DIRECTION_INDEPENDEN
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
RESERVED : Reserved
bits : 23 - 54 (32 bit)
SCT event state register 0
address_offset : 0x328 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSK0 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 0 - 0 (1 bit)
STATEMSK1 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 1 - 2 (2 bit)
STATEMSK2 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 2 - 4 (3 bit)
STATEMSK3 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 3 - 6 (4 bit)
STATEMSK4 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 4 - 8 (5 bit)
STATEMSK5 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 5 - 10 (6 bit)
STATEMSK6 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 6 - 12 (7 bit)
STATEMSK7 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 7 - 14 (8 bit)
STATEMSK8 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 8 - 16 (9 bit)
STATEMSK9 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 9 - 18 (10 bit)
STATEMSK10 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 10 - 20 (11 bit)
STATEMSK11 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 11 - 22 (12 bit)
STATEMSK12 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 12 - 24 (13 bit)
STATEMSK13 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 13 - 26 (14 bit)
STATEMSK14 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 14 - 28 (15 bit)
STATEMSK15 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 15 - 30 (16 bit)
STATEMSK16 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 16 - 32 (17 bit)
STATEMSK17 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 17 - 34 (18 bit)
STATEMSK18 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 18 - 36 (19 bit)
STATEMSK19 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 19 - 38 (20 bit)
STATEMSK20 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 20 - 40 (21 bit)
STATEMSK21 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 21 - 42 (22 bit)
STATEMSK22 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 22 - 44 (23 bit)
STATEMSK23 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 23 - 46 (24 bit)
STATEMSK24 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 24 - 48 (25 bit)
STATEMSK25 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 25 - 50 (26 bit)
STATEMSK26 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 26 - 52 (27 bit)
STATEMSK27 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 27 - 54 (28 bit)
STATEMSK28 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 28 - 56 (29 bit)
STATEMSK29 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 29 - 58 (30 bit)
STATEMSK30 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 30 - 60 (31 bit)
STATEMSK31 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 31 - 62 (32 bit)
SCT event control register 0
address_offset : 0x32C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : L_STATE
L state. Selects the L state and the L match register selected by MATCHSEL.
1 : H_STATE
H state. Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : INPUT
Input. Selects the input selected by IOSEL.
1 : OUTPUT
Output. Selects the output selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 15 (10 bit)
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : STATEV_VALUE_IS_ADDE
STATEV value is added into STATE (the carry-out is ignored).
1 : STATEV_VALUE_IS_LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 34 (20 bit)
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 40 (21 bit)
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 43 (23 bit)
Enumeration: ENUM
0x0 : DIRECTION_INDEPENDEN
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
RESERVED : Reserved
bits : 23 - 54 (32 bit)
SCT event state register 0
address_offset : 0x330 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSK0 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 0 - 0 (1 bit)
STATEMSK1 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 1 - 2 (2 bit)
STATEMSK2 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 2 - 4 (3 bit)
STATEMSK3 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 3 - 6 (4 bit)
STATEMSK4 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 4 - 8 (5 bit)
STATEMSK5 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 5 - 10 (6 bit)
STATEMSK6 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 6 - 12 (7 bit)
STATEMSK7 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 7 - 14 (8 bit)
STATEMSK8 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 8 - 16 (9 bit)
STATEMSK9 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 9 - 18 (10 bit)
STATEMSK10 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 10 - 20 (11 bit)
STATEMSK11 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 11 - 22 (12 bit)
STATEMSK12 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 12 - 24 (13 bit)
STATEMSK13 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 13 - 26 (14 bit)
STATEMSK14 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 14 - 28 (15 bit)
STATEMSK15 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 15 - 30 (16 bit)
STATEMSK16 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 16 - 32 (17 bit)
STATEMSK17 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 17 - 34 (18 bit)
STATEMSK18 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 18 - 36 (19 bit)
STATEMSK19 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 19 - 38 (20 bit)
STATEMSK20 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 20 - 40 (21 bit)
STATEMSK21 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 21 - 42 (22 bit)
STATEMSK22 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 22 - 44 (23 bit)
STATEMSK23 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 23 - 46 (24 bit)
STATEMSK24 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 24 - 48 (25 bit)
STATEMSK25 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 25 - 50 (26 bit)
STATEMSK26 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 26 - 52 (27 bit)
STATEMSK27 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 27 - 54 (28 bit)
STATEMSK28 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 28 - 56 (29 bit)
STATEMSK29 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 29 - 58 (30 bit)
STATEMSK30 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 30 - 60 (31 bit)
STATEMSK31 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 31 - 62 (32 bit)
SCT event control register 0
address_offset : 0x334 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : L_STATE
L state. Selects the L state and the L match register selected by MATCHSEL.
1 : H_STATE
H state. Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : INPUT
Input. Selects the input selected by IOSEL.
1 : OUTPUT
Output. Selects the output selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 15 (10 bit)
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : STATEV_VALUE_IS_ADDE
STATEV value is added into STATE (the carry-out is ignored).
1 : STATEV_VALUE_IS_LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 34 (20 bit)
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 40 (21 bit)
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 43 (23 bit)
Enumeration: ENUM
0x0 : DIRECTION_INDEPENDEN
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
RESERVED : Reserved
bits : 23 - 54 (32 bit)
SCT event state register 0
address_offset : 0x338 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSK0 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 0 - 0 (1 bit)
STATEMSK1 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 1 - 2 (2 bit)
STATEMSK2 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 2 - 4 (3 bit)
STATEMSK3 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 3 - 6 (4 bit)
STATEMSK4 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 4 - 8 (5 bit)
STATEMSK5 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 5 - 10 (6 bit)
STATEMSK6 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 6 - 12 (7 bit)
STATEMSK7 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 7 - 14 (8 bit)
STATEMSK8 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 8 - 16 (9 bit)
STATEMSK9 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 9 - 18 (10 bit)
STATEMSK10 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 10 - 20 (11 bit)
STATEMSK11 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 11 - 22 (12 bit)
STATEMSK12 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 12 - 24 (13 bit)
STATEMSK13 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 13 - 26 (14 bit)
STATEMSK14 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 14 - 28 (15 bit)
STATEMSK15 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 15 - 30 (16 bit)
STATEMSK16 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 16 - 32 (17 bit)
STATEMSK17 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 17 - 34 (18 bit)
STATEMSK18 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 18 - 36 (19 bit)
STATEMSK19 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 19 - 38 (20 bit)
STATEMSK20 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 20 - 40 (21 bit)
STATEMSK21 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 21 - 42 (22 bit)
STATEMSK22 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 22 - 44 (23 bit)
STATEMSK23 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 23 - 46 (24 bit)
STATEMSK24 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 24 - 48 (25 bit)
STATEMSK25 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 25 - 50 (26 bit)
STATEMSK26 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 26 - 52 (27 bit)
STATEMSK27 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 27 - 54 (28 bit)
STATEMSK28 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 28 - 56 (29 bit)
STATEMSK29 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 29 - 58 (30 bit)
STATEMSK30 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 30 - 60 (31 bit)
STATEMSK31 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 31 - 62 (32 bit)
SCT event control register 0
address_offset : 0x33C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : L_STATE
L state. Selects the L state and the L match register selected by MATCHSEL.
1 : H_STATE
H state. Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : INPUT
Input. Selects the input selected by IOSEL.
1 : OUTPUT
Output. Selects the output selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 15 (10 bit)
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : STATEV_VALUE_IS_ADDE
STATEV value is added into STATE (the carry-out is ignored).
1 : STATEV_VALUE_IS_LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 34 (20 bit)
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 40 (21 bit)
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 43 (23 bit)
Enumeration: ENUM
0x0 : DIRECTION_INDEPENDEN
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
RESERVED : Reserved
bits : 23 - 54 (32 bit)
SCT event state register 0
address_offset : 0x340 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSK0 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 0 - 0 (1 bit)
STATEMSK1 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 1 - 2 (2 bit)
STATEMSK2 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 2 - 4 (3 bit)
STATEMSK3 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 3 - 6 (4 bit)
STATEMSK4 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 4 - 8 (5 bit)
STATEMSK5 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 5 - 10 (6 bit)
STATEMSK6 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 6 - 12 (7 bit)
STATEMSK7 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 7 - 14 (8 bit)
STATEMSK8 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 8 - 16 (9 bit)
STATEMSK9 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 9 - 18 (10 bit)
STATEMSK10 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 10 - 20 (11 bit)
STATEMSK11 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 11 - 22 (12 bit)
STATEMSK12 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 12 - 24 (13 bit)
STATEMSK13 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 13 - 26 (14 bit)
STATEMSK14 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 14 - 28 (15 bit)
STATEMSK15 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 15 - 30 (16 bit)
STATEMSK16 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 16 - 32 (17 bit)
STATEMSK17 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 17 - 34 (18 bit)
STATEMSK18 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 18 - 36 (19 bit)
STATEMSK19 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 19 - 38 (20 bit)
STATEMSK20 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 20 - 40 (21 bit)
STATEMSK21 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 21 - 42 (22 bit)
STATEMSK22 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 22 - 44 (23 bit)
STATEMSK23 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 23 - 46 (24 bit)
STATEMSK24 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 24 - 48 (25 bit)
STATEMSK25 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 25 - 50 (26 bit)
STATEMSK26 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 26 - 52 (27 bit)
STATEMSK27 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 27 - 54 (28 bit)
STATEMSK28 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 28 - 56 (29 bit)
STATEMSK29 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 29 - 58 (30 bit)
STATEMSK30 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 30 - 60 (31 bit)
STATEMSK31 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 31 - 62 (32 bit)
SCT event control register 0
address_offset : 0x344 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : L_STATE
L state. Selects the L state and the L match register selected by MATCHSEL.
1 : H_STATE
H state. Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : INPUT
Input. Selects the input selected by IOSEL.
1 : OUTPUT
Output. Selects the output selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 15 (10 bit)
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : STATEV_VALUE_IS_ADDE
STATEV value is added into STATE (the carry-out is ignored).
1 : STATEV_VALUE_IS_LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 34 (20 bit)
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 40 (21 bit)
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 43 (23 bit)
Enumeration: ENUM
0x0 : DIRECTION_INDEPENDEN
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
RESERVED : Reserved
bits : 23 - 54 (32 bit)
SCT event state register 0
address_offset : 0x348 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSK0 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 0 - 0 (1 bit)
STATEMSK1 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 1 - 2 (2 bit)
STATEMSK2 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 2 - 4 (3 bit)
STATEMSK3 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 3 - 6 (4 bit)
STATEMSK4 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 4 - 8 (5 bit)
STATEMSK5 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 5 - 10 (6 bit)
STATEMSK6 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 6 - 12 (7 bit)
STATEMSK7 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 7 - 14 (8 bit)
STATEMSK8 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 8 - 16 (9 bit)
STATEMSK9 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 9 - 18 (10 bit)
STATEMSK10 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 10 - 20 (11 bit)
STATEMSK11 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 11 - 22 (12 bit)
STATEMSK12 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 12 - 24 (13 bit)
STATEMSK13 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 13 - 26 (14 bit)
STATEMSK14 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 14 - 28 (15 bit)
STATEMSK15 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 15 - 30 (16 bit)
STATEMSK16 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 16 - 32 (17 bit)
STATEMSK17 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 17 - 34 (18 bit)
STATEMSK18 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 18 - 36 (19 bit)
STATEMSK19 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 19 - 38 (20 bit)
STATEMSK20 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 20 - 40 (21 bit)
STATEMSK21 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 21 - 42 (22 bit)
STATEMSK22 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 22 - 44 (23 bit)
STATEMSK23 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 23 - 46 (24 bit)
STATEMSK24 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 24 - 48 (25 bit)
STATEMSK25 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 25 - 50 (26 bit)
STATEMSK26 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 26 - 52 (27 bit)
STATEMSK27 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 27 - 54 (28 bit)
STATEMSK28 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 28 - 56 (29 bit)
STATEMSK29 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 29 - 58 (30 bit)
STATEMSK30 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 30 - 60 (31 bit)
STATEMSK31 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 31 - 62 (32 bit)
SCT event control register 0
address_offset : 0x34C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : L_STATE
L state. Selects the L state and the L match register selected by MATCHSEL.
1 : H_STATE
H state. Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : INPUT
Input. Selects the input selected by IOSEL.
1 : OUTPUT
Output. Selects the output selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 15 (10 bit)
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : STATEV_VALUE_IS_ADDE
STATEV value is added into STATE (the carry-out is ignored).
1 : STATEV_VALUE_IS_LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 34 (20 bit)
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 40 (21 bit)
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 43 (23 bit)
Enumeration: ENUM
0x0 : DIRECTION_INDEPENDEN
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
RESERVED : Reserved
bits : 23 - 54 (32 bit)
SCT event state register 0
address_offset : 0x350 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSK0 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 0 - 0 (1 bit)
STATEMSK1 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 1 - 2 (2 bit)
STATEMSK2 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 2 - 4 (3 bit)
STATEMSK3 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 3 - 6 (4 bit)
STATEMSK4 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 4 - 8 (5 bit)
STATEMSK5 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 5 - 10 (6 bit)
STATEMSK6 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 6 - 12 (7 bit)
STATEMSK7 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 7 - 14 (8 bit)
STATEMSK8 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 8 - 16 (9 bit)
STATEMSK9 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 9 - 18 (10 bit)
STATEMSK10 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 10 - 20 (11 bit)
STATEMSK11 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 11 - 22 (12 bit)
STATEMSK12 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 12 - 24 (13 bit)
STATEMSK13 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 13 - 26 (14 bit)
STATEMSK14 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 14 - 28 (15 bit)
STATEMSK15 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 15 - 30 (16 bit)
STATEMSK16 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 16 - 32 (17 bit)
STATEMSK17 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 17 - 34 (18 bit)
STATEMSK18 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 18 - 36 (19 bit)
STATEMSK19 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 19 - 38 (20 bit)
STATEMSK20 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 20 - 40 (21 bit)
STATEMSK21 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 21 - 42 (22 bit)
STATEMSK22 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 22 - 44 (23 bit)
STATEMSK23 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 23 - 46 (24 bit)
STATEMSK24 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 24 - 48 (25 bit)
STATEMSK25 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 25 - 50 (26 bit)
STATEMSK26 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 26 - 52 (27 bit)
STATEMSK27 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 27 - 54 (28 bit)
STATEMSK28 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 28 - 56 (29 bit)
STATEMSK29 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 29 - 58 (30 bit)
STATEMSK30 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 30 - 60 (31 bit)
STATEMSK31 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 31 - 62 (32 bit)
SCT event control register 0
address_offset : 0x354 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : L_STATE
L state. Selects the L state and the L match register selected by MATCHSEL.
1 : H_STATE
H state. Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : INPUT
Input. Selects the input selected by IOSEL.
1 : OUTPUT
Output. Selects the output selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 15 (10 bit)
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : STATEV_VALUE_IS_ADDE
STATEV value is added into STATE (the carry-out is ignored).
1 : STATEV_VALUE_IS_LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 34 (20 bit)
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 40 (21 bit)
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 43 (23 bit)
Enumeration: ENUM
0x0 : DIRECTION_INDEPENDEN
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
RESERVED : Reserved
bits : 23 - 54 (32 bit)
SCT event state register 0
address_offset : 0x358 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSK0 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 0 - 0 (1 bit)
STATEMSK1 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 1 - 2 (2 bit)
STATEMSK2 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 2 - 4 (3 bit)
STATEMSK3 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 3 - 6 (4 bit)
STATEMSK4 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 4 - 8 (5 bit)
STATEMSK5 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 5 - 10 (6 bit)
STATEMSK6 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 6 - 12 (7 bit)
STATEMSK7 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 7 - 14 (8 bit)
STATEMSK8 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 8 - 16 (9 bit)
STATEMSK9 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 9 - 18 (10 bit)
STATEMSK10 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 10 - 20 (11 bit)
STATEMSK11 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 11 - 22 (12 bit)
STATEMSK12 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 12 - 24 (13 bit)
STATEMSK13 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 13 - 26 (14 bit)
STATEMSK14 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 14 - 28 (15 bit)
STATEMSK15 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 15 - 30 (16 bit)
STATEMSK16 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 16 - 32 (17 bit)
STATEMSK17 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 17 - 34 (18 bit)
STATEMSK18 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 18 - 36 (19 bit)
STATEMSK19 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 19 - 38 (20 bit)
STATEMSK20 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 20 - 40 (21 bit)
STATEMSK21 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 21 - 42 (22 bit)
STATEMSK22 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 22 - 44 (23 bit)
STATEMSK23 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 23 - 46 (24 bit)
STATEMSK24 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 24 - 48 (25 bit)
STATEMSK25 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 25 - 50 (26 bit)
STATEMSK26 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 26 - 52 (27 bit)
STATEMSK27 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 27 - 54 (28 bit)
STATEMSK28 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 28 - 56 (29 bit)
STATEMSK29 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 29 - 58 (30 bit)
STATEMSK30 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 30 - 60 (31 bit)
STATEMSK31 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 31 - 62 (32 bit)
SCT event control register 0
address_offset : 0x35C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : L_STATE
L state. Selects the L state and the L match register selected by MATCHSEL.
1 : H_STATE
H state. Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : INPUT
Input. Selects the input selected by IOSEL.
1 : OUTPUT
Output. Selects the output selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 15 (10 bit)
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : STATEV_VALUE_IS_ADDE
STATEV value is added into STATE (the carry-out is ignored).
1 : STATEV_VALUE_IS_LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 34 (20 bit)
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 40 (21 bit)
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 43 (23 bit)
Enumeration: ENUM
0x0 : DIRECTION_INDEPENDEN
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
RESERVED : Reserved
bits : 23 - 54 (32 bit)
SCT event state register 0
address_offset : 0x360 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSK0 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 0 - 0 (1 bit)
STATEMSK1 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 1 - 2 (2 bit)
STATEMSK2 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 2 - 4 (3 bit)
STATEMSK3 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 3 - 6 (4 bit)
STATEMSK4 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 4 - 8 (5 bit)
STATEMSK5 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 5 - 10 (6 bit)
STATEMSK6 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 6 - 12 (7 bit)
STATEMSK7 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 7 - 14 (8 bit)
STATEMSK8 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 8 - 16 (9 bit)
STATEMSK9 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 9 - 18 (10 bit)
STATEMSK10 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 10 - 20 (11 bit)
STATEMSK11 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 11 - 22 (12 bit)
STATEMSK12 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 12 - 24 (13 bit)
STATEMSK13 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 13 - 26 (14 bit)
STATEMSK14 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 14 - 28 (15 bit)
STATEMSK15 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 15 - 30 (16 bit)
STATEMSK16 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 16 - 32 (17 bit)
STATEMSK17 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 17 - 34 (18 bit)
STATEMSK18 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 18 - 36 (19 bit)
STATEMSK19 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 19 - 38 (20 bit)
STATEMSK20 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 20 - 40 (21 bit)
STATEMSK21 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 21 - 42 (22 bit)
STATEMSK22 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 22 - 44 (23 bit)
STATEMSK23 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 23 - 46 (24 bit)
STATEMSK24 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 24 - 48 (25 bit)
STATEMSK25 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 25 - 50 (26 bit)
STATEMSK26 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 26 - 52 (27 bit)
STATEMSK27 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 27 - 54 (28 bit)
STATEMSK28 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 28 - 56 (29 bit)
STATEMSK29 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 29 - 58 (30 bit)
STATEMSK30 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 30 - 60 (31 bit)
STATEMSK31 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 31 - 62 (32 bit)
SCT event control register 0
address_offset : 0x364 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : L_STATE
L state. Selects the L state and the L match register selected by MATCHSEL.
1 : H_STATE
H state. Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : INPUT
Input. Selects the input selected by IOSEL.
1 : OUTPUT
Output. Selects the output selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 15 (10 bit)
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : STATEV_VALUE_IS_ADDE
STATEV value is added into STATE (the carry-out is ignored).
1 : STATEV_VALUE_IS_LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 34 (20 bit)
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 40 (21 bit)
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 43 (23 bit)
Enumeration: ENUM
0x0 : DIRECTION_INDEPENDEN
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
RESERVED : Reserved
bits : 23 - 54 (32 bit)
SCT event state register 0
address_offset : 0x368 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSK0 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 0 - 0 (1 bit)
STATEMSK1 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 1 - 2 (2 bit)
STATEMSK2 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 2 - 4 (3 bit)
STATEMSK3 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 3 - 6 (4 bit)
STATEMSK4 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 4 - 8 (5 bit)
STATEMSK5 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 5 - 10 (6 bit)
STATEMSK6 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 6 - 12 (7 bit)
STATEMSK7 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 7 - 14 (8 bit)
STATEMSK8 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 8 - 16 (9 bit)
STATEMSK9 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 9 - 18 (10 bit)
STATEMSK10 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 10 - 20 (11 bit)
STATEMSK11 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 11 - 22 (12 bit)
STATEMSK12 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 12 - 24 (13 bit)
STATEMSK13 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 13 - 26 (14 bit)
STATEMSK14 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 14 - 28 (15 bit)
STATEMSK15 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 15 - 30 (16 bit)
STATEMSK16 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 16 - 32 (17 bit)
STATEMSK17 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 17 - 34 (18 bit)
STATEMSK18 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 18 - 36 (19 bit)
STATEMSK19 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 19 - 38 (20 bit)
STATEMSK20 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 20 - 40 (21 bit)
STATEMSK21 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 21 - 42 (22 bit)
STATEMSK22 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 22 - 44 (23 bit)
STATEMSK23 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 23 - 46 (24 bit)
STATEMSK24 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 24 - 48 (25 bit)
STATEMSK25 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 25 - 50 (26 bit)
STATEMSK26 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 26 - 52 (27 bit)
STATEMSK27 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 27 - 54 (28 bit)
STATEMSK28 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 28 - 56 (29 bit)
STATEMSK29 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 29 - 58 (30 bit)
STATEMSK30 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 30 - 60 (31 bit)
STATEMSK31 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 31 - 62 (32 bit)
SCT event control register 0
address_offset : 0x36C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : L_STATE
L state. Selects the L state and the L match register selected by MATCHSEL.
1 : H_STATE
H state. Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : INPUT
Input. Selects the input selected by IOSEL.
1 : OUTPUT
Output. Selects the output selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 15 (10 bit)
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : STATEV_VALUE_IS_ADDE
STATEV value is added into STATE (the carry-out is ignored).
1 : STATEV_VALUE_IS_LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 34 (20 bit)
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 40 (21 bit)
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 43 (23 bit)
Enumeration: ENUM
0x0 : DIRECTION_INDEPENDEN
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
RESERVED : Reserved
bits : 23 - 54 (32 bit)
SCT event state register 0
address_offset : 0x370 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSK0 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 0 - 0 (1 bit)
STATEMSK1 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 1 - 2 (2 bit)
STATEMSK2 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 2 - 4 (3 bit)
STATEMSK3 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 3 - 6 (4 bit)
STATEMSK4 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 4 - 8 (5 bit)
STATEMSK5 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 5 - 10 (6 bit)
STATEMSK6 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 6 - 12 (7 bit)
STATEMSK7 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 7 - 14 (8 bit)
STATEMSK8 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 8 - 16 (9 bit)
STATEMSK9 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 9 - 18 (10 bit)
STATEMSK10 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 10 - 20 (11 bit)
STATEMSK11 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 11 - 22 (12 bit)
STATEMSK12 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 12 - 24 (13 bit)
STATEMSK13 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 13 - 26 (14 bit)
STATEMSK14 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 14 - 28 (15 bit)
STATEMSK15 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 15 - 30 (16 bit)
STATEMSK16 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 16 - 32 (17 bit)
STATEMSK17 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 17 - 34 (18 bit)
STATEMSK18 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 18 - 36 (19 bit)
STATEMSK19 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 19 - 38 (20 bit)
STATEMSK20 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 20 - 40 (21 bit)
STATEMSK21 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 21 - 42 (22 bit)
STATEMSK22 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 22 - 44 (23 bit)
STATEMSK23 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 23 - 46 (24 bit)
STATEMSK24 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 24 - 48 (25 bit)
STATEMSK25 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 25 - 50 (26 bit)
STATEMSK26 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 26 - 52 (27 bit)
STATEMSK27 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 27 - 54 (28 bit)
STATEMSK28 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 28 - 56 (29 bit)
STATEMSK29 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 29 - 58 (30 bit)
STATEMSK30 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 30 - 60 (31 bit)
STATEMSK31 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 31 - 62 (32 bit)
SCT event control register 0
address_offset : 0x374 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : L_STATE
L state. Selects the L state and the L match register selected by MATCHSEL.
1 : H_STATE
H state. Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : INPUT
Input. Selects the input selected by IOSEL.
1 : OUTPUT
Output. Selects the output selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 15 (10 bit)
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : STATEV_VALUE_IS_ADDE
STATEV value is added into STATE (the carry-out is ignored).
1 : STATEV_VALUE_IS_LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 34 (20 bit)
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 40 (21 bit)
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 43 (23 bit)
Enumeration: ENUM
0x0 : DIRECTION_INDEPENDEN
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
RESERVED : Reserved
bits : 23 - 54 (32 bit)
SCT event state register 0
address_offset : 0x378 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSK0 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 0 - 0 (1 bit)
STATEMSK1 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 1 - 2 (2 bit)
STATEMSK2 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 2 - 4 (3 bit)
STATEMSK3 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 3 - 6 (4 bit)
STATEMSK4 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 4 - 8 (5 bit)
STATEMSK5 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 5 - 10 (6 bit)
STATEMSK6 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 6 - 12 (7 bit)
STATEMSK7 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 7 - 14 (8 bit)
STATEMSK8 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 8 - 16 (9 bit)
STATEMSK9 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 9 - 18 (10 bit)
STATEMSK10 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 10 - 20 (11 bit)
STATEMSK11 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 11 - 22 (12 bit)
STATEMSK12 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 12 - 24 (13 bit)
STATEMSK13 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 13 - 26 (14 bit)
STATEMSK14 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 14 - 28 (15 bit)
STATEMSK15 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 15 - 30 (16 bit)
STATEMSK16 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 16 - 32 (17 bit)
STATEMSK17 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 17 - 34 (18 bit)
STATEMSK18 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 18 - 36 (19 bit)
STATEMSK19 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 19 - 38 (20 bit)
STATEMSK20 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 20 - 40 (21 bit)
STATEMSK21 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 21 - 42 (22 bit)
STATEMSK22 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 22 - 44 (23 bit)
STATEMSK23 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 23 - 46 (24 bit)
STATEMSK24 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 24 - 48 (25 bit)
STATEMSK25 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 25 - 50 (26 bit)
STATEMSK26 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 26 - 52 (27 bit)
STATEMSK27 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 27 - 54 (28 bit)
STATEMSK28 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 28 - 56 (29 bit)
STATEMSK29 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 29 - 58 (30 bit)
STATEMSK30 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 30 - 60 (31 bit)
STATEMSK31 : If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).
bits : 31 - 62 (32 bit)
SCT event control register 0
address_offset : 0x37C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : L_STATE
L state. Selects the L state and the L match register selected by MATCHSEL.
1 : H_STATE
H state. Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : INPUT
Input. Selects the input selected by IOSEL.
1 : OUTPUT
Output. Selects the output selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 15 (10 bit)
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : STATEV_VALUE_IS_ADDE
STATEV value is added into STATE (the carry-out is ignored).
1 : STATEV_VALUE_IS_LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 34 (20 bit)
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 40 (21 bit)
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 43 (23 bit)
Enumeration: ENUM
0x0 : DIRECTION_INDEPENDEN
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
RESERVED : Reserved
bits : 23 - 54 (32 bit)
SCT control register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOWN_L : This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs.
bits : 0 - 0 (1 bit)
STOP_L : When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.
bits : 1 - 2 (2 bit)
HALT_L : When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation.
bits : 2 - 4 (3 bit)
CLRCTR_L : Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
bits : 3 - 6 (4 bit)
BIDIR_L : L or unified counter direction select
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : UP
Up. The counter counts up to its limit condition, then is cleared to zero.
1 : UPDOWN
Up-down. The counter counts up to its limit, then counts down to a limit condition or to 0.
End of enumeration elements list.
PRE_L : Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
bits : 5 - 17 (13 bit)
DOWN_H : This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs.
bits : 16 - 32 (17 bit)
STOP_H : When this bit is 1 and HALT is 0, the H counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.
bits : 17 - 34 (18 bit)
HALT_H : When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation.
bits : 18 - 36 (19 bit)
CLRCTR_H : Writing a 1 to this bit clears the H counter. This bit always reads as 0.
bits : 19 - 38 (20 bit)
BIDIR_H : Direction select
bits : 20 - 40 (21 bit)
Enumeration: ENUM
0 : UP
Up. The H counter counts up to its limit condition, then is cleared to zero.
1 : UPDOWN
Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0.
End of enumeration elements list.
PRE_H : Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
bits : 21 - 49 (29 bit)
RESERVED : Reserved
bits : 29 - 60 (32 bit)
RESERVED : Reserved
bits : 29 - 60 (32 bit)
SCT counter register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTR_L : When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter.
bits : 0 - 15 (16 bit)
CTR_H : When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter.
bits : 16 - 47 (32 bit)
SCT state register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATE_L : State variable.
bits : 0 - 4 (5 bit)
STATE_H : State variable.
bits : 16 - 36 (21 bit)
RESERVED : Reserved.
bits : 21 - 52 (32 bit)
RESERVED : Reserved.
bits : 21 - 52 (32 bit)
SCT input register
address_offset : 0x48 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AIN0 : Real-time status of input 0.
bits : 0 - 0 (1 bit)
AIN1 : Real-time status of input 1.
bits : 1 - 2 (2 bit)
AIN2 : Real-time status of input 2.
bits : 2 - 4 (3 bit)
AIN3 : Real-time status of input 3.
bits : 3 - 6 (4 bit)
AIN4 : Real-time status of input 4.
bits : 4 - 8 (5 bit)
AIN5 : Real-time status of input 5.
bits : 5 - 10 (6 bit)
AIN6 : Real-time status of input 6.
bits : 6 - 12 (7 bit)
AIN7 : Real-time status of input 7.
bits : 7 - 14 (8 bit)
SIN0 : Input 0 state synchronized to the SCT clock.
bits : 16 - 32 (17 bit)
SIN1 : Input 1 state synchronized to the SCT clock.
bits : 17 - 34 (18 bit)
SIN2 : Input 2 state synchronized to the SCT clock.
bits : 18 - 36 (19 bit)
SIN3 : Input 3 state synchronized to the SCT clock.
bits : 19 - 38 (20 bit)
SIN4 : Input 4 state synchronized to the SCT clock.
bits : 20 - 40 (21 bit)
SIN5 : Input 5 state synchronized to the SCT clock.
bits : 21 - 42 (22 bit)
SIN6 : Input 6 state synchronized to the SCT clock.
bits : 22 - 44 (23 bit)
SIN7 : Input 7 state synchronized to the SCT clock.
bits : 23 - 46 (24 bit)
RESERVED : Reserved
bits : 24 - 55 (32 bit)
RESERVED : Reserved
bits : 24 - 55 (32 bit)
SCT match/capture registers mode register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGMOD_L : Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15). 0 = registers operate as match registers. 1 = registers operate as capture registers.
bits : 0 - 15 (16 bit)
REGMOD_H : Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers.
bits : 16 - 47 (32 bit)
SCT output register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT : Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 0 - 15 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 set register
address_offset : 0x500 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
SET1 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
SET2 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
SET3 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
SET4 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
SET5 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
SET6 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
SET7 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
SET8 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
SET9 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
SET10 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
SET11 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
SET12 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
SET13 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
SET14 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
SET15 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 clear register
address_offset : 0x504 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR0 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
CLR1 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
CLR2 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
CLR3 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
CLR4 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
CLR5 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
CLR6 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
CLR7 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
CLR8 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
CLR9 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
CLR10 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
CLR11 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
CLR12 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
CLR13 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
CLR14 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
CLR15 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 set register
address_offset : 0x508 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
SET1 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
SET2 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
SET3 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
SET4 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
SET5 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
SET6 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
SET7 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
SET8 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
SET9 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
SET10 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
SET11 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
SET12 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
SET13 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
SET14 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
SET15 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 clear register
address_offset : 0x50C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR0 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
CLR1 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
CLR2 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
CLR3 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
CLR4 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
CLR5 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
CLR6 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
CLR7 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
CLR8 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
CLR9 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
CLR10 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
CLR11 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
CLR12 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
CLR13 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
CLR14 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
CLR15 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 set register
address_offset : 0x510 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
SET1 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
SET2 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
SET3 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
SET4 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
SET5 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
SET6 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
SET7 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
SET8 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
SET9 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
SET10 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
SET11 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
SET12 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
SET13 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
SET14 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
SET15 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 clear register
address_offset : 0x514 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR0 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
CLR1 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
CLR2 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
CLR3 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
CLR4 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
CLR5 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
CLR6 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
CLR7 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
CLR8 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
CLR9 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
CLR10 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
CLR11 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
CLR12 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
CLR13 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
CLR14 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
CLR15 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 set register
address_offset : 0x518 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
SET1 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
SET2 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
SET3 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
SET4 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
SET5 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
SET6 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
SET7 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
SET8 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
SET9 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
SET10 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
SET11 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
SET12 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
SET13 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
SET14 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
SET15 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 clear register
address_offset : 0x51C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR0 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
CLR1 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
CLR2 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
CLR3 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
CLR4 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
CLR5 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
CLR6 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
CLR7 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
CLR8 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
CLR9 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
CLR10 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
CLR11 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
CLR12 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
CLR13 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
CLR14 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
CLR15 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 set register
address_offset : 0x520 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
SET1 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
SET2 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
SET3 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
SET4 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
SET5 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
SET6 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
SET7 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
SET8 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
SET9 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
SET10 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
SET11 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
SET12 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
SET13 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
SET14 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
SET15 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 clear register
address_offset : 0x524 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR0 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
CLR1 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
CLR2 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
CLR3 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
CLR4 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
CLR5 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
CLR6 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
CLR7 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
CLR8 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
CLR9 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
CLR10 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
CLR11 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
CLR12 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
CLR13 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
CLR14 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
CLR15 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 set register
address_offset : 0x528 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
SET1 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
SET2 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
SET3 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
SET4 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
SET5 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
SET6 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
SET7 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
SET8 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
SET9 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
SET10 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
SET11 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
SET12 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
SET13 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
SET14 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
SET15 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 clear register
address_offset : 0x52C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR0 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
CLR1 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
CLR2 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
CLR3 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
CLR4 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
CLR5 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
CLR6 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
CLR7 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
CLR8 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
CLR9 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
CLR10 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
CLR11 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
CLR12 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
CLR13 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
CLR14 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
CLR15 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 set register
address_offset : 0x530 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
SET1 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
SET2 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
SET3 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
SET4 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
SET5 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
SET6 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
SET7 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
SET8 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
SET9 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
SET10 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
SET11 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
SET12 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
SET13 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
SET14 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
SET15 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 clear register
address_offset : 0x534 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR0 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
CLR1 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
CLR2 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
CLR3 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
CLR4 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
CLR5 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
CLR6 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
CLR7 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
CLR8 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
CLR9 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
CLR10 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
CLR11 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
CLR12 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
CLR13 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
CLR14 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
CLR15 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 set register
address_offset : 0x538 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
SET1 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
SET2 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
SET3 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
SET4 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
SET5 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
SET6 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
SET7 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
SET8 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
SET9 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
SET10 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
SET11 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
SET12 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
SET13 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
SET14 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
SET15 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 clear register
address_offset : 0x53C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR0 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
CLR1 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
CLR2 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
CLR3 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
CLR4 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
CLR5 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
CLR6 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
CLR7 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
CLR8 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
CLR9 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
CLR10 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
CLR11 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
CLR12 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
CLR13 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
CLR14 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
CLR15 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output counter direction control register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETCLR0 : Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
bits : 0 - 1 (2 bit)
Enumeration: ENUM
0x0 : INDEPENDENT
Independent. Set and clear do not depend on any counter.
0x1 : L_COUNTER
L counter. Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_COUNTER
H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR1 : Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.
bits : 2 - 5 (4 bit)
Enumeration: ENUM
0x0 : INDEPENDENT
Independent. Set and clear do not depend on any counter.
0x1 : L_COUNTER
L counter. Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_COUNTER
H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR2 : Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.
bits : 4 - 9 (6 bit)
Enumeration: ENUM
0x0 : INDEPENDENT
Independent. Set and clear do not depend on any counter.
0x1 : L_COUNTER
L counter. Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_COUNTER
H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR3 : Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.
bits : 6 - 13 (8 bit)
Enumeration: ENUM
0x0 : INDEPENDENT
Independent. Set and clear do not depend on any counter.
0x1 : L_COUNTER
L counter. Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_COUNTER
H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR4 : Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : INDEPENDENT
Independent. Set and clear do not depend on any counter.
0x1 : L_COUNTER
L counter. Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_COUNTER
H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR5 : Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : INDEPENDENT
Independent. Set and clear do not depend on any counter.
0x1 : L_COUNTER
L counter. Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_COUNTER
H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR6 : Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : INDEPENDENT
Independent. Set and clear do not depend on any counter.
0x1 : L_COUNTER
L counter. Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_COUNTER
H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR7 : Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : INDEPENDENT
Independent. Set and clear do not depend on any counter.
0x1 : L_COUNTER
L counter. Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_COUNTER
H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR8 : Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.
bits : 16 - 33 (18 bit)
Enumeration: ENUM
0x0 : INDEPENDENT
Independent. Set and clear do not depend on any counter.
0x1 : L_COUNTER
L counter. Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_COUNTER
H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR9 : Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.
bits : 18 - 37 (20 bit)
Enumeration: ENUM
0x0 : INDEPENDENT
Independent. Set and clear do not depend on any counter.
0x1 : L_COUNTER
L counter. Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_COUNTER
H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR10 : Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.
bits : 20 - 41 (22 bit)
Enumeration: ENUM
0x0 : INDEPENDENT
Independent. Set and clear do not depend on any counter.
0x1 : L_COUNTER
L counter. Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_COUNTER
H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR11 : Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.
bits : 22 - 45 (24 bit)
Enumeration: ENUM
0x0 : INDEPENDENT
Independent. Set and clear do not depend on any counter.
0x1 : L_COUNTER
L counter. Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_COUNTER
H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR12 : Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.
bits : 24 - 49 (26 bit)
Enumeration: ENUM
0x0 : INDEPENDENT
Independent. Set and clear do not depend on any counter.
0x1 : L_COUNTER
L counter. Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_COUNTER
H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR13 : Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.
bits : 26 - 53 (28 bit)
Enumeration: ENUM
0x0 : INDEPENDENT
Independent. Set and clear do not depend on any counter.
0x1 : L_COUNTER
L counter. Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_COUNTER
H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR14 : Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.
bits : 28 - 57 (30 bit)
Enumeration: ENUM
0x0 : INDEPENDENT
Independent. Set and clear do not depend on any counter.
0x1 : L_COUNTER
L counter. Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_COUNTER
H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR15 : Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.
bits : 30 - 61 (32 bit)
Enumeration: ENUM
0x0 : INDEPENDENT
Independent. Set and clear do not depend on any counter.
0x1 : L_COUNTER
L counter. Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_COUNTER
H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SCT output 0 set register
address_offset : 0x540 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
SET1 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
SET2 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
SET3 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
SET4 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
SET5 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
SET6 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
SET7 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
SET8 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
SET9 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
SET10 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
SET11 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
SET12 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
SET13 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
SET14 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
SET15 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 clear register
address_offset : 0x544 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR0 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
CLR1 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
CLR2 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
CLR3 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
CLR4 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
CLR5 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
CLR6 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
CLR7 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
CLR8 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
CLR9 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
CLR10 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
CLR11 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
CLR12 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
CLR13 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
CLR14 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
CLR15 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 set register
address_offset : 0x548 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
SET1 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
SET2 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
SET3 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
SET4 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
SET5 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
SET6 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
SET7 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
SET8 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
SET9 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
SET10 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
SET11 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
SET12 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
SET13 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
SET14 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
SET15 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 clear register
address_offset : 0x54C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR0 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
CLR1 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
CLR2 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
CLR3 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
CLR4 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
CLR5 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
CLR6 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
CLR7 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
CLR8 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
CLR9 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
CLR10 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
CLR11 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
CLR12 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
CLR13 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
CLR14 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
CLR15 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 set register
address_offset : 0x550 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
SET1 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
SET2 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
SET3 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
SET4 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
SET5 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
SET6 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
SET7 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
SET8 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
SET9 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
SET10 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
SET11 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
SET12 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
SET13 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
SET14 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
SET15 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 clear register
address_offset : 0x554 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR0 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
CLR1 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
CLR2 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
CLR3 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
CLR4 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
CLR5 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
CLR6 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
CLR7 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
CLR8 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
CLR9 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
CLR10 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
CLR11 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
CLR12 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
CLR13 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
CLR14 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
CLR15 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 set register
address_offset : 0x558 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
SET1 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
SET2 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
SET3 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
SET4 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
SET5 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
SET6 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
SET7 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
SET8 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
SET9 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
SET10 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
SET11 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
SET12 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
SET13 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
SET14 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
SET15 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 clear register
address_offset : 0x55C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR0 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
CLR1 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
CLR2 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
CLR3 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
CLR4 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
CLR5 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
CLR6 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
CLR7 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
CLR8 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
CLR9 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
CLR10 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
CLR11 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
CLR12 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
CLR13 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
CLR14 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
CLR15 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 set register
address_offset : 0x560 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
SET1 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
SET2 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
SET3 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
SET4 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
SET5 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
SET6 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
SET7 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
SET8 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
SET9 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
SET10 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
SET11 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
SET12 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
SET13 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
SET14 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
SET15 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 clear register
address_offset : 0x564 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR0 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
CLR1 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
CLR2 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
CLR3 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
CLR4 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
CLR5 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
CLR6 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
CLR7 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
CLR8 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
CLR9 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
CLR10 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
CLR11 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
CLR12 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
CLR13 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
CLR14 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
CLR15 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 set register
address_offset : 0x568 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
SET1 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
SET2 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
SET3 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
SET4 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
SET5 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
SET6 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
SET7 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
SET8 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
SET9 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
SET10 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
SET11 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
SET12 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
SET13 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
SET14 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
SET15 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 clear register
address_offset : 0x56C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR0 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
CLR1 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
CLR2 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
CLR3 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
CLR4 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
CLR5 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
CLR6 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
CLR7 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
CLR8 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
CLR9 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
CLR10 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
CLR11 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
CLR12 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
CLR13 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
CLR14 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
CLR15 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 set register
address_offset : 0x570 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
SET1 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
SET2 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
SET3 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
SET4 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
SET5 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
SET6 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
SET7 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
SET8 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
SET9 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
SET10 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
SET11 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
SET12 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
SET13 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
SET14 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
SET15 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 clear register
address_offset : 0x574 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR0 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
CLR1 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
CLR2 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
CLR3 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
CLR4 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
CLR5 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
CLR6 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
CLR7 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
CLR8 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
CLR9 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
CLR10 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
CLR11 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
CLR12 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
CLR13 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
CLR14 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
CLR15 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 set register
address_offset : 0x578 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
SET1 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
SET2 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
SET3 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
SET4 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
SET5 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
SET6 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
SET7 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
SET8 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
SET9 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
SET10 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
SET11 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
SET12 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
SET13 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
SET14 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
SET15 : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT output 0 clear register
address_offset : 0x57C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR0 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 0 - 0 (1 bit)
CLR1 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 1 - 2 (2 bit)
CLR2 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 2 - 4 (3 bit)
CLR3 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 3 - 6 (4 bit)
CLR4 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 4 - 8 (5 bit)
CLR5 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 5 - 10 (6 bit)
CLR6 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 6 - 12 (7 bit)
CLR7 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 7 - 14 (8 bit)
CLR8 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 8 - 16 (9 bit)
CLR9 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 9 - 18 (10 bit)
CLR10 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 10 - 20 (11 bit)
CLR11 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 11 - 22 (12 bit)
CLR12 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 12 - 24 (13 bit)
CLR13 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 13 - 26 (14 bit)
CLR14 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 14 - 28 (15 bit)
CLR15 : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT conflict resolution register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
O0RES : Effect of simultaneous set and clear on output 0.
bits : 0 - 1 (2 bit)
Enumeration: ENUM
0x0 : NO_CHANGE
No change.
0x1 : SET_OUTPUT_OR_CLEAR
Set output (or clear based on the SETCLR0 field).
0x2 : CLEAR_OUTPUT_OR_SET
Clear output (or set based on the SETCLR0 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O1RES : Effect of simultaneous set and clear on output 1.
bits : 2 - 5 (4 bit)
Enumeration: ENUM
0x0 : NO_CHANGE
No change.
0x1 : SET_OUTPUT_OR_CLEAR
Set output (or clear based on the SETCLR1 field).
0x2 : CLEAR_OUTPUT_OR_SET
Clear output (or set based on the SETCLR1 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O2RES : Effect of simultaneous set and clear on output 2.
bits : 4 - 9 (6 bit)
Enumeration: ENUM
0x0 : NO_CHANGE
No change.
0x1 : SET_OUTPUT_OR_CLEAR
Set output (or clear based on the SETCLR2 field).
0x2 : CLEAR_OUTPUT_N_OR_S
Clear output n (or set based on the SETCLR2 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O3RES : Effect of simultaneous set and clear on output 3.
bits : 6 - 13 (8 bit)
Enumeration: ENUM
0x0 : NO_CHANGE
No change.
0x1 : SET_OUTPUT_OR_CLEAR
Set output (or clear based on the SETCLR3 field).
0x2 : CLEAR_OUTPUT_OR_SET
Clear output (or set based on the SETCLR3 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O4RES : Effect of simultaneous set and clear on output 4.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : NO_CHANGE
No change.
0x1 : SET_OUTPUT_OR_CLEAR
Set output (or clear based on the SETCLR4 field).
0x2 : CLEAR_OUTPUT_OR_SET
Clear output (or set based on the SETCLR4 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O5RES : Effect of simultaneous set and clear on output 5.
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : NO_CHANGE
No change.
0x1 : SET_OUTPUT_OR_CLEAR
Set output (or clear based on the SETCLR5 field).
0x2 : CLEAR_OUTPUT_OR_SET
Clear output (or set based on the SETCLR5 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O6RES : Effect of simultaneous set and clear on output 6.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_CHANGE
No change.
0x1 : SET_OUTPUT_OR_CLEAR
Set output (or clear based on the SETCLR6 field).
0x2 : CLEAR_OUTPUT_OR_SET
Clear output (or set based on the SETCLR6 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O7RES : Effect of simultaneous set and clear on output 7.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_CHANGE
No change.
0x1 : SET_OUTPUT_OR_CLEAR
Set output (or clear based on the SETCLR7 field).
0x2 : CLEAR_OUTPUT_OR_SET
Clear output (or set based on the SETCLR7 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O8RES : Effect of simultaneous set and clear on output 8.
bits : 16 - 33 (18 bit)
Enumeration: ENUM
0x0 : NO_CHANGE
No change.
0x1 : SET_OUTPUT_OR_CLEAR
Set output (or clear based on the SETCLR8 field).
0x2 : CLEAR_OUTPUT_OR_SET
Clear output (or set based on the SETCLR8 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O9RES : Effect of simultaneous set and clear on output 9.
bits : 18 - 37 (20 bit)
Enumeration: ENUM
0x0 : NO_CHANGE
No change.
0x1 : SET_OUTPUT_OR_CLEAR
Set output (or clear based on the SETCLR9 field).
0x2 : CLEAR_OUTPUT_OR_SET
Clear output (or set based on the SETCLR9 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O10RES : Effect of simultaneous set and clear on output 10.
bits : 20 - 41 (22 bit)
Enumeration: ENUM
0x0 : NO_CHANGE
No change.
0x1 : SET_OUTPUT_OR_CLEAR
Set output (or clear based on the SETCLR10 field).
0x2 : CLEAR_OUTPUT_OR_SET
Clear output (or set based on the SETCLR10 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O11RES : Effect of simultaneous set and clear on output 11.
bits : 22 - 45 (24 bit)
Enumeration: ENUM
0x0 : NO_CHANGE
No change.
0x1 : SET_OUTPUT_OR_CLEAR
Set output (or clear based on the SETCLR11 field).
0x2 : CLEAR_OUTPUT_OR_SET
Clear output (or set based on the SETCLR11 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O12RES : Effect of simultaneous set and clear on output 12.
bits : 24 - 49 (26 bit)
Enumeration: ENUM
0x0 : NO_CHANGE
No change.
0x1 : SET_OUTPUT_OR_CLEAR
Set output (or clear based on the SETCLR12 field).
0x2 : CLEAR_OUTPUT_OR_SET
Clear output (or set based on the SETCLR12 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O13RES : Effect of simultaneous set and clear on output 13.
bits : 26 - 53 (28 bit)
Enumeration: ENUM
0x0 : NO_CHANGE
No change.
0x1 : SET_OUTPUT_OR_CLEAR
Set output (or clear based on the SETCLR13 field).
0x2 : CLEAR_OUTPUT_OR_SET
Clear output (or set based on the SETCLR13 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O14RES : Effect of simultaneous set and clear on output 14.
bits : 28 - 57 (30 bit)
Enumeration: ENUM
0x0 : NO_CHANGE
No change.
0x1 : SET_OUTPUT_OR_CLEAR
Set output (or clear based on the SETCLR14 field).
0x2 : CLEAR_OUTPUT_OR_SET
Clear output (or set based on the SETCLR14 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O15RES : Effect of simultaneous set and clear on output 15.
bits : 30 - 61 (32 bit)
Enumeration: ENUM
0x0 : NO_CHANGE
No change.
0x1 : SET_OUTPUT_OR_CLEAR
Set output (or clear based on the SETCLR15 field).
0x2 : CLEAR_OUTPUT_OR_SET
Clear output (or set based on the SETCLR15 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
SCT DMA request 0 register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEV_00 : If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 0 (1 bit)
DEV_01 : If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 1 - 2 (2 bit)
DEV_02 : If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 2 - 4 (3 bit)
DEV_03 : If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 3 - 6 (4 bit)
DEV_04 : If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 4 - 8 (5 bit)
DEV_05 : If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 5 - 10 (6 bit)
DEV_06 : If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 6 - 12 (7 bit)
DEV_07 : If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 7 - 14 (8 bit)
DEV_08 : If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 8 - 16 (9 bit)
DEV_09 : If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 9 - 18 (10 bit)
DEV_010 : If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 10 - 20 (11 bit)
DEV_011 : If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 11 - 22 (12 bit)
DEV_012 : If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 12 - 24 (13 bit)
DEV_013 : If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 13 - 26 (14 bit)
DEV_014 : If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 14 - 28 (15 bit)
DEV_015 : If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 45 (30 bit)
DRL0 : A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers.
bits : 30 - 60 (31 bit)
DRQ0 : This read-only bit indicates the state of DMA Request 0
bits : 31 - 62 (32 bit)
SCT DMA request 1 register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEV_10 : If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 0 (1 bit)
DEV_11 : If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 1 - 2 (2 bit)
DEV_12 : If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 2 - 4 (3 bit)
DEV_13 : If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 3 - 6 (4 bit)
DEV_14 : If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 4 - 8 (5 bit)
DEV_15 : If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 5 - 10 (6 bit)
DEV_16 : If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 6 - 12 (7 bit)
DEV_17 : If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 7 - 14 (8 bit)
DEV_18 : If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 8 - 16 (9 bit)
DEV_19 : If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 9 - 18 (10 bit)
DEV_110 : If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 10 - 20 (11 bit)
DEV_111 : If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 11 - 22 (12 bit)
DEV_112 : If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 12 - 24 (13 bit)
DEV_113 : If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 13 - 26 (14 bit)
DEV_114 : If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 14 - 28 (15 bit)
DEV_115 : If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 45 (30 bit)
DRL1 : A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
bits : 30 - 60 (31 bit)
DRQ1 : This read-only bit indicates the state of DMA Request 1.
bits : 31 - 62 (32 bit)
SCT limit register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LIMMSK_L : If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
bits : 0 - 15 (16 bit)
LIMMSK_H : If bit n is one, event n is used as a counter limit event for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).
bits : 16 - 47 (32 bit)
SCT halt condition register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALTMSK_L : If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
bits : 0 - 15 (16 bit)
HALTMSK_H : If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).
bits : 16 - 47 (32 bit)
SCT event enable register
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IEN0 : The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 0 (1 bit)
IEN1 : The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 1 - 2 (2 bit)
IEN2 : The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 2 - 4 (3 bit)
IEN3 : The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 3 - 6 (4 bit)
IEN4 : The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 4 - 8 (5 bit)
IEN5 : The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 5 - 10 (6 bit)
IEN6 : The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 6 - 12 (7 bit)
IEN7 : The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 7 - 14 (8 bit)
IEN8 : The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 8 - 16 (9 bit)
IEN9 : The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 9 - 18 (10 bit)
IEN10 : The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 10 - 20 (11 bit)
IEN11 : The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 11 - 22 (12 bit)
IEN12 : The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 12 - 24 (13 bit)
IEN13 : The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 13 - 26 (14 bit)
IEN14 : The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 14 - 28 (15 bit)
IEN15 : The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT event flag register
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLAG0 : Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 0 - 0 (1 bit)
FLAG1 : Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 1 - 2 (2 bit)
FLAG2 : Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 2 - 4 (3 bit)
FLAG3 : Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 3 - 6 (4 bit)
FLAG4 : Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 4 - 8 (5 bit)
FLAG5 : Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 5 - 10 (6 bit)
FLAG6 : Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 6 - 12 (7 bit)
FLAG7 : Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 7 - 14 (8 bit)
FLAG8 : Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 8 - 16 (9 bit)
FLAG9 : Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 9 - 18 (10 bit)
FLAG10 : Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 10 - 20 (11 bit)
FLAG11 : Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 11 - 22 (12 bit)
FLAG12 : Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 12 - 24 (13 bit)
FLAG13 : Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 13 - 26 (14 bit)
FLAG14 : Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 14 - 28 (15 bit)
FLAG15 : Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT conflict enable register
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NCEN0 : The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 0 - 0 (1 bit)
NCEN1 : The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 1 - 2 (2 bit)
NCEN2 : The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 2 - 4 (3 bit)
NCEN3 : The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 3 - 6 (4 bit)
NCEN4 : The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 4 - 8 (5 bit)
NCEN5 : The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 5 - 10 (6 bit)
NCEN6 : The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 6 - 12 (7 bit)
NCEN7 : The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 7 - 14 (8 bit)
NCEN8 : The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 8 - 16 (9 bit)
NCEN9 : The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 9 - 18 (10 bit)
NCEN10 : The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 10 - 20 (11 bit)
NCEN11 : The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 11 - 22 (12 bit)
NCEN12 : The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 12 - 24 (13 bit)
NCEN13 : The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 13 - 26 (14 bit)
NCEN14 : The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 14 - 28 (15 bit)
NCEN15 : The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 15 - 30 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
SCT conflict flag register
address_offset : 0xFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NCFLAG0 : Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 0 - 0 (1 bit)
NCFLAG1 : Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 1 - 2 (2 bit)
NCFLAG2 : Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 2 - 4 (3 bit)
NCFLAG3 : Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 3 - 6 (4 bit)
NCFLAG4 : Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 4 - 8 (5 bit)
NCFLAG5 : Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 5 - 10 (6 bit)
NCFLAG6 : Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 6 - 12 (7 bit)
NCFLAG7 : Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 7 - 14 (8 bit)
NCFLAG8 : Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 8 - 16 (9 bit)
NCFLAG9 : Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 9 - 18 (10 bit)
NCFLAG10 : Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 10 - 20 (11 bit)
NCFLAG11 : Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 11 - 22 (12 bit)
NCFLAG12 : Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 12 - 24 (13 bit)
NCFLAG13 : Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 13 - 26 (14 bit)
NCFLAG14 : Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 14 - 28 (15 bit)
NCFLAG15 : Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).
bits : 15 - 30 (16 bit)
RESERVED : Reserved.
bits : 16 - 45 (30 bit)
BUSERRL : The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful.
bits : 30 - 60 (31 bit)
BUSERRH : The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted.
bits : 31 - 62 (32 bit)
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