\n
address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected
Signature start address register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Signature generation start address (corresponds to AHB byte address bits[20:4]).
bits : 0 - 16 (17 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 17 - 48 (32 bit)
Signature stop-address register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOP : BIST stop address divided by 16 (corresponds to AHB byte address [20:4]).
bits : 0 - 16 (17 bit)
SIG_START : Start control bit for signature generation.
bits : 17 - 34 (18 bit)
Enumeration: ENUM
0 : STOP
Signature generation is stopped
1 : START
Initiate signature generation
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 18 - 49 (32 bit)
128-bit signature Word 0
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SW0_31_0 : Word 0 of 128-bit signature (bits 31 to 0).
bits : 0 - 31 (32 bit)
128-bit signature Word 1
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SW1_63_32 : Word 1 of 128-bit signature (bits 63 to 32).
bits : 0 - 31 (32 bit)
128-bit signature Word 2
address_offset : 0x34 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SW2_95_64 : Word 2 of 128-bit signature (bits 95 to 64).
bits : 0 - 31 (32 bit)
128-bit signature Word 3
address_offset : 0x38 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SW3_127_96 : Word 3 of 128-bit signature (bits 127 to 96).
bits : 0 - 31 (32 bit)
EEPROM command register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Command. 000: 8-bit read 001: 16-bit read 010: 32-bit read 011: 8-bit write 100: 16-bit write 101: 32-bit write 110: erase/program page 111: reserved
bits : 0 - 2 (3 bit)
RDPREFETCH : Read data prefetch bit. 0: do not prefetch next read data as result of reading from the read data register. 1: prefetch read data as result of reading from the read data register. When this bit is set multiple consecutive data elements can be read without the need of programming new address values in the address register. The address post-increment and the automatic read data prefetch (if enabled) allow only reading from the read data register to be done to read the data.
bits : 3 - 6 (4 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 4 - 35 (32 bit)
EEPROM address register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : EEPROM Address. Lower 6 bits are don't care.
bits : 0 - 11 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 43 (32 bit)
EEPROM write data register
address_offset : 0x88 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WDATA : Write data. In case of: 8-bit write operations: bits [7:0] must contain valid write data. 16-bit write operations: bits [15:0] must contain valid write data. 32-bit write operations: bits [31:0] must contain valid write data.
bits : 0 - 31 (32 bit)
EEPROM read data register
address_offset : 0x8C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATA : Read data. In case of: 8-bit read operations: bits [7:0] contain read data, others are zero. 16-bit read operations: bits [15:0] contain read data, others are zero. 32-bit read operations: bits [31:0] contain read data.
bits : 0 - 31 (32 bit)
EEPROM wait state register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHASE3 : Wait states 3 (minus 1 encoded). The number of system clock periods required to give a minimum time of 15 ns.
bits : 0 - 7 (8 bit)
PHASE2 : Wait states 2 (minus 1 encoded). The number of system clock periods required to give a minimum time of 55 ns.
bits : 8 - 23 (16 bit)
PHASE1 : Wait states 1 (minus 1 encoded). The number of system clock periods required to give a minimum time of 35 ns.
bits : 16 - 39 (24 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 55 (32 bit)
EEPROM clock divider register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIV : Division factor (minus 1 encoded).
bits : 0 - 15 (16 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 16 - 47 (32 bit)
EEPROM power-down register
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWRDWN : Power down mode bit. 0: not in power down mode. 1: power down mode (this will put all EEPROM devices in power down).
bits : 0 - 0 (1 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 32 (32 bit)
EEPROM interrupt enable clear
address_offset : 0xFD8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RDWR_CLR_EN : Clear read/write operation finished interrupt enable bit (EEPROM). 0: leave corresponding bit unchanged. 1: clear corresponding bit.
bits : 26 - 52 (27 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 27 - 54 (28 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 27 - 54 (28 bit)
PROG1_CLR_EN : Clear program operation finished interrupt enable bit for EEPROM device 1. 0: leave corresponding bit unchanged. 1: clear corresponding bit.
bits : 28 - 56 (29 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 29 - 60 (32 bit)
EEPROM interrupt enable set
address_offset : 0xFDC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RDWR_SET_EN : Set read/write operation finished interrupt enable bit (EEPROM). 0: leave corresponding bit unchanged. 1: set corresponding bit.
bits : 26 - 52 (27 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 27 - 54 (28 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 27 - 54 (28 bit)
PROG1_SET_EN : Set program operation finished interrupt enable bit for EEPROM device 1. 0: leave corresponding bit unchanged. 1: set corresponding bit.
bits : 28 - 56 (29 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 29 - 60 (32 bit)
Signature generation status register
address_offset : 0xFE0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SIG_DONE : When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag.
bits : 2 - 4 (3 bit)
RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 3 - 28 (26 bit)
END_OF_RDWR : EEPROM read/write operation finished interrupt status bit. Bit is: - set when this operation has finished OR when 1 is written in the corresponding bit of the EEINTSTATSET register. - cleared when 1 is written to the corresponding bit of the EEINTSTATCLR register.
bits : 26 - 52 (27 bit)
RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 27 - 54 (28 bit)
RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 27 - 54 (28 bit)
END_OF_PROG1 : EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when 1 is written to the corresponding bit of the EEINTSTATSET register. - cleared when 1 is written to the corresponding bit of the EEINTSTATCLR register.
bits : 28 - 56 (29 bit)
RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 29 - 60 (32 bit)
EEPROM interrupt enable
address_offset : 0xFE4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EE_RW_DONE : EEPROM read/write operation finished interrupt enable bit. Bit is: - set when 1 is written to the corresponding bit of the EEINTENSET register. - cleared when 1 is written to the corresponding bit of the EEINTENCLR register.
bits : 26 - 52 (27 bit)
RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 27 - 54 (28 bit)
RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 27 - 54 (28 bit)
EE_PROG_DONE : EEPROM program operation finished interrupt enable bit. Bit is: - set when 1 is written in the corresponding bit of the EEINTENSET register. - cleared when 1 is written to the corresponding bit of the EEINTENCLR register.
bits : 28 - 56 (29 bit)
RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 29 - 60 (32 bit)
Signature generation status clear register
address_offset : 0xFE8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SIG_DONE_CLR : Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register.
bits : 2 - 4 (3 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 28 (26 bit)
RDWR_CLR_ST : Clear read/write operation finished interrupt status bit (EEPROM). 0 leave corresponding bit unchanged. 1 clear corresponding bit.
bits : 26 - 52 (27 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 27 - 54 (28 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 27 - 54 (28 bit)
PROG1_CLR_ST : Clear program operation finished interrupt status bit for EEPROM device 1. 0 leave corresponding bit unchanged. 1 clear corresponding bit.
bits : 28 - 56 (29 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 29 - 60 (32 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.