INTST

INTEN

INTSET

INCLR

PORTSEL

TMR

DEVINTST

DEVINTEN

DEVINTCLR

DEVINTSET

CMDCODE

CMDDATA

RXDATA

TXDATA

TXPLEN

CTRL

DEVINTPRI

EPINTST

EPINTEN

EPINTCLR

EPINTSET

EPINTPRI

REEP

EPIN

MAXPSIZE

DMARST

DMARCLR

DMARSET

UDCAH

EPDMAST

EPDMAEN

EPDMADIS

DMAINTST

DMAINTEN

EOTINTST

EOTINTCLR

EOTINTSET

NDDRINTST

NDDRINTCLR

NDDRINTSET

SYSERRINTST

SYSERRINTCLR

SYSERRINTSET

I2C_RX

I2C_TX

I2C_STS

I2C_CTL

I2C_CLKHI

I2C_CLKLO

RXPLEN

CLKCTRL

OTGClkSt

TMR : Timer time-out.
bits : 0 - 0 (1 bit)

REMOVE_PU : Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor.
bits : 1 - 2 (2 bit)

HNP_FAILURE : HNP failed. This bit is set by hardware to indicate that the HNP switching has failed.
bits : 2 - 4 (3 bit)

HNP_SUCCESS : HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded.
bits : 3 - 6 (4 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 4 - 35 (32 bit)

TMR_EN : 1 = enable the corresponding bit in the IntSt register.
bits : 0 - 0 (1 bit)

REMOVE_PU_EN : 1 = enable the corresponding bit in the IntSt register.
bits : 1 - 2 (2 bit)

HNP_FAILURE_EN : 1 = enable the corresponding bit in the IntSt register.
bits : 2 - 4 (3 bit)

HNP_SUCCES_EN : 1 = enable the corresponding bit in the IntSt register.
bits : 3 - 6 (4 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 4 - 35 (32 bit)

TMR_SET : 0 = no effect. 1 = set the corresponding bit in the IntSt register.
bits : 0 - 0 (1 bit)

REMOVE_PU_SET : 0 = no effect. 1 = set the corresponding bit in the IntSt register.
bits : 1 - 2 (2 bit)

HNP_FAILURE_SET : 0 = no effect. 1 = set the corresponding bit in the IntSt register.
bits : 2 - 4 (3 bit)

HNP_SUCCES_SET : 0 = no effect. 1 = set the corresponding bit in the IntSt register.
bits : 3 - 6 (4 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 4 - 35 (32 bit)

TMR_CLR : 0 = no effect. 1 = clear the corresponding bit in the IntSt register.
bits : 0 - 0 (1 bit)

REMOVE_PU_CLR : 0 = no effect. 1 = clear the corresponding bit in the IntSt register.
bits : 1 - 2 (2 bit)

HNP_FAILURE_CLR : 0 = no effect. 1 = clear the corresponding bit in the IntSt register.
bits : 2 - 4 (3 bit)

HNP_SUCCES_CLR : 0 = no effect. 1 = clear the corresponding bit in the IntSt register.
bits : 3 - 6 (4 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 4 - 35 (32 bit)

PORTSEL : Selects which USB port the device controller signals are mapped to. Other values are reserved.
bits : 0 - 1 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

TMR_SCALE : Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved
bits : 2 - 5 (4 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 2 - 33 (32 bit)

TMR_MODE : Timer mode selection. 0: monoshot 1: free running
bits : 4 - 8 (5 bit)

TMR_EN : Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0.
bits : 5 - 10 (6 bit)

TMR_RST : Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled.
bits : 6 - 12 (7 bit)

B_HNP_TRACK : Enable HNP tracking for B-device (peripheral), see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.
bits : 8 - 16 (9 bit)

A_HNP_TRACK : Enable HNP tracking for A-device (host), see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.
bits : 9 - 18 (10 bit)

PU_REMOVED : When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.
bits : 10 - 20 (11 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 11 - 26 (16 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 11 - 26 (16 bit)

TMR_CNT : Current timer count value.
bits : 16 - 47 (32 bit)

TIMEOUT_CNT : The TMR interrupt is set when TMR_CNT reaches this value.
bits : 0 - 15 (16 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 16 - 47 (32 bit)

FRAME : The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers.
bits : 0 - 0 (1 bit)

EP_FAST : Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit.
bits : 1 - 2 (2 bit)

EP_SLOW : Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit.
bits : 2 - 4 (3 bit)

DEV_STAT : Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366.
bits : 3 - 6 (4 bit)

CCEMPTY : The command code register (USBCmdCode) is empty (New command can be written).
bits : 4 - 8 (5 bit)

CDFULL : Command data register (USBCmdData) is full (Data can be read now).
bits : 5 - 10 (6 bit)

RxENDPKT : The current packet in the endpoint buffer is transferred to the CPU.
bits : 6 - 12 (7 bit)

TxENDPKT : The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen).
bits : 7 - 14 (8 bit)

EP_RLZED : Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed.
bits : 8 - 16 (9 bit)

ERR_INT : Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368
bits : 9 - 18 (10 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 10 - 41 (32 bit)

FRAMEEN : 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
bits : 0 - 0 (1 bit)

EP_FASTEN : 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
bits : 1 - 2 (2 bit)

EP_SLOWEN : 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
bits : 2 - 4 (3 bit)

DEV_STATEN : 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
bits : 3 - 6 (4 bit)

CCEMPTYEN : 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
bits : 4 - 8 (5 bit)

CDFULLEN : 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
bits : 5 - 10 (6 bit)

RxENDPKTEN : 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
bits : 6 - 12 (7 bit)

TxENDPKTEN : 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
bits : 7 - 14 (8 bit)

EP_RLZEDEN : 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
bits : 8 - 16 (9 bit)

ERR_INTEN : 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
bits : 9 - 18 (10 bit)

RESERVED : Reserved
bits : 10 - 41 (32 bit)

FRAMECLR : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
bits : 0 - 0 (1 bit)

EP_FASTCLR : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
bits : 1 - 2 (2 bit)

EP_SLOWCLR : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
bits : 2 - 4 (3 bit)

DEV_STATCLR : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
bits : 3 - 6 (4 bit)

CCEMPTYCLR : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
bits : 4 - 8 (5 bit)

CDFULLCLR : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
bits : 5 - 10 (6 bit)

RxENDPKTCLR : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
bits : 6 - 12 (7 bit)

TxENDPKTCLR : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
bits : 7 - 14 (8 bit)

EP_RLZEDCLR : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
bits : 8 - 16 (9 bit)

ERR_INTCLR : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
bits : 9 - 18 (10 bit)

RESERVED : Reserved
bits : 10 - 41 (32 bit)

FRAMESET : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
bits : 0 - 0 (1 bit)

EP_FASTSET : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
bits : 1 - 2 (2 bit)

EP_SLOWSET : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
bits : 2 - 4 (3 bit)

DEV_STATSET : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
bits : 3 - 6 (4 bit)

CCEMPTYSET : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
bits : 4 - 8 (5 bit)

CDFULLSET : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
bits : 5 - 10 (6 bit)

RxENDPKTSET : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
bits : 6 - 12 (7 bit)

TxENDPKTSET : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
bits : 7 - 14 (8 bit)

EP_RLZEDSET : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
bits : 8 - 16 (9 bit)

ERR_INTSET : 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
bits : 9 - 18 (10 bit)

RESERVED : Reserved
bits : 10 - 41 (32 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 0 - 7 (8 bit)

CMD_PHASE : The command phase:
bits : 8 - 23 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

CMD_CODE_WDATA : This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA).
bits : 16 - 39 (24 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 55 (32 bit)

CMD_RDATA : Command Read Data.
bits : 0 - 7 (8 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)

RX_DATA : Data received.
bits : 0 - 31 (32 bit)

TX_DATA : Transmit Data.
bits : 0 - 31 (32 bit)

PKT_LNGTH : The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt.
bits : 0 - 9 (10 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 41 (32 bit)

RD_EN : Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

WR_EN : Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

LOG_ENDPOINT : Logical Endpoint number.
bits : 2 - 7 (6 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 6 - 37 (32 bit)

FRAME : Frame interrupt routing
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

EP_FAST : Fast endpoint interrupt routing
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 2 - 33 (32 bit)

EPST0 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 0 - 0 (1 bit)

EPST1 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 1 - 2 (2 bit)

EPST2 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 2 - 4 (3 bit)

EPST3 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 3 - 6 (4 bit)

EPST4 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 4 - 8 (5 bit)

EPST5 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 5 - 10 (6 bit)

EPST6 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 6 - 12 (7 bit)

EPST7 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 7 - 14 (8 bit)

EPST8 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 8 - 16 (9 bit)

EPST9 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 9 - 18 (10 bit)

EPST10 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 10 - 20 (11 bit)

EPST11 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 11 - 22 (12 bit)

EPST12 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 12 - 24 (13 bit)

EPST13 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 13 - 26 (14 bit)

EPST14 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 14 - 28 (15 bit)

EPST15 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 15 - 30 (16 bit)

EPST16 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 16 - 32 (17 bit)

EPST17 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 17 - 34 (18 bit)

EPST18 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 18 - 36 (19 bit)

EPST19 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 19 - 38 (20 bit)

EPST20 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 20 - 40 (21 bit)

EPST21 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 21 - 42 (22 bit)

EPST22 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 22 - 44 (23 bit)

EPST23 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 23 - 46 (24 bit)

EPST24 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 24 - 48 (25 bit)

EPST25 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 25 - 50 (26 bit)

EPST26 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 26 - 52 (27 bit)

EPST27 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 27 - 54 (28 bit)

EPST28 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 28 - 56 (29 bit)

EPST29 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 29 - 58 (30 bit)

EPST30 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 30 - 60 (31 bit)

EPST31 : 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
bits : 31 - 62 (32 bit)

EPEN0 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 0 - 0 (1 bit)

EPEN1 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 1 - 2 (2 bit)

EPEN2 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 2 - 4 (3 bit)

EPEN3 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 3 - 6 (4 bit)

EPEN4 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 4 - 8 (5 bit)

EPEN5 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 5 - 10 (6 bit)

EPEN6 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 6 - 12 (7 bit)

EPEN7 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 7 - 14 (8 bit)

EPEN8 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 8 - 16 (9 bit)

EPEN9 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 9 - 18 (10 bit)

EPEN10 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 10 - 20 (11 bit)

EPEN11 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 11 - 22 (12 bit)

EPEN12 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 12 - 24 (13 bit)

EPEN13 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 13 - 26 (14 bit)

EPEN14 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 14 - 28 (15 bit)

EPEN15 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 15 - 30 (16 bit)

EPEN16 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 16 - 32 (17 bit)

EPEN17 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 17 - 34 (18 bit)

EPEN18 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 18 - 36 (19 bit)

EPEN19 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 19 - 38 (20 bit)

EPEN20 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 20 - 40 (21 bit)

EPEN21 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 21 - 42 (22 bit)

EPEN22 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 22 - 44 (23 bit)

EPEN23 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 23 - 46 (24 bit)

EPEN24 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 24 - 48 (25 bit)

EPEN25 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 25 - 50 (26 bit)

EPEN26 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 26 - 52 (27 bit)

EPEN27 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 27 - 54 (28 bit)

EPEN28 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 28 - 56 (29 bit)

EPEN29 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 29 - 58 (30 bit)

EPEN30 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 30 - 60 (31 bit)

EPEN31 : 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
bits : 31 - 62 (32 bit)

EPCLR0 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 0 - 0 (1 bit)

EPCLR1 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 1 - 2 (2 bit)

EPCLR2 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 2 - 4 (3 bit)

EPCLR3 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 3 - 6 (4 bit)

EPCLR4 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 4 - 8 (5 bit)

EPCLR5 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 5 - 10 (6 bit)

EPCLR6 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 6 - 12 (7 bit)

EPCLR7 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 7 - 14 (8 bit)

EPCLR8 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 8 - 16 (9 bit)

EPCLR9 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 9 - 18 (10 bit)

EPCLR10 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 10 - 20 (11 bit)

EPCLR11 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 11 - 22 (12 bit)

EPCLR12 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 12 - 24 (13 bit)

EPCLR13 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 13 - 26 (14 bit)

EPCLR14 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 14 - 28 (15 bit)

EPCLR15 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 15 - 30 (16 bit)

EPCLR16 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 16 - 32 (17 bit)

EPCLR17 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 17 - 34 (18 bit)

EPCLR18 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 18 - 36 (19 bit)

EPCLR19 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 19 - 38 (20 bit)

EPCLR20 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 20 - 40 (21 bit)

EPCLR21 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 21 - 42 (22 bit)

EPCLR22 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 22 - 44 (23 bit)

EPCLR23 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 23 - 46 (24 bit)

EPCLR24 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 24 - 48 (25 bit)

EPCLR25 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 25 - 50 (26 bit)

EPCLR26 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 26 - 52 (27 bit)

EPCLR27 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 27 - 54 (28 bit)

EPCLR28 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 28 - 56 (29 bit)

EPCLR29 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 29 - 58 (30 bit)

EPCLR30 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 30 - 60 (31 bit)

EPCLR31 : 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
bits : 31 - 62 (32 bit)

EPSET0 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 0 - 0 (1 bit)

EPSET1 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 1 - 2 (2 bit)

EPSET2 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 2 - 4 (3 bit)

EPSET3 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 3 - 6 (4 bit)

EPSET4 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 4 - 8 (5 bit)

EPSET5 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 5 - 10 (6 bit)

EPSET6 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 6 - 12 (7 bit)

EPSET7 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 7 - 14 (8 bit)

EPSET8 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 8 - 16 (9 bit)

EPSET9 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 9 - 18 (10 bit)

EPSET10 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 10 - 20 (11 bit)

EPSET11 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 11 - 22 (12 bit)

EPSET12 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 12 - 24 (13 bit)

EPSET13 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 13 - 26 (14 bit)

EPSET14 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 14 - 28 (15 bit)

EPSET15 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 15 - 30 (16 bit)

EPSET16 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 16 - 32 (17 bit)

EPSET17 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 17 - 34 (18 bit)

EPSET18 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 18 - 36 (19 bit)

EPSET19 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 19 - 38 (20 bit)

EPSET20 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 20 - 40 (21 bit)

EPSET21 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 21 - 42 (22 bit)

EPSET22 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 22 - 44 (23 bit)

EPSET23 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 23 - 46 (24 bit)

EPSET24 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 24 - 48 (25 bit)

EPSET25 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 25 - 50 (26 bit)

EPSET26 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 26 - 52 (27 bit)

EPSET27 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 27 - 54 (28 bit)

EPSET28 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 28 - 56 (29 bit)

EPSET29 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 29 - 58 (30 bit)

EPSET30 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 30 - 60 (31 bit)

EPSET31 : 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
bits : 31 - 62 (32 bit)

EPPRI0 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 0 - 0 (1 bit)

EPPRI1 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 1 - 2 (2 bit)

EPPRI2 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 2 - 4 (3 bit)

EPPRI3 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 3 - 6 (4 bit)

EPPRI4 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 4 - 8 (5 bit)

EPPRI5 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 5 - 10 (6 bit)

EPPRI6 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 6 - 12 (7 bit)

EPPRI7 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 7 - 14 (8 bit)

EPPRI8 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 8 - 16 (9 bit)

EPPRI9 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 9 - 18 (10 bit)

EPPRI10 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 10 - 20 (11 bit)

EPPRI11 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 11 - 22 (12 bit)

EPPRI12 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 12 - 24 (13 bit)

EPPRI13 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 13 - 26 (14 bit)

EPPRI14 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 14 - 28 (15 bit)

EPPRI15 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 15 - 30 (16 bit)

EPPRI16 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 16 - 32 (17 bit)

EPPRI17 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 17 - 34 (18 bit)

EPPRI18 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 18 - 36 (19 bit)

EPPRI19 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 19 - 38 (20 bit)

EPPRI20 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 20 - 40 (21 bit)

EPPRI21 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 21 - 42 (22 bit)

EPPRI22 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 22 - 44 (23 bit)

EPPRI23 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 23 - 46 (24 bit)

EPPRI24 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 24 - 48 (25 bit)

EPPRI25 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 25 - 50 (26 bit)

EPPRI26 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 26 - 52 (27 bit)

EPPRI27 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 27 - 54 (28 bit)

EPPRI28 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 28 - 56 (29 bit)

EPPRI29 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 29 - 58 (30 bit)

EPPRI30 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 30 - 60 (31 bit)

EPPRI31 : 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bits : 31 - 62 (32 bit)

EPR0 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 0 - 0 (1 bit)

EPR1 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 1 - 2 (2 bit)

EPR2 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 2 - 4 (3 bit)

EPR3 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 3 - 6 (4 bit)

EPR4 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 4 - 8 (5 bit)

EPR5 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 5 - 10 (6 bit)

EPR6 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 6 - 12 (7 bit)

EPR7 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 7 - 14 (8 bit)

EPR8 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 8 - 16 (9 bit)

EPR9 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 9 - 18 (10 bit)

EPR10 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 10 - 20 (11 bit)

EPR11 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 11 - 22 (12 bit)

EPR12 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 12 - 24 (13 bit)

EPR13 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 13 - 26 (14 bit)

EPR14 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 14 - 28 (15 bit)

EPR15 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 15 - 30 (16 bit)

EPR16 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 16 - 32 (17 bit)

EPR17 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 17 - 34 (18 bit)

EPR18 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 18 - 36 (19 bit)

EPR19 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 19 - 38 (20 bit)

EPR20 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 20 - 40 (21 bit)

EPR21 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 21 - 42 (22 bit)

EPR22 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 22 - 44 (23 bit)

EPR23 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 23 - 46 (24 bit)

EPR24 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 24 - 48 (25 bit)

EPR25 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 25 - 50 (26 bit)

EPR26 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 26 - 52 (27 bit)

EPR27 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 27 - 54 (28 bit)

EPR28 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 28 - 56 (29 bit)

EPR29 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 29 - 58 (30 bit)

EPR30 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 30 - 60 (31 bit)

EPR31 : 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
bits : 31 - 62 (32 bit)

PHY_EP : Physical endpoint number (0-31)
bits : 0 - 4 (5 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 5 - 36 (32 bit)

MPS : The maximum packet size value.
bits : 0 - 9 (10 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 41 (32 bit)

EPRST0 : Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0).
bits : 0 - 0 (1 bit)

EPRST1 : Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0).
bits : 1 - 2 (2 bit)

EPRST2 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 2 - 4 (3 bit)

EPRST3 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 3 - 6 (4 bit)

EPRST4 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 4 - 8 (5 bit)

EPRST5 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 5 - 10 (6 bit)

EPRST6 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 6 - 12 (7 bit)

EPRST7 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 7 - 14 (8 bit)

EPRST8 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 8 - 16 (9 bit)

EPRST9 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 9 - 18 (10 bit)

EPRST10 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 10 - 20 (11 bit)

EPRST11 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 11 - 22 (12 bit)

EPRST12 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 12 - 24 (13 bit)

EPRST13 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 13 - 26 (14 bit)

EPRST14 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 14 - 28 (15 bit)

EPRST15 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 15 - 30 (16 bit)

EPRST16 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 16 - 32 (17 bit)

EPRST17 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 17 - 34 (18 bit)

EPRST18 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 18 - 36 (19 bit)

EPRST19 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 19 - 38 (20 bit)

EPRST20 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 20 - 40 (21 bit)

EPRST21 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 21 - 42 (22 bit)

EPRST22 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 22 - 44 (23 bit)

EPRST23 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 23 - 46 (24 bit)

EPRST24 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 24 - 48 (25 bit)

EPRST25 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 25 - 50 (26 bit)

EPRST26 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 26 - 52 (27 bit)

EPRST27 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 27 - 54 (28 bit)

EPRST28 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 28 - 56 (29 bit)

EPRST29 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 29 - 58 (30 bit)

EPRST30 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 30 - 60 (31 bit)

EPRST31 : Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
bits : 31 - 62 (32 bit)

EPRCLR0 : Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0).
bits : 0 - 0 (1 bit)

EPRCLR1 : Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0).
bits : 1 - 2 (2 bit)

EPRCLR2 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 2 - 4 (3 bit)

EPRCLR3 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 3 - 6 (4 bit)

EPRCLR4 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 4 - 8 (5 bit)

EPRCLR5 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 5 - 10 (6 bit)

EPRCLR6 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 6 - 12 (7 bit)

EPRCLR7 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 7 - 14 (8 bit)

EPRCLR8 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 8 - 16 (9 bit)

EPRCLR9 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 9 - 18 (10 bit)

EPRCLR10 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 10 - 20 (11 bit)

EPRCLR11 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 11 - 22 (12 bit)

EPRCLR12 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 12 - 24 (13 bit)

EPRCLR13 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 13 - 26 (14 bit)

EPRCLR14 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 14 - 28 (15 bit)

EPRCLR15 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 15 - 30 (16 bit)

EPRCLR16 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 16 - 32 (17 bit)

EPRCLR17 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 17 - 34 (18 bit)

EPRCLR18 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 18 - 36 (19 bit)

EPRCLR19 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 19 - 38 (20 bit)

EPRCLR20 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 20 - 40 (21 bit)

EPRCLR21 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 21 - 42 (22 bit)

EPRCLR22 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 22 - 44 (23 bit)

EPRCLR23 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 23 - 46 (24 bit)

EPRCLR24 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 24 - 48 (25 bit)

EPRCLR25 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 25 - 50 (26 bit)

EPRCLR26 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 26 - 52 (27 bit)

EPRCLR27 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 27 - 54 (28 bit)

EPRCLR28 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 28 - 56 (29 bit)

EPRCLR29 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 29 - 58 (30 bit)

EPRCLR30 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 30 - 60 (31 bit)

EPRCLR31 : Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
bits : 31 - 62 (32 bit)

EPRSET0 : Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0).
bits : 0 - 0 (1 bit)

EPRSET1 : Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0).
bits : 1 - 2 (2 bit)

EPRSET2 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 2 - 4 (3 bit)

EPRSET3 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 3 - 6 (4 bit)

EPRSET4 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 4 - 8 (5 bit)

EPRSET5 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 5 - 10 (6 bit)

EPRSET6 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 6 - 12 (7 bit)

EPRSET7 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 7 - 14 (8 bit)

EPRSET8 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 8 - 16 (9 bit)

EPRSET9 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 9 - 18 (10 bit)

EPRSET10 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 10 - 20 (11 bit)

EPRSET11 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 11 - 22 (12 bit)

EPRSET12 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 12 - 24 (13 bit)

EPRSET13 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 13 - 26 (14 bit)

EPRSET14 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 14 - 28 (15 bit)

EPRSET15 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 15 - 30 (16 bit)

EPRSET16 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 16 - 32 (17 bit)

EPRSET17 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 17 - 34 (18 bit)

EPRSET18 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 18 - 36 (19 bit)

EPRSET19 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 19 - 38 (20 bit)

EPRSET20 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 20 - 40 (21 bit)

EPRSET21 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 21 - 42 (22 bit)

EPRSET22 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 22 - 44 (23 bit)

EPRSET23 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 23 - 46 (24 bit)

EPRSET24 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 24 - 48 (25 bit)

EPRSET25 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 25 - 50 (26 bit)

EPRSET26 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 26 - 52 (27 bit)

EPRSET27 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 27 - 54 (28 bit)

EPRSET28 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 28 - 56 (29 bit)

EPRSET29 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 29 - 58 (30 bit)

EPRSET30 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 30 - 60 (31 bit)

EPRSET31 : Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
bits : 31 - 62 (32 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries.
bits : 0 - 6 (7 bit)

UDCA_ADDR : Start address of the UDCA.
bits : 7 - 38 (32 bit)

EP_DMA_ST0 : Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0).
bits : 0 - 0 (1 bit)

EP_DMA_ST1 : Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0).
bits : 1 - 2 (2 bit)

EP_DMA_ST2 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 2 - 4 (3 bit)

EP_DMA_ST3 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 3 - 6 (4 bit)

EP_DMA_ST4 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 4 - 8 (5 bit)

EP_DMA_ST5 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 5 - 10 (6 bit)

EP_DMA_ST6 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 6 - 12 (7 bit)

EP_DMA_ST7 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 7 - 14 (8 bit)

EP_DMA_ST8 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 8 - 16 (9 bit)

EP_DMA_ST9 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 9 - 18 (10 bit)

EP_DMA_ST10 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 10 - 20 (11 bit)

EP_DMA_ST11 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 11 - 22 (12 bit)

EP_DMA_ST12 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 12 - 24 (13 bit)

EP_DMA_ST13 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 13 - 26 (14 bit)

EP_DMA_ST14 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 14 - 28 (15 bit)

EP_DMA_ST15 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 15 - 30 (16 bit)

EP_DMA_ST16 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 16 - 32 (17 bit)

EP_DMA_ST17 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 17 - 34 (18 bit)

EP_DMA_ST18 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 18 - 36 (19 bit)

EP_DMA_ST19 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 19 - 38 (20 bit)

EP_DMA_ST20 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 20 - 40 (21 bit)

EP_DMA_ST21 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 21 - 42 (22 bit)

EP_DMA_ST22 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 22 - 44 (23 bit)

EP_DMA_ST23 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 23 - 46 (24 bit)

EP_DMA_ST24 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 24 - 48 (25 bit)

EP_DMA_ST25 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 25 - 50 (26 bit)

EP_DMA_ST26 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 26 - 52 (27 bit)

EP_DMA_ST27 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 27 - 54 (28 bit)

EP_DMA_ST28 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 28 - 56 (29 bit)

EP_DMA_ST29 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 29 - 58 (30 bit)

EP_DMA_ST30 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 30 - 60 (31 bit)

EP_DMA_ST31 : Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
bits : 31 - 62 (32 bit)

EP_DMA_EN0 : Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0).
bits : 0 - 0 (1 bit)

EP_DMA_EN1 : Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0).
bits : 1 - 2 (2 bit)

EP_DMA_EN : Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx.
bits : 2 - 33 (32 bit)

EP_DMA_DIS0 : Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0).
bits : 0 - 0 (1 bit)

EP_DMA_DIS1 : Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0).
bits : 1 - 2 (2 bit)

EP_DMA_DIS2 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 2 - 4 (3 bit)

EP_DMA_DIS3 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 3 - 6 (4 bit)

EP_DMA_DIS4 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 4 - 8 (5 bit)

EP_DMA_DIS5 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 5 - 10 (6 bit)

EP_DMA_DIS6 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 6 - 12 (7 bit)

EP_DMA_DIS7 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 7 - 14 (8 bit)

EP_DMA_DIS8 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 8 - 16 (9 bit)

EP_DMA_DIS9 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 9 - 18 (10 bit)

EP_DMA_DIS10 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 10 - 20 (11 bit)

EP_DMA_DIS11 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 11 - 22 (12 bit)

EP_DMA_DIS12 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 12 - 24 (13 bit)

EP_DMA_DIS13 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 13 - 26 (14 bit)

EP_DMA_DIS14 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 14 - 28 (15 bit)

EP_DMA_DIS15 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 15 - 30 (16 bit)

EP_DMA_DIS16 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 16 - 32 (17 bit)

EP_DMA_DIS17 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 17 - 34 (18 bit)

EP_DMA_DIS18 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 18 - 36 (19 bit)

EP_DMA_DIS19 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 19 - 38 (20 bit)

EP_DMA_DIS20 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 20 - 40 (21 bit)

EP_DMA_DIS21 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 21 - 42 (22 bit)

EP_DMA_DIS22 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 22 - 44 (23 bit)

EP_DMA_DIS23 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 23 - 46 (24 bit)

EP_DMA_DIS24 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 24 - 48 (25 bit)

EP_DMA_DIS25 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 25 - 50 (26 bit)

EP_DMA_DIS26 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 26 - 52 (27 bit)

EP_DMA_DIS27 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 27 - 54 (28 bit)

EP_DMA_DIS28 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 28 - 56 (29 bit)

EP_DMA_DIS29 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 29 - 58 (30 bit)

EP_DMA_DIS30 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 30 - 60 (31 bit)

EP_DMA_DIS31 : Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
bits : 31 - 62 (32 bit)

EOT : End of Transfer Interrupt bit.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

NDDR : New DD Request Interrupt bit.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

ERR : System Error Interrupt bit.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 3 - 34 (32 bit)

EOT : End of Transfer Interrupt enable bit.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

NDDR : New DD Request Interrupt enable bit.
bits : 1 - 2 (2 bit)

Enumeration: ENUM