CTRL

CLKENA

TMOUT

CTYPE

BLKSIZ

BYTCNT

INTMASK

CMDARG

CMD

RESP0

RESP1

RESP2

RESP3

PWREN

MINTSTS

RINTSTS

STATUS

FIFOTH

CDETECT

WRTPRT

TCBCNT

TBBCNT

DEBNCE

RST_N

CLKDIV

BMOD

PLDMND

DBADDR

IDSTS

IDINTEN

DSCADDR

BUFADDR

CLKSRC

CONTROLLER_RESET : Controller reset. To reset controller, software should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles. This resets: - BIU/CIU interface - CIU and state machines - abort_read_data, send_irq_response, and read_wait bits of Control register - start_cmd bit of Command register Does not affect any registers or DMA interface, or FIFO. or host interrupts.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

FIFO_RESET : Fifo reset. To reset FIFO, software should set bit to 1. This bit is auto-cleared after completion of reset operation. auto-cleared after two AHB clocks.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

DMA_RESET : Dma reset. To reset DMA interface, software should set bit to 1. This bit is auto-cleared after two AHB clocks.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

INT_ENABLE : Global interrupt enable/disable bit. The int port is 1 only when this bit is 1 and one or more unmasked interrupts are set.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Always write this bit as 0.
bits : 5 - 10 (6 bit)

READ_WAIT : Read/wait. For sending read-wait to SDIO cards.
bits : 6 - 12 (7 bit)

Enumeration: ENUM

End of enumeration elements list.

SEND_IRQ_RESPONSE : Send irq response. This bit automatically clears once response is sent. To wait for MMC card interrupts, the host issues CMD40, and the SD/MMC controller waits for an interrupt response from the MMC card. In the meantime, if the host wants the SD/MMC interface to exit waiting for interrupt state, it can set this bit, at which time the SD/MMC interface command state-machine sends a CMD40 response on the bus and returns to idle state.
bits : 7 - 14 (8 bit)

Enumeration: ENUM

End of enumeration elements list.

ABORT_READ_DATA : Abort read data. Used in SDIO card suspend sequence.
bits : 8 - 16 (9 bit)

Enumeration: ENUM

End of enumeration elements list.

SEND_CCSD : Send ccsd. When set, the SD/MMC controller sends CCSD to the CE-ATA device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device. Once the CCSD pattern is sent to device, the SD/MMC interface automatically clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and generates interrupt to host if Command Done interrupt is not masked. NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, during the boundary conditions it may happen that CCSD is sent to the CE-ATA device, even if the device signalled CCS.
bits : 9 - 18 (10 bit)

Enumeration: ENUM

End of enumeration elements list.

SEND_AUTO_STOP : Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and send_ccsd bits together send_auto_stop_ccsd should not be set independent of send_ccsd. When set, the SD/MMC interface automatically sends internallygenerated STOP command (CMD12) to CE-ATA device. After sending internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set and generates interrupt to host if Auto Command Done interrupt is not masked. After sending the CCSD, the SD/MMC interface automatically clears send_auto_stop_ccsd bit.
bits : 10 - 20 (11 bit)

Enumeration: ENUM

End of enumeration elements list.

CEATA_DEVICE_INTERRUPT_STATUS : CEATA device interrupt status. Software should appropriately write to this bit after power-on reset or any other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software should set this bit.
bits : 11 - 22 (12 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 12 - 27 (16 bit)

CARD_VOLTAGE_A0 : Controls the state of the SD_VOLT0 pin. SD/MMC card voltage control is not implemented.
bits : 16 - 32 (17 bit)

CARD_VOLTAGE_A1 : Controls the state of the SD_VOLT1 pin. SD/MMC card voltage control is not implemented.
bits : 17 - 34 (18 bit)

CARD_VOLTAGE_A2 : Controls the state of the SD_VOLT2 pin. SD/MMC card voltage control is not implemented.
bits : 18 - 36 (19 bit)

RESERVED : Reserved.
bits : 19 - 42 (24 bit)

RESERVED : Reserved. Always write this bit as 0.
bits : 24 - 48 (25 bit)

RESERVED : Reserved. Always write this bit as 0.
bits : 24 - 48 (25 bit)

USE_INTERNAL_DMAC : SD/MMC DMA use.
bits : 25 - 50 (26 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 26 - 57 (32 bit)

CCLK_ENABLE : Clock-enable control for SD card clock. One MMC card clock supported. 0 - Clock disabled 1 - Clock enabled
bits : 0 - 0 (1 bit)

RESERVED : Reserved
bits : 1 - 16 (16 bit)

CCLK_LOW_POWER : Low-power control for SD card clock. One MMC card clock supported. 0 - Non-low-power mode 1 - Low-power mode stop clock when card in IDLE (should be normally set to only MMC and SD memory cards for SDIO cards, if interrupts must be detected, clock should not be stopped).
bits : 16 - 32 (17 bit)

RESERVED : Reserved
bits : 17 - 48 (32 bit)

RESPONSE_TIMEOUT : Response time-out value. Value is in number of card output clocks - cclk_out.
bits : 0 - 7 (8 bit)

DATA_TIMEOUT : Value for card Data Read time-out same value also used for Data Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card. Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card.
bits : 8 - 39 (32 bit)

CARD_WIDTH0 : Indicates if card is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to 0).
bits : 0 - 0 (1 bit)

RESERVED : Reserved
bits : 1 - 16 (16 bit)

CARD_WIDTH1 : Indicates if card is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode.
bits : 16 - 32 (17 bit)

RESERVED : Reserved
bits : 17 - 48 (32 bit)

BLOCK_SIZE : Block size
bits : 0 - 15 (16 bit)

RESERVED : Reserved
bits : 16 - 47 (32 bit)

BYTE_COUNT : Number of bytes to be transferred should be integer multiple of Block Size for block transfers. For undefined number of byte transfers, byte count should be set to 0. When byte count is set to 0, it is responsibility of host to explicitly send stop/abort command to terminate data transfer.
bits : 0 - 31 (32 bit)

CDET : Card detect. Bits used to mask unwanted interrupts. Value of 0 masks interrupt value of 1 enables interrupt.
bits : 0 - 0 (1 bit)

RE : Response error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt value of 1 enables interrupt.
bits : 1 - 2 (2 bit)

CDONE : Command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt value of 1 enables interrupt.
bits : 2 - 4 (3 bit)

DTO : Data transfer over. Bits used to mask unwanted interrupts. Value of 0 masks interrupt value of 1 enables interrupt.
bits : 3 - 6 (4 bit)

TXDR : Transmit FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt value of 1 enables interrupt.
bits : 4 - 8 (5 bit)

RXDR : Receive FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt value of 1 enables interrupt.
bits : 5 - 10 (6 bit)

RCRC : Response CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt value of 1 enables interrupt.
bits : 6 - 12 (7 bit)

DCRC : Data CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt value of 1 enables interrupt.
bits : 7 - 14 (8 bit)

RTO : Response time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt value of 1 enables interrupt.
bits : 8 - 16 (9 bit)

DRTO : Data read time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt value of 1 enables interrupt.
bits : 9 - 18 (10 bit)

HTO : Data starvation-by-host time-out (HTO) /Volt_switch_int. Bits used to mask unwanted interrupts. Value of 0 masks interrupt value of 1 enables interrupt.
bits : 10 - 20 (11 bit)

FRUN : FIFO underrun/overrun error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt value of 1 enables interrupt.
bits : 11 - 22 (12 bit)

HLE : Hardware locked write error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt value of 1 enables interrupt.
bits : 12 - 24 (13 bit)

SBE : Start-bit error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt value of 1 enables interrupt.
bits : 13 - 26 (14 bit)

ACD : Auto command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt value of 1 enables interrupt.
bits : 14 - 28 (15 bit)

EBE : End-bit error (read)/Write no CRC. Bits used to mask unwanted interrupts. Value of 0 masks interrupt value of 1 enables interrupt.
bits : 15 - 30 (16 bit)

SDIO_INT_MASK : Mask SDIO interrupt. When masked, SDIO interrupt detection for card is disabled. A 0 masks an interrupt, and 1 enables an interrupt. In MMC-Ver3.3-only mode, this bit is always 0.
bits : 16 - 32 (17 bit)

RESERVED : Reserved
bits : 17 - 48 (32 bit)

CMD_ARG : Value indicates command argument to be passed to card.
bits : 0 - 31 (32 bit)

CMD_INDEX : Command index
bits : 0 - 5 (6 bit)

RESPONSE_EXPECT : Response expect
bits : 6 - 12 (7 bit)

Enumeration: ENUM

End of enumeration elements list.

RESPONSE_LENGTH : Response length
bits : 7 - 14 (8 bit)

Enumeration: ENUM

End of enumeration elements list.

CHECK_RESPONSE_CRC : Check response crc. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller.
bits : 8 - 16 (9 bit)

Enumeration: ENUM

End of enumeration elements list.

DATA_EXPECTED : Data expected
bits : 9 - 18 (10 bit)

Enumeration: ENUM

End of enumeration elements list.

READ_WRITE : read/write. Don't care if no data expected from card.
bits : 10 - 20 (11 bit)

Enumeration: ENUM

End of enumeration elements list.

TRANSFER_MODE : Transfer mode. Don't care if no data expected.
bits : 11 - 22 (12 bit)

Enumeration: ENUM

End of enumeration elements list.

SEND_AUTO_STOP : Send auto stop. When set, the SD/MMC interface sends stop command to SD_MMC_CEATA cards at end of data transfer. Refer to Table 339 to determine: - when send_auto_stop bit should be set, since some data transfers do not need explicit stop commands - open-ended transfers that software should explicitly send to stop command Additionally, when resume is sent to resume - suspended memory access of SD-Combo card - bit should be set correctly if suspended data transfer needs send_auto_stop. Don't care if no data expected from card.
bits : 12 - 24 (13 bit)

Enumeration: ENUM

End of enumeration elements list.

WAIT_PRVDATA_COMPLETE : Wait prvdata complete. The wait_prvdata_complete = 0 option typically used to query status of card during data transfer or to stop current data transfer card_number should be same as in previous command.
bits : 13 - 26 (14 bit)

Enumeration: ENUM

End of enumeration elements list.

STOP_ABORT_CMD : Stop abort command. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot.
bits : 14 - 28 (15 bit)

Enumeration: ENUM

End of enumeration elements list.

SEND_INITIALIZATION : Send initialization. After power on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory).
bits : 15 - 30 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Always write as 0.
bits : 16 - 36 (21 bit)

UPDATE_CLOCK_REGISTERS_ONLY : Update clock registers only. Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode) provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards.
bits : 21 - 42 (22 bit)

Enumeration: ENUM

End of enumeration elements list.

READ_CEATA_DEVICE : Read ceata device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data time-out indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds.The SD/MMC interface should not indicate read data time-out while waiting for data from CE-ATA device.
bits : 22 - 44 (23 bit)

Enumeration: ENUM

End of enumeration elements list.

CCS_EXPECTED : CCS expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. The SD/MMC controller sets the Data Transfer Over (DTO) bit in the RINTSTS register and generates an interrupt to the host if the Data Transfer Over interrupt is not masked.
bits : 23 - 46 (24 bit)

Enumeration: ENUM

End of enumeration elements list.

ENABLE_BOOT : Enable Boot - this bit should be set only for mandatory boot mode. When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together.
bits : 24 - 48 (25 bit)

EXPECT_BOOT_ACK : Expect Boot Acknowledge. When Software sets this bit along with enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card.
bits : 25 - 50 (26 bit)

DISABLE_BOOT : Disable Boot. When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together.
bits : 26 - 52 (27 bit)

BOOT_MODE : Boot Mode
bits : 27 - 54 (28 bit)

Enumeration: ENUM

End of enumeration elements list.

VOLT_SWITCH : Voltage switch bit
bits : 28 - 56 (29 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 29 - 59 (31 bit)

START_CMD : Start command. Once command is taken by CIU, this bit is cleared. When bit is set, host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt register.
bits : 31 - 62 (32 bit)

RESPONSE0 : Bit[31:0] of response
bits : 0 - 31 (32 bit)

RESPONSE1 : Register represents bit[63:32] of long response. When CIU sends auto-stop command, then response is saved in register. Response for previous command sent by host is still preserved in Response 0 register. Additional auto-stop issued only for data transfer commands, and response type is always short for them. For information on when CIU sends auto-stop commands, refer to Auto-Stop .
bits : 0 - 31 (32 bit)

RESPONSE2 : Bit[95:64] of long response
bits : 0 - 31 (32 bit)

RESPONSE3 : Bit[127:96] of long response
bits : 0 - 31 (32 bit)

POWER_ENABLE : Power on/off switch for card once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card. 0 - power off 1 - power on Optional feature: port can be used as general-purpose output on the SD_POW pin.
bits : 0 - 0 (1 bit)

RESERVED : Reserved
bits : 1 - 32 (32 bit)

CDET : Card detect. Interrupt enabled only if corresponding bit in interrupt mask register is set.
bits : 0 - 0 (1 bit)

RE : Response error. Interrupt enabled only if corresponding bit in interrupt mask register is set.
bits : 1 - 2 (2 bit)

CDONE : Command done. Interrupt enabled only if corresponding bit in interrupt mask register is set.
bits : 2 - 4 (3 bit)

DTO : Data transfer over. Interrupt enabled only if corresponding bit in interrupt mask register is set.
bits : 3 - 6 (4 bit)

TXDR : Transmit FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set.
bits : 4 - 8 (5 bit)

RXDR : Receive FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set.
bits : 5 - 10 (6 bit)

RCRC : Response CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set.
bits : 6 - 12 (7 bit)

DCRC : Data CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set.
bits : 7 - 14 (8 bit)

RTO : Response time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set.
bits : 8 - 16 (9 bit)

DRTO : Data read time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set.
bits : 9 - 18 (10 bit)

HTO : Data starvation-by-host time-out (HTO). Interrupt enabled only if corresponding bit in interrupt mask register is set.
bits : 10 - 20 (11 bit)

FRUN : FIFO underrun/overrun error. Interrupt enabled only if corresponding bit in interrupt mask register is set.
bits : 11 - 22 (12 bit)

HLE : Hardware locked write error. Interrupt enabled only if corresponding bit in interrupt mask register is set.
bits : 12 - 24 (13 bit)

SBE : Start-bit error. Interrupt enabled only if corresponding bit in interrupt mask register is set.
bits : 13 - 26 (14 bit)

ACD : Auto command done. Interrupt enabled only if corresponding bit in interrupt mask register is set.
bits : 14 - 28 (15 bit)

EBE : End-bit error (read)/write no CRC. Interrupt enabled only if corresponding bit in interrupt mask register is set.
bits : 15 - 30 (16 bit)

SDIO_INTERRUPT : Interrupt from SDIO card. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1 enables interrupt 0 masks interrupt). 0 - No SDIO interrupt from card 1 - SDIO interrupt from card In MMC-Ver3.3-only mode, this bit is always 0.
bits : 16 - 32 (17 bit)

RESERVED : Reserved
bits : 17 - 48 (32 bit)

CDET : Card detect. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.
bits : 0 - 0 (1 bit)

RE : Response error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.
bits : 1 - 2 (2 bit)

CDONE : Command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.
bits : 2 - 4 (3 bit)

DTO : Data transfer over. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.
bits : 3 - 6 (4 bit)

TXDR : Transmit FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.
bits : 4 - 8 (5 bit)

RXDR : Receive FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.
bits : 5 - 10 (6 bit)

RCRC : Response CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.
bits : 6 - 12 (7 bit)

DCRC : Data CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.
bits : 7 - 14 (8 bit)

RTO_BAR : Response time-out (RTO)/Boot Ack Received (BAR). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.
bits : 8 - 16 (9 bit)

DRTO_BDS : Data read time-out (DRTO)/Boot Data Start (BDS). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.
bits : 9 - 18 (10 bit)

HTO : Data starvation-by-host time-out (HTO). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status./Volt_switch_int
bits : 10 - 20 (11 bit)

FRUN : FIFO underrun/overrun error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.
bits : 11 - 22 (12 bit)

HLE : Hardware locked write error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.
bits : 12 - 24 (13 bit)

SBE : Start-bit error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.
bits : 13 - 26 (14 bit)

ACD : Auto command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.
bits : 14 - 28 (15 bit)

EBE : End-bit error (read)/write no CRC. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.
bits : 15 - 30 (16 bit)

SDIO_INTERRUPT : Interrupt from SDIO card. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact. 0 - No SDIO interrupt from card 1 - SDIO interrupt from card In MMC-Ver3.3-only mode, bits always 0. Bits are logged regardless of interrupt-mask status.
bits : 16 - 32 (17 bit)

RESERVED : Reserved.
bits : 17 - 48 (32 bit)

FIFO_RX_WATERMARK : FIFO reached Receive watermark level not qualified with data transfer.
bits : 0 - 0 (1 bit)

FIFO_TX_WATERMARK : FIFO reached Transmit watermark level not qualified with data transfer.
bits : 1 - 2 (2 bit)

FIFO_EMPTY : FIFO is empty status
bits : 2 - 4 (3 bit)

FIFO_FULL : FIFO is full status
bits : 3 - 6 (4 bit)

CMDFSMSTATES : Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits. The STATUS Register(7:4) has 4 bits to represent the command FSM states. Using these 4 bits, only 16 states can be represented. Thus three states cannot be represented in the STATUS(7:4) register. The three states that are not represented in the STATUS Register(7:4) are: - Bit 16 - Wait for CCS - Bit 17 - Send CCSD - Bit 18 - Boot Mode Due to this, while command FSM is in Wait for CCS state or Send CCSD or Boot Mode, the Status register indicates status as 0 for the bit field 7:4.
bits : 4 - 11 (8 bit)

DATA_3_STATUS : Raw selected card_data[3] checks whether card is present 0 - card not present 1 - card present
bits : 8 - 16 (9 bit)

DATA_BUSY : Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy
bits : 9 - 18 (10 bit)

DATA_STATE_MC_BUSY : Data transmit or receive state-machine is busy
bits : 10 - 20 (11 bit)

RESPONSE_INDEX : Index of previous response, including any auto-stop sent by core.
bits : 11 - 27 (17 bit)

FIFO_COUNT : FIFO count - Number of filled locations in FIFO
bits : 17 - 46 (30 bit)

DMA_ACK : DMA acknowledge signal state
bits : 30 - 60 (31 bit)

DMA_REQ : DMA request signal state
bits : 31 - 62 (32 bit)

TX_WMARK : FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming. In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: TX_WMark >= 1 Recommended value: TX_WMARK = 16 (means less than or equal to FIFO_DEPTH/2).
bits : 0 - 11 (12 bit)

RX_WMARK : FIFO threshold watermark level when receiving data to card. When FIFO data count reaches greater than this number, DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data. In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt. In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: RX_WMark less than FIFO_DEPTH-2 Recommended: RX_WMARK = 15 (means greater than (FIFO_DEPTH/2) - 1) NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at the end of packet, even if remaining bytes are less than threshold. In this case, there will be some data left in the FIFO. It is the responsibility of the application to reset the FIFO after the CCS time-out.
bits : 16 - 43 (28 bit)

DMA_MTS : Burst size of multiple transaction should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the H_DATA_WIDTH parameter. A single transfer (dw_dma_single assertion in case of Non DW DMA interface) would be signalled based on this value. Value should be sub-multiple of (RX_WMark + 1) and (32 - TX_WMark). For example, if FIFO_DEPTH = 16, FDATA_WIDTH = H_DATA_WIDTH Allowed combinations for MSize and TX_WMark are: MSize = 1, TX_WMARK = 1-15 MSize = 4, TX_WMark = 8 MSize = 4, TX_WMark = 4 MSize = 4, TX_WMark = 12 MSize = 8, TX_WMark = 8 MSize = 8, TX_WMark = 4. Allowed combinations for MSize and RX_WMark are: MSize = 1, RX_WMARK = 0-14 MSize = 4, RX_WMark = 3 MSize = 4, RX_WMark = 7 MSize = 4, RX_WMark = 11 MSize = 8, RX_WMark = 7 MSize = 8, RX_WMark = 11 Recommended: MSize = 8, TX_WMark = 8, RX_WMark = 7
bits : 28 - 58 (31 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 31 - 62 (32 bit)

RESERVED : Reserved
bits : 31 - 62 (32 bit)

CARD_DETECT : Card detect. 0 represents presence of card.
bits : 0 - 0 (1 bit)

RESERVED : Reserved
bits : 1 - 32 (32 bit)

WRITE_PROTECT : Write protect. 1 represents write protection.
bits : 0 - 0 (1 bit)

RESERVED : Reserved
bits : 1 - 32 (32 bit)

TRANS_CARD_BYTE_COUNT : Number of bytes transferred by CIU unit to card. Register should be read only after data transfer completes during data transfer, register returns 0.
bits : 0 - 31 (32 bit)

TRANS_FIFO_BYTE_COUNT : Number of bytes transferred between Host/DMA memory and BIU FIFO.
bits : 0 - 31 (32 bit)

DEBOUNCE_COUNT : Number of host clocks (clk) used by debounce filter logic for card detect typical debounce time is 5-25 ms.
bits : 0 - 23 (24 bit)

RESERVED : Reserved
bits : 24 - 55 (32 bit)

CARD_RESET : Hardware reset. 1 - Active mode 0 - Reset Toggles state on SD_RST pin. This bit causes the card to enter pre-idle state, which requires it to be re-initialized.
bits : 0 - 0 (1 bit)

RESERVED : Reserved
bits : 1 - 32 (32 bit)

CLK_DIVIDER0 : Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on.
bits : 0 - 7 (8 bit)

CLK_DIVIDER1 : Clock divider-1 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported.
bits : 8 - 23 (16 bit)

CLK_DIVIDER2 : Clock divider-2 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported.
bits : 16 - 39 (24 bit)

CLK_DIVIDER3 : Clock divider-3 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported.
bits : 24 - 55 (32 bit)

SWR : Software Reset. When set, the DMA Controller resets all its internal registers. SWR is read/write. It is automatically cleared after 1 clock cycle.
bits : 0 - 0 (1 bit)

FB : Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. FB is read/write.
bits : 1 - 2 (2 bit)

DSL : Descriptor Skip Length. Specifies the number of HWord/Word/Dword to skip between two unchained descriptors. This is applicable only for dual buffer structure. DSL is read/write.
bits : 2 - 8 (7 bit)

DE : SD/MMC DMA Enable. When set, the SD/MMC DMA is enabled. DE is read/write.
bits : 7 - 14 (8 bit)

PBL : Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one SD/MMC DMA transaction. The SD/MMC DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows.Transfer unit is 32 bit. PBL is a read-only value.
bits : 8 - 18 (11 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved
bits : 11 - 42 (32 bit)

PD : Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the SD/MMC DMA state machine to resume normal descriptor fetch operation. This is a write only register. PD bit is write-only.
bits : 0 - 31 (32 bit)

SDL : Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the SD/MMC DMA internally. Hence these LSB bits are read-only.
bits : 0 - 31 (32 bit)

TI : Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a 1 clears this bit.
bits : 0 - 0 (1 bit)

RI : Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit.
bits : 1 - 2 (2 bit)

FBE : Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears this bit.
bits : 2 - 4 (3 bit)

DU : Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit.
bits : 4 - 8 (5 bit)

CES : Card Error Summary. Indicates the status of the transaction to/from the card also present in RINTSTS. Indicates the logical OR of the following bits: EBE - End Bit Error RTO - Response Time-out/Boot Ack Time-out RCRC - Response CRC SBE - Start Bit Error DRTO - Data Read Time-out/BDS time-out DCRC - Data CRC for Receive RE - Response Error Writing a 1 clears this bit.
bits : 5 - 10 (6 bit)

RESERVED : Reserved
bits : 6 - 13 (8 bit)

NIS : Normal Interrupt Summary. Logical OR of the following: IDSTS[0] - Transmit Interrupt IDSTS[1] - Receive Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing a 1 clears this bit.
bits : 8 - 16 (9 bit)

AIS : Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] - Fatal Bus Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] - Card Error Summary Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing a 1 clears this bit.
bits : 9 - 18 (10 bit)

EB : Error Bits. Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt. 001 - Host Abort received during transmission 010 - Host Abort received during reception Others: Reserved EB is read-only.
bits : 10 - 22 (13 bit)

FSM : DMAC state machine present state. 0 - DMA_IDLE 1 - DMA_SUSPEND 2 - DESC_RD 3 - DESC_CHK 4 - DMA_RD_REQ_WAIT 5 - DMA_WR_REQ_WAIT 6 - DMA_RD 7 - DMA_WR 8 - DESC_CLOSE This bit is read-only.
bits : 13 - 29 (17 bit)

RESERVED : Reserved
bits : 17 - 48 (32 bit)

RESERVED : Reserved
bits : 17 - 48 (32 bit)

TI : Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled.
bits : 0 - 0 (1 bit)

RI : Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled.
bits : 1 - 2 (2 bit)

FBE : Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled.
bits : 2 - 4 (3 bit)

DU : Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled.
bits : 4 - 8 (5 bit)

CES : Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary.
bits : 5 - 10 (6 bit)

RESERVED : Reserved
bits : 6 - 13 (8 bit)

NIS : Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0] - Transmit Interrupt IDINTEN[1] - Receive Interrupt
bits : 8 - 16 (9 bit)

AIS : Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2] - Fatal Bus Error Interrupt IDINTEN[4] - DU Interrupt IDINTEN[5] - Card Error Summary Interrupt
bits : 9 - 18 (10 bit)

RESERVED : Reserved
bits : 10 - 41 (32 bit)

RESERVED : Reserved
bits : 10 - 41 (32 bit)

HDA : Host Descriptor Address Pointer. Cleared on reset. Pointer updated by IDMAC during operation. This register points to the start address of the current descriptor read by the SD/MMC DMA.
bits : 0 - 31 (32 bit)

HBA : Host Buffer Address Pointer. Cleared on Reset. Pointer updated by IDMAC during operation. This register points to the current Data Buffer Address being accessed by the SD/MMC DMA.
bits : 0 - 31 (32 bit)

CLK_SOURCE : Clock divider source for SD card. 00 - Clock divider 0 01 - Clock divider 1 10 - Clock divider 2 11 - Clock divider 3 In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.
bits : 0 - 1 (2 bit)

RESERVED : Reserved
bits : 1 - 32 (32 bit)