Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected
ARM Cortex-M4 memory mapping
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M4MAP : Shadow address when accessing memory at address 0x0000 0000
bits : 12 - 43 (32 bit)
Chip configuration register 5. Controls JTAG access.
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Reserved.
bits : 0 - 9 (10 bit)
M0SUBTAPSEL : JTAG debug disable for M0SUB co-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.
bits : 10 - 20 (11 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : DISABLE_JTAG_DEBUG
Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source.
End of enumeration elements list.
M4TAPSEL : JTAG debug disable for M4 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.
bits : 11 - 22 (12 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : DISABLE_JTAG_DEBUG
Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source.
End of enumeration elements list.
M0APPTAPSEL : JTAG debug disable for M0APPco-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.
bits : 12 - 24 (13 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : DISABLE_JTAG_DEBUG
Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source.
End of enumeration elements list.
RESERVED : Reserved.
bits : 13 - 44 (32 bit)
DMA mux control
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAMUXPER0 : Select DMA to peripheral connection for DMA peripheral 0.
bits : 0 - 1 (2 bit)
Enumeration: ENUM
0x0 : SPIFI
SPIFI
0x1 : SCT_CTOUT_2
SCT CTOUT_2
0x2 : SGPIO14
SGPIO14
0x3 : TIMER3_MATCH_1
Timer3 match 1
End of enumeration elements list.
DMAMUXPER1 : Select DMA to peripheral connection for DMA peripheral 1
bits : 2 - 5 (4 bit)
Enumeration: ENUM
0x0 : TIMER0_MATCH_0
Timer0 match 0
0x1 : USART0_TRANSMIT
USART0 transmit
0x2 : RESERVED
Reserved
0x3 : RESERVED
Reserved
End of enumeration elements list.
DMAMUXPER2 : Select DMA to peripheral connection for DMA peripheral 2.
bits : 4 - 9 (6 bit)
Enumeration: ENUM
0x0 : TIMER0_MATCH_1
Timer0 match 1
0x1 : USART0_RECEIVE
USART0 receive
0x2 : RESERVED
Reserved
0x3 : RESERVED
Reserved
End of enumeration elements list.
DMAMUXPER3 : Select DMA to peripheral connection for DMA peripheral 3.
bits : 6 - 13 (8 bit)
Enumeration: ENUM
0x0 : TIMER1_MATCH_0
Timer1 match 0
0x1 : UART1_TRANSMIT
UART1 transmit
0x2 : I2S1_DMA_REQUEST_1
I2S1 DMA request 1
0x3 : SSP1_TRANSMIT
SSP1 transmit
End of enumeration elements list.
DMAMUXPER4 : Select DMA to peripheral connection for DMA peripheral 4.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : TIMER1_MATCH_1
Timer1 match 1
0x1 : UART1_RECEIVE
UART1 receive
0x2 : I2S1_DMA_REQUEST_2
I2S1 DMA request 2
0x3 : SSP1_RECEIVE
SSP1 receive
End of enumeration elements list.
DMAMUXPER5 : Select DMA to peripheral connection for DMA peripheral 5.
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : TIMER2_MATCH_0
Timer2 match 0
0x1 : USART2_TRANSMIT
USART2 transmit
0x2 : SSP1_TRANSMIT
SSP1 transmit
0x3 : SGPIO15
SGPIO15
End of enumeration elements list.
DMAMUXPER6 : Selects DMA to peripheral connection for DMA peripheral 6.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : TIMER2_MATCH_1
Timer2 match 1
0x1 : USART2_RECEIVE
USART2 receive
0x2 : SSP1_RECEIVE
SSP1 receive
0x3 : SGPIO14
SGPIO14
End of enumeration elements list.
DMAMUXPER7 : Selects DMA to peripheral connection for DMA peripheral 7.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : TIMER3_MATCH_0
Timer3 match 0
0x1 : USART3_TRANSMIT
USART3 transmit
0x2 : SCT_DMA_REQUEST_0
SCT DMA request 0
0x3 : ADCHS_WRITE
ADCHS write
End of enumeration elements list.
DMAMUXPER8 : Select DMA to peripheral connection for DMA peripheral 8.
bits : 16 - 33 (18 bit)
Enumeration: ENUM
0x0 : TIMER3_MATCH_1
Timer3 match 1
0x1 : USART3_RECEIVE
USART3 receive
0x2 : SCT_DMA_REQUEST_1
SCT DMA request 1
0x3 : ADCHS_READ
ADCHS read
End of enumeration elements list.
DMAMUXPER9 : Select DMA to peripheral connection for DMA peripheral 9.
bits : 18 - 37 (20 bit)
Enumeration: ENUM
0x0 : SSP0_RECEIVE
SSP0 receive
0x1 : I2S0_DMA_REQUEST_1
I2S0 DMA request 1
0x2 : SCT_DMA_REQUEST_1
SCT DMA request 1
0x3 : RESERVED
Reserved
End of enumeration elements list.
DMAMUXPER10 : Select DMA to peripheral connection for DMA peripheral 10.
bits : 20 - 41 (22 bit)
Enumeration: ENUM
0x0 : SSP0_TRANSMIT
SSP0 transmit
0x1 : I2S0_DMA_REQUEST_2
I2S0 DMA request 2
0x2 : SCT_DMA_REQUEST_0
SCT DMA request 0
0x3 : RESERVED
Reserved
End of enumeration elements list.
DMAMUXPER11 : Selects DMA to peripheral connection for DMA peripheral 11.
bits : 22 - 45 (24 bit)
Enumeration: ENUM
0x0 : SSP1_RECEIVE
SSP1 receive
0x1 : SGPIO14
SGPIO14
0x2 : USART0_TRANSMIT
USART0 transmit
0x3 : RESERVED
Reserved
End of enumeration elements list.
DMAMUXPER12 : Select DMA to peripheral connection for DMA peripheral 12.
bits : 24 - 49 (26 bit)
Enumeration: ENUM
0x0 : SSP1_TRANSMIT
SSP1 transmit
0x1 : SGPIO15
SGPIO15
0x2 : USART0_RECEIVE
USART0 receive
0x3 : RESERVED
Reserved
End of enumeration elements list.
DMAMUXPER13 : Select DMA to peripheral connection for DMA peripheral 13.
bits : 26 - 53 (28 bit)
Enumeration: ENUM
0x0 : ADC0
ADC0
0x1 : RESERVED
Reserved
0x2 : SSP1_RECEIVE
SSP1 receive
0x3 : USART3_RECEIVE
USART3 receive
End of enumeration elements list.
DMAMUXPER14 : Select DMA to peripheral connection for DMA peripheral 14.
bits : 28 - 57 (30 bit)
Enumeration: ENUM
0x0 : ADC1
ADC1
0x1 : RESERVED
Reserved
0x2 : SSP1_TRANSMIT
SSP1 transmit
0x3 : USART3_TRANSMIT
USART3 transmit
End of enumeration elements list.
DMAMUXPER15 : Select DMA to peripheral connection for DMA peripheral 15.
bits : 30 - 61 (32 bit)
Enumeration: ENUM
0x0 : DAC
DAC
0x1 : SCT_CTOUT_3
SCT CTOUT_3
0x2 : SGPIO15
SGPIO15
0x3 : TIMER3_MATCH_0
Timer3 match 0
End of enumeration elements list.
Flash accelerator configuration register for flash bank A
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Reserved. Do not change these bits from the reset value.
bits : 0 - 11 (12 bit)
FLASHTIM : Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.
bits : 12 - 27 (16 bit)
Enumeration: ENUM
0x0 : 1_BASE_M4_CLK_CLOCK
1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz.
0x1 : 2_BASE_M4_CLK_CLOCKS
2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz.
0x2 : 3_BASE_M4_CLK_CLOCKS
3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz.
0x3 : 4_BASE_M4_CLK_CLOCKS
4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz.
0x4 : 5_BASE_M4_CLK_CLOCKS
5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz.
0x5 : 6_BASE_M4_CLK_CLOCKS
6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz.
0x6 : 7_BASE_M4_CLK_CLOCKS
7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz.
0x7 : 8_BASE_M4_CLK_CLOCKS
8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz.
0x8 : 9_BASE_M4_CLK_CLOCKS
9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz.
0x9 : 10_BASE_M4_CLK_CLOCK
10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions.
End of enumeration elements list.
RESERVED : Reserved. Write zeros only to these bits.
bits : 16 - 46 (31 bit)
POW : Flash bank A power control
bits : 31 - 62 (32 bit)
Enumeration: ENUM
0 : POWER_DOWN
Power-down
1 : ACTIVE
Active (Default)
End of enumeration elements list.
Flash accelerator configuration register for flash bank B
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Reserved. Do not change these bits from the reset value.
bits : 0 - 11 (12 bit)
FLASHTIM : Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.
bits : 12 - 27 (16 bit)
Enumeration: ENUM
0x0 : 1_BASE_M4_CLK_CLOCK
1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz.
0x1 : 2_BASE_M4_CLK_CLOCKS
2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz.
0x2 : 3_BASE_M4_CLK_CLOCKS
3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz.
0x3 : 4_BASE_M4_CLK_CLOCKS
4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz.
0x4 : 5_BASE_M4_CLK_CLOCKS
5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz.
0x5 : 6_BASE_M4_CLK_CLOCKS
6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz.
0x6 : 7_BASE_M4_CLK_CLOCKS
7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz.
0x7 : 8_BASE_M4_CLK_CLOCKS
8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz.
0x8 : 9_BASE_M4_CLK_CLOCKS
9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz.
0x9 : 10_BASE_M4_CLK_CLOCK
10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions.
End of enumeration elements list.
RESERVED : Reserved. Write zeros only to these bits.
bits : 16 - 46 (31 bit)
POW : Flash bank A power control
bits : 31 - 62 (32 bit)
Enumeration: ENUM
0 : POWER_DOWN
Power-down
1 : ACTIVE
Active (Default)
End of enumeration elements list.
ETB RAM configuration
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETB : Select SRAM interface
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : ETB_ACCESSES_SRAM_AT
ETB accesses SRAM at address 0x2000 C000.
1 : AHB_ACCESSES_SRAM_AT
AHB accesses SRAM at address 0x2000 C000.
End of enumeration elements list.
RESERVED : Reserved.
bits : 1 - 32 (32 bit)
Chip configuration register 6. Controls multiple functions : Ethernet interface, SCT output, I2S0/1 inputs, EMC clock.
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETHMODE : Selects the Ethernet mode. Reset the ethernet after changing the PHY interface. All other settings are reserved.
bits : 0 - 2 (3 bit)
Enumeration: ENUM
0x0 : MII
MII
0x4 : RMII
RMII
End of enumeration elements list.
RESERVED : Reserved.
bits : 3 - 6 (4 bit)
CTOUTCTRL : Selects the functionality of the SCT outputs.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : COMBINE_SCT_AND_TIME
Combine SCT and timer match outputs. SCT outputs are Red with timer outputs.
1 : SCT_OUTPUTS_ONLY
SCT outputs only. SCT outputs are used without timer match outputs.
End of enumeration elements list.
RESERVED : Reserved.
bits : 5 - 16 (12 bit)
I2S0_TX_SCK_IN_SEL : I2S0_TX_SCK input select
bits : 12 - 24 (13 bit)
Enumeration: ENUM
0 : I2S_REGISTER
I2S Register. I2S clock selected as defined by the I2S transmit mode register Table 960.
1 : BASE_AUDIO_CLK_FOR_I
BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode.
End of enumeration elements list.
I2S0_RX_SCK_IN_SEL : I2S0_RX_SCK input select
bits : 13 - 26 (14 bit)
Enumeration: ENUM
0 : I2S_REGISTER
I2S Register. I2S clock selected as defined by the I2S receive mode register Table 961.
1 : BASE_AUDIO_CLK_FOR_I
BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode.
End of enumeration elements list.
I2S1_TX_SCK_IN_SEL : I2S1_TX_SCK input select
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : I2S_REGISTER
I2S register. I2S clock selected as defined by the I2S transmit mode register Table 960.
1 : BASE_AUDIO_CLK_FOR_I
BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode.
End of enumeration elements list.
I2S1_RX_SCK_IN_SEL : I2S1_RX_SCK input select
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : I2S_REGISTER
I2S register. I2S clock selected as defined by the I2S receive mode register Table 961.
1 : BASE_AUDIO_CLK_FOR_I
BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode.
End of enumeration elements list.
EMC_CLK_SEL : EMC_CLK divided clock select (see Section 21.1).
bits : 16 - 32 (17 bit)
Enumeration: ENUM
0 : DIVIDE_BY_1
Divide by 1. EMC_CLK_DIV not divided.
1 : DIVIDE_BY_2
Divide by 2. EMC_CLK_DIV divided by 2.
End of enumeration elements list.
RESERVED : Reserved.
bits : 17 - 48 (32 bit)
Cortex-M4 TXEV event clear
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXEVCLR : Cortex-M4 TXEV event.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : CLEAR_THE_TXEV_EVENT
Clear the TXEV event.
1 : NO_EFFECT
No effect.
End of enumeration elements list.
RESERVED : Reserved.
bits : 1 - 32 (32 bit)
Part ID
address_offset : 0x200 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : Boundary scan ID code 0x5906 002B or 0x6906 002B = LPC4350/30/20/10 (flashless parts) 0x4906 002B = LPC4357/53 (parts with on-chip flash)
bits : 0 - 31 (32 bit)
ARM Cortex-M0SUB memory mapping
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0SUBMAP : Shadow address when accessing memory at address 0x0000 0000
bits : 12 - 43 (32 bit)
Cortex-M0SUB TXEV event clear
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXEVCLR : Cortex-M0SUB TXEV event handling.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : CLEAR_THE_TXEV_EVENT
Clear the TXEV event.
1 : NO_EFFECT
No effect.
End of enumeration elements list.
RESERVED : Reserved.
bits : 1 - 32 (32 bit)
Chip configuration register 32 kHz oscillator output and BOD control register.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN1KHZ : Enable 1 kHz output.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : 1_KHZ_OUTPUT_DISABLE
1 kHz output disabled.
1 : 1_KHZ_OUTPUT_ENABLED
1 kHz output enabled.
End of enumeration elements list.
EN32KHZ : Enable 32 kHz output
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : 32_KHZ_OUTPUT_DISABL
32 kHz output disabled.
1 : 32_KHZ_OUTPUT_ENABLE
32 kHz output enabled.
End of enumeration elements list.
RESET32KHZ : 32 kHz oscillator reset
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : CLEAR_RESET
Clear reset.
1 : RESET_ACTIVE
Reset active.
End of enumeration elements list.
PD32KHZ : 32 kHz power control.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : POWERED
Powered.
1 : POWERED_DOWN
Powered-down.
End of enumeration elements list.
RESERVED : Reserved
bits : 4 - 8 (5 bit)
USB0PHY : USB0 PHY power control.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : ENABLE_USB0_PHY_POWE
Enable USB0 PHY power.
1 : DISABLE_USB0_PHY
Disable USB0 PHY. PHY powered down.
End of enumeration elements list.
ALARMCTRL : RTC_ALARM pin output control
bits : 6 - 13 (8 bit)
Enumeration: ENUM
0x0 : RTC_ALARM
RTC alarm.
0x1 : EVENT_ROUTER_EVENT
Event router event.
0x2 : RESERVED
Reserved.
0x3 : INACTIVE
Inactive.
End of enumeration elements list.
BODLVL1 : BOD trip level to generate an interrupt. See the LPC43xx data sheets for the trip values.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : LEVEL_0_INTERRUPT
Level 0 interrupt
0x1 : LEVEL_1_INTERRUPT
Level 1 interrupt
0x2 : LEVEL_2_INTERRUPT
Level 2 interrupt
0x3 : LEVEL_3_INTERRUPT
Level 3 interrupt
End of enumeration elements list.
BODLVL2 : BOD trip level to generate a reset. See the LPC43xx data sheets for the trip values.
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : LEVEL_0_RESET
Level 0 reset
0x1 : LEVEL_1_RESET
Level 1 reset
0x2 : LEVEL_2_RESET
Level 2 reset
0x3 : LEVEL_3_RESET
Level 3 reset
End of enumeration elements list.
SAMPLECTRL : SAMPLE pin input/output control
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : RESERVED
Reserved
0x1 : SAMPLE_OUTPUT_FROM_T
Sample output from the event monitor/recorder.
0x2 : OUTPUT_FROM_THE_EVEN
Output from the event router.
0x3 : RESERVED
Reserved.
End of enumeration elements list.
WAKEUP0CTRL : WAKEUP0 pin input/output control
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : INPUT_TO_THE_EVENT_R
Input to the event router.
0x1 : OUTPUT_FROM_THE_EVEN
Output from the event router.
0x2 : RESERVED
Reserved.
0x3 : INPUT_TO_THE_EVENT_R
Input to the event router.
End of enumeration elements list.
WAKEUP1CTRL : WAKEUP1 pin input/output control
bits : 16 - 33 (18 bit)
Enumeration: ENUM
0x0 : INPUT_TO_EVENT_ROUTE
Input to event router.
0x1 : OUTPUT_FROM_THE_EVEN
Output from the event router.
0x2 : RESERVED
Reserved
0x3 : INPUT_TO_EVENT_ROUTE
Input to event router.
End of enumeration elements list.
RESERVED : Reserved
bits : 18 - 49 (32 bit)
Cortex-M0APP TXEV event clear
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXEVCLR : Cortex-M0APP TXEV event handling.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : CLEAR_THE_TXEV_EVENT
Clear the TXEV event.
1 : NO_EFFECT
No effect.
End of enumeration elements list.
RESERVED : Reserved.
bits : 1 - 32 (32 bit)
ARM Cortex-M0APP memory mapping
address_offset : 0x404 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0APPMAP : Shadow address when accessing memory at address 0x0000 0000
bits : 12 - 43 (32 bit)
USB0 frame length adjust register
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLTV : Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)
bits : 0 - 5 (6 bit)
RESERVED : Reserved
bits : 6 - 37 (32 bit)
USB1 frame length adjust register
address_offset : 0x600 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLTV : Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)
bits : 0 - 5 (6 bit)
RESERVED : Reserved
bits : 6 - 37 (32 bit)
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