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EVENTROUTER

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected

Registers

HILO

EDGE

CLR_EN

SET_EN

STATUS

ENABLE

CLR_STAT

SET_STAT


HILO

Level configuration register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HILO HILO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAKEUP0_L WAKEUP1_L WAKEUP2_L WAKEUP3_L ATIMER_L RTC_L BOD_L WWDT_L ETH_L USB0_L USB1_L SDMMC_L CAN_L TIM2_L TIM6_L QEI_L TIM14_L RESERVED RESET_L BODRESET_L DPDRESET_L RESERVED

WAKEUP0_L : Level detect mode for WAKEUP0 event.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL

Detect LOW level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect falling edge if bit 0 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL

Detect HIGH level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect rising edge if bit 0 in the EDGE register is 1.

End of enumeration elements list.

WAKEUP1_L : Level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL

Detect LOW level on the WAKEUP1 pin if bit 1 in the EDGE register is 0.

1 : DETECT_HIGH_LEVEL

Detect HIGH level on the WAKEUP1 pin if bit 1 in the EDGE register is 0. Detect rising edge if bit 1 in the EDGE register is 1.

End of enumeration elements list.

WAKEUP2_L : Level detect mode for WAKEUP2 event.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL

Detect LOW level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect falling edge if bit 2 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL

Detect HIGH level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect rising edge if bit 2 in the EDGE register is 1.

End of enumeration elements list.

WAKEUP3_L : Level detect mode for WAKEUP3 event.
bits : 3 - 6 (4 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL

Detect LOW level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect falling edge if bit 3 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL

Detect HIGH level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect rising edge if bit 3 in the EDGE register is 1.

End of enumeration elements list.

ATIMER_L : Level detect mode for alarm timer event.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL

Detect LOW level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect falling edge if bit 4 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL

Detect HIGH level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect rising edge if bit 4 in the EDGE register is 1.

End of enumeration elements list.

RTC_L : Level detect mode for RTC event.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL

Detect LOW level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect falling edge if bit 5 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL

Detect HIGH level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect rising edge if bit 5 in the EDGE register is 1.

End of enumeration elements list.

BOD_L : Level detect mode for BOD event.
bits : 6 - 12 (7 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL

Detect LOW level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect falling edge if bit 6 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL

Detect HIGH level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect rising edge if bit 6 in the EDGE register is 1.

End of enumeration elements list.

WWDT_L : Level detect mode for WWDT event.
bits : 7 - 14 (8 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL

Detect LOW level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect falling edge if bit 7 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL

Detect HIGH level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect rising edge if bit 7 in the EDGE register is 1.

End of enumeration elements list.

ETH_L : Level detect mode for Ethernet event
bits : 8 - 16 (9 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL

Detect LOW level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect falling edge if bit 8 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL

Detect HIGH level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect rising edge if bit 8 in the EDGE register is 1.

End of enumeration elements list.

USB0_L : Level detect mode for USB0 event
bits : 9 - 18 (10 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL

Detect LOW level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect falling edge if bit 9 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL

Detect HIGH level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect rising edge if bit 9 in the EDGE register is 1.

End of enumeration elements list.

USB1_L : Level detect mode for USB1 event
bits : 10 - 20 (11 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL

Detect LOW level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect falling edge if bit 10 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL

Detect HIGH level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect rising edge if bit 10 in the EDGE register is 1.

End of enumeration elements list.

SDMMC_L : Level detect mode for SD/MMC event
bits : 11 - 22 (12 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL

Detect LOW level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect falling edge if bit 11 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL

Detect HIGH level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect rising edge if bit 11 in the EDGE register is 1.

End of enumeration elements list.

CAN_L : Level detect mode for C_CAN event.
bits : 12 - 24 (13 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL

Detect LOW level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect falling edge if bit 12 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL

Detect HIGH level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect rising edge if bit 12 in the EDGE register is 1.

End of enumeration elements list.

TIM2_L : Level detect mode for combined timer output 2 event.
bits : 13 - 26 (14 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL

Detect LOW level GIMA output 25 if bit 13 in the EDGE register is 0. Detect falling edge if bit 13 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL

Detect HIGH level GIMA output 25 if bit 13 in the EDGE register is 0. Detect rising edge if bit 13 in the EDGE register is 1.

End of enumeration elements list.

TIM6_L : Level detect mode for combined timer output 6 event.
bits : 14 - 28 (15 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL

Detect LOW level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect falling edge if bit 14 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL

Detect HIGH level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect rising edge if bit 14 in the EDGE register is 1.

End of enumeration elements list.

QEI_L : Level detect mode for QEI event.
bits : 15 - 30 (16 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL

Detect LOW level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect falling edge if bit 15 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL

Detect HIGH level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect rising edge if bit 15 in the EDGE register is 1.

End of enumeration elements list.

TIM14_L : Level detect mode for combined timer output 14 event.
bits : 16 - 32 (17 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL

Detect LOW level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect falling edge if bit 16 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL

Detect HIGH level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect rising edge if bit 16 in the EDGE register is 1.

End of enumeration elements list.

RESERVED : Reserved.
bits : 17 - 35 (19 bit)

RESET_L : Level detect mode for Reset
bits : 19 - 38 (20 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL_IF

Detect LOW level if bit 17 in the EDGE register is 0. Detect falling edge if bit 17 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL_IF

Detect HIGH level if bit 17 in the EDGE register is 0. Detect rising edge if bit 17 in the EDGE register is 1.

End of enumeration elements list.

BODRESET_L : Level detect mode for BOD Reset
bits : 20 - 40 (21 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL_IF

Detect LOW level if bit 20 in the EDGE register is 0. Detect falling edge if bit 20 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL_IF

Detect HIGH level if bit 20 in the EDGE register is 0. Detect rising edge if bit 20 in the EDGE register is 1.

End of enumeration elements list.

DPDRESET_L : Level detect mode for Deep power-down Reset
bits : 21 - 42 (22 bit)

Enumeration: ENUM

0 : DETECT_LOW_LEVEL_IF

Detect LOW level if bit 21 in the EDGE register is 0. Detect falling edge if bit 21 in the EDGE register is 1.

1 : DETECT_HIGH_LEVEL_IF

Detect HIGH level if bit 21 in the EDGE register is 0. Detect rising edge if bit 21 in the EDGE register is 1.

End of enumeration elements list.

RESERVED : Reserved.
bits : 22 - 53 (32 bit)


EDGE

Edge configuration
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EDGE EDGE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAKEUP0_E WAKEUP1_E WAKEUP2_E WAKEUP3_E ATIMER_E RTC_E BOD_E WWDT_E ETH_E USB0_E USB1_E SDMMC_E CAN_E TIM2_E TIM6_E QEI_E TIM14_E RESERVED RESET_E BODRESET_E DPDRESET_E RESERVED

WAKEUP0_E : Edge detect mode for WAKEUP0 event. The corresponding bit in the EDGE register must be 0.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_WAKEU

Edge detect of WAKEUP0 pin. Detect falling edge if bit 0 in the HILO register is 0. Detect rising edge if bit 0 in the HILO register is 1.

End of enumeration elements list.

WAKEUP1_E : Edge/level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_WAKEU

Edge detect of WAKEUP1 pin. Detect falling edge if bit 1 in the HILO register is 0. Detect rising edge if bit 1 in the HILO register is 1.

End of enumeration elements list.

WAKEUP2_E : Edge/level detect mode for WAKEUP2 event. The corresponding bit in the EDGE register must be 0.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_WAKEU

Edge detect of WAKEUP2 pin. Detect falling edge if bit 2 in the HILO register is 0. Detect rising edge if bit 2 in the HILO register is 1.

End of enumeration elements list.

WAKEUP3_E : Edge/level detect mode for WAKEUP3 event. The corresponding bit in the EDGE register must be 0.
bits : 3 - 6 (4 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_WAKEU

Edge detect of WAKEUP3 pin. Detect falling edge if bit 30 in the HILO register is 0. Detect rising edge if bit 3 in the HILO register is 1.

End of enumeration elements list.

ATIMER_E : Edge/level detect mode for alarm timer event. The corresponding bit in the EDGE register must be 0.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_THE_A

Edge detect of the alarm timer interrupt. Detect falling edge if bit 4 in the HILO register is 0. Detect rising edge if bit 4 in the HILO register is 1.

End of enumeration elements list.

RTC_E : Edge/level detect mode for RTC event. The corresponding bit in the EDGE register must be 0.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_THE_R

Edge detect of the RTC interrupt. Detect falling edge if bit 5 in the HILO register is 0. Detect rising edge if bit 5 in the HILO register is 1.

End of enumeration elements list.

BOD_E : Edge/level detect mode for BOD event. The corresponding bit in the EDGE register must be 0.
bits : 6 - 12 (7 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_THE_B

Edge detect of the BOD interrupt. Detect falling edge if bit 6 in the HILO register is 0. Detect rising edge if bit 6 in the HILO register is 1.

End of enumeration elements list.

WWDT_E : Edge/level detect mode for WWDTD event. The corresponding bit in the EDGE register must be 0.
bits : 7 - 14 (8 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_THE_W

Edge detect of the WWDT interrupt. Detect falling edge if bit 7 in the HILO register is 0. Detect rising edge if bit 7 in the HILO register is 1.

End of enumeration elements list.

ETH_E : Edge/level detect mode for ethernet event. The corresponding bit in the EDGE register must be 0.
bits : 8 - 16 (9 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_THE_E

Edge detect of the Ethernet interrupt. Detect falling edge if bit 8 in the HILO register is 0. Detect rising edge if bit 8 in the HILO register is 1.

End of enumeration elements list.

USB0_E : Edge/level detect mode for USB0 event. The corresponding bit in the EDGE register must be 0.
bits : 9 - 18 (10 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_THE_U

Edge detect of the USB0 event. Detect falling edge if bit 9 in the HILO register is 0. Detect rising edge if bit 9 in the HILO register is 1.

End of enumeration elements list.

USB1_E : Edge/level detect mode for USB1 event. The corresponding bit in the EDGE register must be 0.
bits : 10 - 20 (11 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_THE_U

Edge detect of the USB1 interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1.

End of enumeration elements list.

SDMMC_E : Edge/level detect mode for SD/MMC event.The corresponding bit in the EDGE register must be 0.
bits : 11 - 22 (12 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_THE_S

Edge detect of the SD/MMC interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1.

End of enumeration elements list.

CAN_E : Edge/level detect mode for C_CAN event. The corresponding bit in the EDGE register must be 0.
bits : 12 - 24 (13 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_THE_C

Edge detect of the combined C_CAN interrupt. Detect falling edge if bit 12 in the HILO register is 0. Detect rising edge if bit 12 in the HILO register is 1.

End of enumeration elements list.

TIM2_E : Edge/level detect mode for combined timer output 2 event. The corresponding bit in the EDGE register must be 0.
bits : 13 - 26 (14 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_GIMA

Edge detect of GIMA output 25. Detect falling edge if bit 13 in the HILO register is 0. Detect rising edge if bit 13 in the HILO register is 1.

End of enumeration elements list.

TIM6_E : Edge/level detect mode for combined timer output 6 event. The corresponding bit in the EDGE register must be 0.
bits : 14 - 28 (15 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_GIMA

Edge detect of GIMA output 26. Detect falling edge if bit 14 in the HILO register is 0. Detect rising edge if bit 14 in the HILO register is 1.

End of enumeration elements list.

QEI_E : Edge/level detect mode for QEI interrupt signal. The corresponding bit in the EDGE register must be 0.
bits : 15 - 30 (16 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_QEI_I

Edge detect of QEI interrupt. Detect falling edge if bit 15 in the HILO register is 0. Detect rising edge if bit 15 in the HILO register is 1.

End of enumeration elements list.

TIM14_E : Edge/level detect mode for combined timer output 14 event. The corresponding bit in the EDGE register must be 0.
bits : 16 - 32 (17 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_GIMA

Edge detect of GIMA output 27. Detect falling edge if bit 16 in the HILO register is 0. Detect rising edge if bit 16 in the HILO register is 1.

End of enumeration elements list.

RESERVED : Reserved.
bits : 17 - 35 (19 bit)

RESET_E : Edge/level detect mode for Reset. The corresponding bit in the EDGE register must be 0.
bits : 19 - 38 (20 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_THE_R

Edge detect of the reset signal. Detect falling edge if bit 19 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1.

End of enumeration elements list.

BODRESET_E : Edge detect of the BOD reset signal. The corresponding bit in the EDGE register must be 0.
bits : 20 - 40 (21 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_THE_R

Edge detect of the reset signal. Detect falling edge if bit 20 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1.

End of enumeration elements list.

DPDRESET_E : Edge detect of the deep power-down reset signal. The corresponding bit in the EDGE register must be 0.
bits : 21 - 42 (22 bit)

Enumeration: ENUM

0 : LEVEL_DETECT

Level detect.

1 : EDGE_DETECT_OF_THE_R

Edge detect of the reset signal. Detect falling edge if bit 21 in the HILO register is 0. Detect rising edge if bit 21 in the HILO register is 1.

End of enumeration elements list.

RESERVED : Reserved.
bits : 22 - 53 (32 bit)


CLR_EN

Clear event enable register
address_offset : 0xFD8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CLR_EN CLR_EN write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAKEUP0_CLREN WAKEUP1_CLREN WAKEUP2_CLREN WAKEUP3_CLREN ATIMER_CLREN RTC_CLREN BOD_CLREN WWDT_CLREN ETH_CLREN USB0_CLREN USB1_CLREN SDMMC_CLREN CAN_CLREN TIM2_CLREN TIM6_CLREN QEI_CLREN TIM14_CLREN RESERVED RESET_CLREN BODRESET_CLREN DPDRESET_CLREN RESERVED

WAKEUP0_CLREN : Writing a 1 to this bit clears the event enable bit 0 in the ENABLE register.
bits : 0 - 0 (1 bit)

WAKEUP1_CLREN : Writing a 1 to this bit clears the event enable bit 1 in the ENABLE register.
bits : 1 - 2 (2 bit)

WAKEUP2_CLREN : Writing a 1 to this bit clears the event enable bit 2 in the ENABLE register.
bits : 2 - 4 (3 bit)

WAKEUP3_CLREN : Writing a 1 to this bit clears the event enable bit 3 in the ENABLE register.
bits : 3 - 6 (4 bit)

ATIMER_CLREN : Writing a 1 to this bit clears the event enable bit 4 in the ENABLE register.
bits : 4 - 8 (5 bit)

RTC_CLREN : Writing a 1 to this bit clears the event enable bit 5 in the ENABLE register.
bits : 5 - 10 (6 bit)

BOD_CLREN : Writing a 1 to this bit clears the event enable bit 6 in the ENABLE register.
bits : 6 - 12 (7 bit)

WWDT_CLREN : Writing a 1 to this bit clears the event enable bit 7 in the ENABLE register.
bits : 7 - 14 (8 bit)

ETH_CLREN : Writing a 1 to this bit clears the event enable bit 8 in the ENABLE register.
bits : 8 - 16 (9 bit)

USB0_CLREN : Writing a 1 to this bit clears the event enable bit 9 in the ENABLE register.
bits : 9 - 18 (10 bit)

USB1_CLREN : Writing a 1 to this bit clears the event enable bit 10 in the ENABLE register.
bits : 10 - 20 (11 bit)

SDMMC_CLREN : Writing a 1 to this bit clears the event enable bit 11 in the ENABLE register.
bits : 11 - 22 (12 bit)

CAN_CLREN : Writing a 1 to this bit clears the event enable bit 12 in the ENABLE register.
bits : 12 - 24 (13 bit)

TIM2_CLREN : Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register.
bits : 13 - 26 (14 bit)

TIM6_CLREN : Writing a 1 to this bit clears the event enable bit 14 in the ENABLE register.
bits : 14 - 28 (15 bit)

QEI_CLREN : Writing a 1 to this bit clears the event enable bit 15 in the ENABLE register.
bits : 15 - 30 (16 bit)

TIM14_CLREN : Writing a 1 to this bit clears the event enable bit 16 in the ENABLE register.
bits : 16 - 32 (17 bit)

RESERVED : Reserved.
bits : 17 - 35 (19 bit)

RESET_CLREN : Writing a 1 to this bit clears the event enable bit 19 in the ENABLE register.
bits : 19 - 38 (20 bit)

BODRESET_CLREN : Writing a 1 to this bit clears the event enable bit 20 in the ENABLE register.
bits : 20 - 40 (21 bit)

DPDRESET_CLREN : Writing a 1 to this bit clears the event enable bit 21 in the ENABLE register.
bits : 21 - 42 (22 bit)

RESERVED : Reserved.
bits : 22 - 53 (32 bit)


SET_EN

Set event enable register
address_offset : 0xFDC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SET_EN SET_EN write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAKEUP0_SETEN WAKEUP1_SETEN WAKEUP2_SETEN WAKEUP3_SETEN ATIMER_SETEN RTC_SETEN BOD_SETEN WWDT_SETEN ETH_SETEN USB0_SETEN USB1_SETEN SDMMC_SETEN CAN_SETEN TIM2_SETEN TIM6_SETEN QEI_SETEN TIM14_SETEN RESERVED RESET_SETEN BODRESET_SETEN DPDRESET_SETEN RESERVED

WAKEUP0_SETEN : Writing a 1 to this bit sets the event enable bit 0 in the ENABLE register.
bits : 0 - 0 (1 bit)

WAKEUP1_SETEN : Writing a 1 to this bit sets the event enable bit 1 in the ENABLE register.
bits : 1 - 2 (2 bit)

WAKEUP2_SETEN : Writing a 1 to this bit sets the event enable bit 2 in the ENABLE register.
bits : 2 - 4 (3 bit)

WAKEUP3_SETEN : Writing a 1 to this bit sets the event enable bit 3 in the ENABLE register.
bits : 3 - 6 (4 bit)

ATIMER_SETEN : Writing a 1 to this bit sets the event enable bit 4 in the ENABLE register.
bits : 4 - 8 (5 bit)

RTC_SETEN : Writing a 1 to this bit sets the event enable bit 5 in the ENABLE register.
bits : 5 - 10 (6 bit)

BOD_SETEN : Writing a 1 to this bit sets the event enable bit 6 in the ENABLE register.
bits : 6 - 12 (7 bit)

WWDT_SETEN : Writing a 1 to this bit sets the event enable bit 7 in the ENABLE register.
bits : 7 - 14 (8 bit)

ETH_SETEN : Writing a 1 to this bit sets the event enable bit 8 in the ENABLE register.
bits : 8 - 16 (9 bit)

USB0_SETEN : Writing a 1 to this bit sets the event enable bit 9 in the ENABLE register.
bits : 9 - 18 (10 bit)

USB1_SETEN : Writing a 1 to this bit sets the event enable bit 10 in the ENABLE register.
bits : 10 - 20 (11 bit)

SDMMC_SETEN : Writing a 1 to this bit sets the event enable bit 11 in the ENABLE register.
bits : 11 - 22 (12 bit)

CAN_SETEN : Writing a 1 to this bit sets the event enable bit 12 in the ENABLE register.
bits : 12 - 24 (13 bit)

TIM2_SETEN : Writing a 1 to this bit sets the event enable bit 13 in the ENABLE register.
bits : 13 - 26 (14 bit)

TIM6_SETEN : Writing a 1 to this bit sets the event enable bit 14 in the ENABLE register.
bits : 14 - 28 (15 bit)

QEI_SETEN : Writing a 1 to this bit sets the event enable bit 15 in the ENABLE register.
bits : 15 - 30 (16 bit)

TIM14_SETEN : Writing a 1 to this bit sets the event enable bit 16 in the ENABLE register.
bits : 16 - 32 (17 bit)

RESERVED : Reserved.
bits : 17 - 35 (19 bit)

RESET_SETEN : Writing a 1 to this bit sets the event enable bit 19 in the ENABLE register.
bits : 19 - 38 (20 bit)

BODRESET_SETEN : Writing a 1 to this bit sets the event enable bit 20 in the ENABLE register.
bits : 20 - 40 (21 bit)

DPDRESET_SETEN : Writing a 1 to this bit sets the event enable bit 21 in the ENABLE register.
bits : 21 - 42 (22 bit)

RESERVED : Reserved.
bits : 22 - 53 (32 bit)


STATUS

Event Status register
address_offset : 0xFE0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAKEUP0_ST WAKEUP1_ST WAKEUP2_ST WAKEUP3_ST ATIMER_ST RTC_ST BOD_ST WWDT_ST ETH_ST USB0_ST USB1_ST SDMMC_ST CAN_ST TIM2_ST TIM6_ST QEI_ST TIM14_ST RESERVED RESET_ST BODRESET_ST DPDRESET_ST RESERVED

WAKEUP0_ST : A 1 in this bit shows that the WAKEUP0 event has been raised.
bits : 0 - 0 (1 bit)

WAKEUP1_ST : A 1 in this bit shows that the WAKEUP1 event has been raised.
bits : 1 - 2 (2 bit)

WAKEUP2_ST : A 1 in this bit shows that the WAKEUP2 event has been raised.
bits : 2 - 4 (3 bit)

WAKEUP3_ST : A 1 in this bit shows that the WAKEUP3 event has been raised.
bits : 3 - 6 (4 bit)

ATIMER_ST : A 1 in this bit shows that the ATIMER event has been raised.
bits : 4 - 8 (5 bit)

RTC_ST : A 1 in this bit shows that the RTC event has been raised.
bits : 5 - 10 (6 bit)

BOD_ST : A 1 in this bit shows that the BOD event has been raised.
bits : 6 - 12 (7 bit)

WWDT_ST : A 1 in this bit shows that the WWDT event has been raised.
bits : 7 - 14 (8 bit)

ETH_ST : A 1 in this bit shows that the ETHERNET event has been raised.
bits : 8 - 16 (9 bit)

USB0_ST : A 1 in this bit shows that the USB0 event has been raised.
bits : 9 - 18 (10 bit)

USB1_ST : A 1 in this bit shows that the USB1 event has been raised.
bits : 10 - 20 (11 bit)

SDMMC_ST : A 1 in this bit indicates that the SDMMC event has been raised.
bits : 11 - 22 (12 bit)

CAN_ST : A 1 in this bit shows that the C_CAN event has been raised.
bits : 12 - 24 (13 bit)

TIM2_ST : A 1 in this bit shows that the combined timer 2 output event has been raised.
bits : 13 - 26 (14 bit)

TIM6_ST : A 1 in this bit shows that the combined timer 6 output event has been raised.
bits : 14 - 28 (15 bit)

QEI_ST : A 1 in this bit shows that the QEI event has been raised.
bits : 15 - 30 (16 bit)

TIM14_ST : A 1 in this bit shows that the combined timer 14 output event has been raised.
bits : 16 - 32 (17 bit)

RESERVED : Reserved.
bits : 17 - 35 (19 bit)

RESET_ST : A 1 in this bit shows that the reset event has been raised.
bits : 19 - 38 (20 bit)

BODRESET_ST : A 1 in this bit indicates that the reset event has been raised.
bits : 20 - 40 (21 bit)

DPDRESET_ST : A 1 in this bit indicates that the reset event has been raised.
bits : 21 - 42 (22 bit)

RESERVED : Reserved.
bits : 22 - 53 (32 bit)


ENABLE

Event Enable register
address_offset : 0xFE4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENABLE ENABLE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAKEUP0_EN WAKEUP1_EN WAKEUP2_EN WAKEUP3_EN ATIMER_EN RTC_EN BOD_EN WWDT_EN ETH_EN USB0_EN USB1_EN SDMMC_EN CAN_EN TIM2_EN TIM6_EN QEI_EN TIM14_EN RESERVED RESET_EN BODRESET_EN DPDRESET_EN RESERVED

WAKEUP0_EN : A 1 in this bit shows that the WAKEUP0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 0 - 0 (1 bit)

WAKEUP1_EN : A 1 in this bit shows that the WAKEUP1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 1 - 2 (2 bit)

WAKEUP2_EN : A 1 in this bit shows that the WAKEUP2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 2 - 4 (3 bit)

WAKEUP3_EN : A 1 in this bit shows that the WAKEUP3 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 3 - 6 (4 bit)

ATIMER_EN : A 1 in this bit shows that the ATIMER event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 4 - 8 (5 bit)

RTC_EN : A 1 in this bit shows that the RTC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 5 - 10 (6 bit)

BOD_EN : A 1 in this bit shows that the BOD event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 6 - 12 (7 bit)

WWDT_EN : A 1 in this bit shows that the WWDT event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 7 - 14 (8 bit)

ETH_EN : A 1 in this bit shows that the ETHERNET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 8 - 16 (9 bit)

USB0_EN : A 1 in this bit shows that the USB0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 9 - 18 (10 bit)

USB1_EN : A 1 in this bit shows that the USB1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 10 - 20 (11 bit)

SDMMC_EN : A 1 in this bit indicates that the SDMMC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 11 - 22 (12 bit)

CAN_EN : A 1 in this bit shows that the CAN event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 12 - 24 (13 bit)

TIM2_EN : A 1 in this bit shows that the TIM2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 13 - 26 (14 bit)

TIM6_EN : A 1 in this bit shows that the TIM6 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 14 - 28 (15 bit)

QEI_EN : A 1 in this bit shows that the QEI event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 15 - 30 (16 bit)

TIM14_EN : A 1 in this bit shows that the TIM14 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 16 - 32 (17 bit)

RESERVED : Reserved
bits : 17 - 35 (19 bit)

RESET_EN : A 1 in this bit shows that the RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 19 - 38 (20 bit)

BODRESET_EN : A 1 in this bit indicates that the BOD RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 20 - 40 (21 bit)

DPDRESET_EN : A 1 in this bit indicates that the deep power-down RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
bits : 21 - 42 (22 bit)

RESERVED : Reserved.
bits : 22 - 53 (32 bit)


CLR_STAT

Clear event status register
address_offset : 0xFE8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CLR_STAT CLR_STAT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAKEUP0_CLRST WAKEUP1_CLRST WAKEUP2_CLRST WAKEUP3_CLRST ATIMER_CLRST RTC_CLRST BOD_CLRST WWDT_CLRST ETH_CLRST USB0_CLRST USB1_CLRST SDMMC_CLRST CAN_CLRST TIM2_CLRST TIM6_CLRST QEI_CLRST TIM14_CLRST RESERVED RESET_CLRST BODRESET_CLRST DPDRESET_CLRST RESERVED

WAKEUP0_CLRST : Writing a 1 to this bit clears the STATUS event bit 0 in the STATUS register.
bits : 0 - 0 (1 bit)

WAKEUP1_CLRST : Writing a 1 to this bit clears the STATUS event bit 1 in the STATUS register.
bits : 1 - 2 (2 bit)

WAKEUP2_CLRST : Writing a 1 to this bit clears the STATUS event bit 2 in the STATUS register.
bits : 2 - 4 (3 bit)

WAKEUP3_CLRST : Writing a 1 to this bit clears the STATUS event bit 3 in the STATUS register.
bits : 3 - 6 (4 bit)

ATIMER_CLRST : Writing a 1 to this bit clears the STATUS event bit 4 in the STATUS register.
bits : 4 - 8 (5 bit)

RTC_CLRST : Writing a 1 to this bit clears the STATUS event bit 5 in the STATUS register.
bits : 5 - 10 (6 bit)

BOD_CLRST : Writing a 1 to this bit clears the STATUS event bit 6 in the STATUS register.
bits : 6 - 12 (7 bit)

WWDT_CLRST : Writing a 1 to this bit clears the STATUS event bit 7 in the STATUS register.
bits : 7 - 14 (8 bit)

ETH_CLRST : Writing a 1 to this bit clears the STATUS event bit 8 in the STATUS register.
bits : 8 - 16 (9 bit)

USB0_CLRST : Writing a 1 to this bit clears the STATUS event bit 9 in the STATUS register.
bits : 9 - 18 (10 bit)

USB1_CLRST : Writing a 1 to this bit clears the STATUS event bit 10 in the STATUS register.
bits : 10 - 20 (11 bit)

SDMMC_CLRST : Writing a 1 to this bit clears the STATUS event bit 11 in the STATUS register.
bits : 11 - 22 (12 bit)

CAN_CLRST : Writing a 1 to this bit clears the STATUS event bit 12 in the STATUS register.
bits : 12 - 24 (13 bit)

TIM2_CLRST : Writing a 1 to this bit clears the STATUS event bit 13 in the STATUS register.
bits : 13 - 26 (14 bit)

TIM6_CLRST : Writing a 1 to this bit clears the STATUS event bit 14 in the STATUS register.
bits : 14 - 28 (15 bit)

QEI_CLRST : Writing a 1 to this bit clears the STATUS event bit 15 in the STATUS register.
bits : 15 - 30 (16 bit)

TIM14_CLRST : Writing a 1 to this bit clears the STATUS event bit 16 in the STATUS register.
bits : 16 - 32 (17 bit)

RESERVED : Reserved.
bits : 17 - 35 (19 bit)

RESET_CLRST : Writing a 1 to this bit clears the STATUS event bit 19 in the STATUS register.
bits : 19 - 38 (20 bit)

BODRESET_CLRST : Writing a 1 to this bit clears the STATUS event bit 20 in the STATUS register.
bits : 20 - 40 (21 bit)

DPDRESET_CLRST : Writing a 1 to this bit clears the STATUS event bit 21 in the STATUS register.
bits : 21 - 42 (22 bit)

RESERVED : Reserved.
bits : 22 - 53 (32 bit)


SET_STAT

Set event status register
address_offset : 0xFEC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SET_STAT SET_STAT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAKEUP0_SETST WAKEUP1_SETST WAKEUP2_SETST WAKEUP3_SETST ATIMER_SETST RTC_SETST BOD_SETST WWDT_SETST ETH_SETST USB0_SETST USB1_SETST SDMMC_SETST CAN_SETST TIM2_SETST TIM6_SETST QEI_SETST TIM14_SETST RESERVED RESET_SETST BODRESET_SETST DPDRESET_SETST RESERVED

WAKEUP0_SETST : Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS register.
bits : 0 - 0 (1 bit)

WAKEUP1_SETST : Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS register.
bits : 1 - 2 (2 bit)

WAKEUP2_SETST : Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS register.
bits : 2 - 4 (3 bit)

WAKEUP3_SETST : Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS register.
bits : 3 - 6 (4 bit)

ATIMER_SETST : Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS register.
bits : 4 - 8 (5 bit)

RTC_SETST : Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS register.
bits : 5 - 10 (6 bit)

BOD_SETST : Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS register.
bits : 6 - 12 (7 bit)

WWDT_SETST : Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register.
bits : 7 - 14 (8 bit)

ETH_SETST : Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS register.
bits : 8 - 16 (9 bit)

USB0_SETST : Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS register.
bits : 9 - 18 (10 bit)

USB1_SETST : Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS register.
bits : 10 - 20 (11 bit)

SDMMC_SETST : Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS register.
bits : 11 - 22 (12 bit)

CAN_SETST : Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS register.
bits : 12 - 24 (13 bit)

TIM2_SETST : Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register.
bits : 13 - 26 (14 bit)

TIM6_SETST : Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register.
bits : 14 - 28 (15 bit)

QEI_SETST : Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS register.
bits : 15 - 30 (16 bit)

TIM14_SETST : Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS register.
bits : 16 - 32 (17 bit)

RESERVED : Reserved.
bits : 17 - 35 (19 bit)

RESET_SETST : Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS register.
bits : 19 - 38 (20 bit)

BODRESET_SETST : Writing a 1 to this bit sets the STATUS event bit 20 in the STATUS register.
bits : 20 - 40 (21 bit)

DPDRESET_SETST : Writing a 1 to this bit sets the STATUS event bit 21 in the STATUS register.
bits : 21 - 42 (22 bit)

RESERVED : Reserved.
bits : 22 - 53 (32 bit)



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