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I2C

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected

Registers

CONSET

SCLH

MASK3

SCLL

CONCLR

MMCTRL

DATA_BUFFER

STAT

ADR1

MASK0

ADR2

DAT

ADR3

MASK1

ADR0

MASK2


CONSET

I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSET CONSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED AA SI STO STA I2EN RESERVED

RESERVED : Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 0 - 1 (2 bit)

AA : Assert acknowledge flag.
bits : 2 - 4 (3 bit)

SI : I2C interrupt flag.
bits : 3 - 6 (4 bit)

STO : STOP flag.
bits : 4 - 8 (5 bit)

STA : START flag.
bits : 5 - 10 (6 bit)

I2EN : I2C interface enable.
bits : 6 - 12 (7 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 7 - 38 (32 bit)


SCLH

SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCLH SCLH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCLH RESERVED

SCLH : Count for SCL HIGH time period selection.
bits : 0 - 15 (16 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 16 - 47 (32 bit)


MASK3

I2C Slave address mask register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASK3 MASK3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED MASK RESERVED

RESERVED : Reserved. User software should not write ones to reserved bits. This bit reads always back as 0.
bits : 0 - 0 (1 bit)

MASK : Mask bits.
bits : 1 - 8 (8 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)


SCLL

SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCLL SCLL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCLL RESERVED

SCLL : Count for SCL low time period selection.
bits : 0 - 15 (16 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 16 - 47 (32 bit)


CONCLR

I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.
address_offset : 0x18 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CONCLR CONCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED AAC SIC RESERVED STAC I2ENC RESERVED RESERVED

RESERVED : Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 0 - 1 (2 bit)

AAC : Assert acknowledge Clear bit.
bits : 2 - 4 (3 bit)

SIC : I2C interrupt Clear bit.
bits : 3 - 6 (4 bit)

RESERVED : Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 4 - 8 (5 bit)

STAC : START flag Clear bit.
bits : 5 - 10 (6 bit)

I2ENC : I2C interface Disable bit.
bits : 6 - 12 (7 bit)

RESERVED : Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 7 - 14 (8 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)


MMCTRL

Monitor mode control register.
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMCTRL MMCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MM_ENA ENA_SCL MATCH_ALL RESERVED

MM_ENA : Monitor mode enable.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : MONITOR_MODE_DISABLE

Monitor mode disabled.

1 : THE_I_2C_MODULE_WILL

The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line.

End of enumeration elements list.

ENA_SCL : SCL output enable.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

0 : WHEN_THIS_BIT_IS_CLE

When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line.

1 : WHEN_THIS_BIT_IS_SET

When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]

End of enumeration elements list.

MATCH_ALL : Select interrupt register match.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

0 : WHEN_THIS_BIT_IS_CLE

When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned.

1 : WHEN_THIS_BIT_IS_SET

When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus.

End of enumeration elements list.

RESERVED : Reserved. The value read from reserved bits is not defined.
bits : 3 - 34 (32 bit)


DATA_BUFFER

Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DATA_BUFFER DATA_BUFFER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data RESERVED

Data : This register holds contents of the 8 MSBs of the DAT shift register.
bits : 0 - 7 (8 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)


STAT

I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED Status RESERVED

RESERVED : These bits are unused and are always 0.
bits : 0 - 2 (3 bit)

Status : These bits give the actual status information about the I 2C interface.
bits : 3 - 10 (8 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)


ADR1

I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADR1 ADR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GC Address RESERVED

GC : General Call enable bit.
bits : 0 - 0 (1 bit)

Address : The I2C device address for slave mode.
bits : 1 - 8 (8 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)


MASK0

I2C Slave address mask register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASK0 MASK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED MASK RESERVED

RESERVED : Reserved. User software should not write ones to reserved bits. This bit reads always back as 0.
bits : 0 - 0 (1 bit)

MASK : Mask bits.
bits : 1 - 8 (8 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)


ADR2

I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADR2 ADR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GC Address RESERVED

GC : General Call enable bit.
bits : 0 - 0 (1 bit)

Address : The I2C device address for slave mode.
bits : 1 - 8 (8 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)


DAT

I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAT DAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data RESERVED

Data : This register holds data values that have been received or are to be transmitted.
bits : 0 - 7 (8 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)


ADR3

I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADR3 ADR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GC Address RESERVED

GC : General Call enable bit.
bits : 0 - 0 (1 bit)

Address : The I2C device address for slave mode.
bits : 1 - 8 (8 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)


MASK1

I2C Slave address mask register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASK1 MASK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED MASK RESERVED

RESERVED : Reserved. User software should not write ones to reserved bits. This bit reads always back as 0.
bits : 0 - 0 (1 bit)

MASK : Mask bits.
bits : 1 - 8 (8 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)


ADR0

I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADR0 ADR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GC Address RESERVED

GC : General Call enable bit.
bits : 0 - 0 (1 bit)

Address : The I2C device address for slave mode.
bits : 1 - 8 (8 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)


MASK2

I2C Slave address mask register
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASK2 MASK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED MASK RESERVED

RESERVED : Reserved. User software should not write ones to reserved bits. This bit reads always back as 0.
bits : 0 - 0 (1 bit)

MASK : Mask bits.
bits : 1 - 8 (8 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)



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