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QEI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected

Registers

CON

MAXPOS

CMPOS0

CMPOS1

CMPOS2

INXCNT

INXCMP0

LOAD

TIME

VEL

CAP

VELCOMP

FILTERPHA

STAT

FILTERPHB

FILTERINX

WINDOW

INXCMP1

INXCMP2

CONF

POS

IEC

IES

INTSTAT

IE

CLR

SET


CON

Control register
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CON CON write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESP RESPI RESV RESI RESERVED

RESP : Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared.
bits : 0 - 0 (1 bit)

RESPI : Reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs. Autoclears when the position counter is cleared.
bits : 1 - 2 (2 bit)

RESV : Reset velocity. When set = 1, resets the velocity counter to all zeros and reloads the velocity timer. Autoclears when the velocity counter is cleared.
bits : 2 - 4 (3 bit)

RESI : Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared.
bits : 3 - 6 (4 bit)

RESERVED : reserved
bits : 4 - 35 (32 bit)


MAXPOS

Maximum position register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAXPOS MAXPOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAXPOS

MAXPOS : Maximum position value.
bits : 0 - 31 (32 bit)


CMPOS0

position compare register 0
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPOS0 CMPOS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCMP0

PCMP0 : Position compare value 0.
bits : 0 - 31 (32 bit)


CMPOS1

position compare register 1
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPOS1 CMPOS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCMP1

PCMP1 : Position compare value 1.
bits : 0 - 31 (32 bit)


CMPOS2

position compare register 2
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPOS2 CMPOS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCMP2

PCMP2 : Position compare value 2.
bits : 0 - 31 (32 bit)


INXCNT

Index count register
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INXCNT INXCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENCPOS

ENCPOS : Current encoder position value.
bits : 0 - 31 (32 bit)


INXCMP0

Index compare register 0
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INXCMP0 INXCMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICMP0

ICMP0 : Index compare value.
bits : 0 - 31 (32 bit)


LOAD

Velocity timer reload register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOAD LOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VELLOAD

VELLOAD : Current velocity timer load value.
bits : 0 - 31 (32 bit)


TIME

Velocity timer register
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TIME TIME read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VELVAL

VELVAL : Current velocity timer value.
bits : 0 - 31 (32 bit)


VEL

Velocity counter register
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VEL VEL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VELPC

VELPC : Current velocity pulse count.
bits : 0 - 31 (32 bit)


CAP

Velocity capture register
address_offset : 0x34 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAP CAP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VELCAP

VELCAP : Velocity capture value.
bits : 0 - 31 (32 bit)


VELCOMP

Velocity compare register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VELCOMP VELCOMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VELCMP

VELCMP : Velocity compare value.
bits : 0 - 31 (32 bit)


FILTERPHA

Digital filter register on input phase A (QEI_A)
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FILTERPHA FILTERPHA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTA

FILTA : Digital filter sampling delay
bits : 0 - 31 (32 bit)


STAT

Encoder status register
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIR RESERVED

DIR : Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 516.
bits : 0 - 0 (1 bit)

RESERVED : reserved
bits : 1 - 32 (32 bit)


FILTERPHB

Digital filter register on input phase B (QEI_B)
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FILTERPHB FILTERPHB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTB

FILTB : Digital filter sampling delay
bits : 0 - 31 (32 bit)


FILTERINX

Digital filter register on input index (QEI_IDX)
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FILTERINX FILTERINX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FITLINX

FITLINX : Digital filter sampling delay
bits : 0 - 31 (32 bit)


WINDOW

Index acceptance window register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WINDOW WINDOW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WINDOW

WINDOW : Index acceptance window width
bits : 0 - 31 (32 bit)


INXCMP1

Index compare register 1
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INXCMP1 INXCMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICMP1

ICMP1 : Index compare value 1.
bits : 0 - 31 (32 bit)


INXCMP2

Index compare register 2
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INXCMP2 INXCMP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICMP2

ICMP2 : Index compare value 2.
bits : 0 - 31 (32 bit)


CONF

Configuration register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONF CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIRINV SIGMODE CAPMODE INVINX CRESPI RESERVED INXGATE RESERVED

DIRINV : Direction invert. When = 1, complements the DIR bit.
bits : 0 - 0 (1 bit)

SIGMODE : Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA functions as the direction signal and PhB functions as the clock signal.
bits : 1 - 2 (2 bit)

CAPMODE : Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range.
bits : 2 - 4 (3 bit)

INVINX : Invert Index. When set, inverts the sense of the index input.
bits : 3 - 6 (4 bit)

CRESPI : Continuously reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs at the next position increase (recalibration). Auto-clears when the position counter is cleared.
bits : 4 - 8 (5 bit)

RESERVED : Reserved
bits : 5 - 20 (16 bit)

INXGATE : Index gating configuration: when INXGATE(19)=1, pass the index when Pha=0 and Phb=0, else block. when INXGATE(18)=1, pass the index when Pha=0 and Phb=1, else block. when INXGATE(17)=1, pass the index when Pha=1 and Phb=1, else block. when INXGATE(16)=1, pass the index when Pha=1 and Phb=0, else block.
bits : 16 - 35 (20 bit)

RESERVED : reserved
bits : 20 - 51 (32 bit)


POS

Position register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

POS POS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POS

POS : Current position value.
bits : 0 - 31 (32 bit)


IEC

Interrupt enable clear register
address_offset : 0xFD8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IEC IEC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INX_EN TIM_EN VELC_EN DIR_EN ERR_EN ENCLK_EN POS0_Int POS1_Int POS2_Int REV_Int POS0REV_Int POS1REV_Int POS2REV_Int REV1_Int REV2_Int MAXPOS_Int RESERVED

INX_EN : Indicates that an index pulse was detected.
bits : 0 - 0 (1 bit)

TIM_EN : Indicates that a velocity timer overflow occurred
bits : 1 - 2 (2 bit)

VELC_EN : Indicates that captured velocity is less than compare velocity.
bits : 2 - 4 (3 bit)

DIR_EN : Indicates that a change of direction was detected.
bits : 3 - 6 (4 bit)

ERR_EN : Indicates that an encoder phase error was detected.
bits : 4 - 8 (5 bit)

ENCLK_EN : Indicates that and encoder clock pulse was detected.
bits : 5 - 10 (6 bit)

POS0_Int : Indicates that the position 0 compare value is equal to the current position.
bits : 6 - 12 (7 bit)

POS1_Int : Indicates that the position 1compare value is equal to the current position.
bits : 7 - 14 (8 bit)

POS2_Int : Indicates that the position 2 compare value is equal to the current position.
bits : 8 - 16 (9 bit)

REV_Int : Indicates that the index compare value is equal to the current index count.
bits : 9 - 18 (10 bit)

POS0REV_Int : Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set.
bits : 10 - 20 (11 bit)

POS1REV_Int : Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set.
bits : 11 - 22 (12 bit)

POS2REV_Int : Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set.
bits : 12 - 24 (13 bit)

REV1_Int : Indicates that the index 1 compare value is equal to the current index count.
bits : 13 - 26 (14 bit)

REV2_Int : Indicates that the index 2 compare value is equal to the current index count.
bits : 14 - 28 (15 bit)

MAXPOS_Int : Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.
bits : 15 - 30 (16 bit)

RESERVED : Reserved
bits : 16 - 47 (32 bit)


IES

Interrupt enable set register
address_offset : 0xFDC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IES IES write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INX_EN TIM_EN VELC_EN DIR_EN ERR_EN ENCLK_EN POS0_Int POS1_Int POS2_Int REV_Int POS0REV_Int POS1REV_Int POS2REV_Int REV1_Int REV2_Int MAXPOS_Int RESERVED

INX_EN : Indicates that an index pulse was detected.
bits : 0 - 0 (1 bit)

TIM_EN : Indicates that a velocity timer overflow occurred
bits : 1 - 2 (2 bit)

VELC_EN : Indicates that captured velocity is less than compare velocity.
bits : 2 - 4 (3 bit)

DIR_EN : Indicates that a change of direction was detected.
bits : 3 - 6 (4 bit)

ERR_EN : Indicates that an encoder phase error was detected.
bits : 4 - 8 (5 bit)

ENCLK_EN : Indicates that and encoder clock pulse was detected.
bits : 5 - 10 (6 bit)

POS0_Int : Indicates that the position 0 compare value is equal to the current position.
bits : 6 - 12 (7 bit)

POS1_Int : Indicates that the position 1compare value is equal to the current position.
bits : 7 - 14 (8 bit)

POS2_Int : Indicates that the position 2 compare value is equal to the current position.
bits : 8 - 16 (9 bit)

REV_Int : Indicates that the index compare value is equal to the current index count.
bits : 9 - 18 (10 bit)

POS0REV_Int : Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set.
bits : 10 - 20 (11 bit)

POS1REV_Int : Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set.
bits : 11 - 22 (12 bit)

POS2REV_Int : Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set.
bits : 12 - 24 (13 bit)

REV1_Int : Indicates that the index 1 compare value is equal to the current index count.
bits : 13 - 26 (14 bit)

REV2_Int : Indicates that the index 2 compare value is equal to the current index count.
bits : 14 - 28 (15 bit)

MAXPOS_Int : Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.
bits : 15 - 30 (16 bit)

RESERVED : Reserved
bits : 16 - 47 (32 bit)


INTSTAT

Interrupt status register
address_offset : 0xFE0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTAT INTSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INX_Int TIM_Int VELC_Int DIR_Int ERR_Int ENCLK_Int POS0_Int POS1_Int POS2_Int REV_Int POS0REV_Int POS1REV_Int POS2REV_Int REV1_Int REV2_Int MAXPOS_Int RESERVED

INX_Int : Indicates that an index pulse was detected.
bits : 0 - 0 (1 bit)

TIM_Int : Indicates that a velocity timer overflow occurred
bits : 1 - 2 (2 bit)

VELC_Int : Indicates that captured velocity is less than compare velocity.
bits : 2 - 4 (3 bit)

DIR_Int : Indicates that a change of direction was detected.
bits : 3 - 6 (4 bit)

ERR_Int : Indicates that an encoder phase error was detected.
bits : 4 - 8 (5 bit)

ENCLK_Int : Indicates that and encoder clock pulse was detected.
bits : 5 - 10 (6 bit)

POS0_Int : Indicates that the position 0 compare value is equal to the current position.
bits : 6 - 12 (7 bit)

POS1_Int : Indicates that the position 1compare value is equal to the current position.
bits : 7 - 14 (8 bit)

POS2_Int : Indicates that the position 2 compare value is equal to the current position.
bits : 8 - 16 (9 bit)

REV_Int : Indicates that the index compare value is equal to the current index count.
bits : 9 - 18 (10 bit)

POS0REV_Int : Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set.
bits : 10 - 20 (11 bit)

POS1REV_Int : Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set.
bits : 11 - 22 (12 bit)

POS2REV_Int : Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set.
bits : 12 - 24 (13 bit)

REV1_Int : Indicates that the index 1 compare value is equal to the current index count.
bits : 13 - 26 (14 bit)

REV2_Int : Indicates that the index 2 compare value is equal to the current index count.
bits : 14 - 28 (15 bit)

MAXPOS_Int : Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.
bits : 15 - 30 (16 bit)

RESERVED : Reserved
bits : 16 - 47 (32 bit)


IE

Interrupt enable register
address_offset : 0xFE4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IE IE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INX_Int TIM_Int VELC_Int DIR_Int ERR_Int ENCLK_Int POS0_Int POS1_Int POS2_Int REV_Int POS0REV_Int POS1REV_Int POS2REV_Int REV1_Int REV2_Int MAXPOS_Int RESERVED

INX_Int : Indicates that an index pulse was detected.
bits : 0 - 0 (1 bit)

TIM_Int : Indicates that a velocity timer overflow occurred
bits : 1 - 2 (2 bit)

VELC_Int : Indicates that captured velocity is less than compare velocity.
bits : 2 - 4 (3 bit)

DIR_Int : Indicates that a change of direction was detected.
bits : 3 - 6 (4 bit)

ERR_Int : Indicates that an encoder phase error was detected.
bits : 4 - 8 (5 bit)

ENCLK_Int : Indicates that and encoder clock pulse was detected.
bits : 5 - 10 (6 bit)

POS0_Int : Indicates that the position 0 compare value is equal to the current position.
bits : 6 - 12 (7 bit)

POS1_Int : Indicates that the position 1compare value is equal to the current position.
bits : 7 - 14 (8 bit)

POS2_Int : Indicates that the position 2 compare value is equal to the current position.
bits : 8 - 16 (9 bit)

REV_Int : Indicates that the index compare value is equal to the current index count.
bits : 9 - 18 (10 bit)

POS0REV_Int : Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set.
bits : 10 - 20 (11 bit)

POS1REV_Int : Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set.
bits : 11 - 22 (12 bit)

POS2REV_Int : Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set.
bits : 12 - 24 (13 bit)

REV1_Int : Indicates that the index 1 compare value is equal to the current index count.
bits : 13 - 26 (14 bit)

REV2_Int : Indicates that the index 2 compare value is equal to the current index count.
bits : 14 - 28 (15 bit)

MAXPOS_Int : Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.
bits : 15 - 30 (16 bit)

RESERVED : Reserved
bits : 16 - 47 (32 bit)


CLR

Interrupt status clear register
address_offset : 0xFE8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CLR CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INX_Int TIM_Int VELC_Int DIR_Int ERR_Int ENCLK_Int POS0_Int POS1_Int POS2_Int REV_Int POS0REV_Int POS1REV_Int REV1_Int REV2_Int MAXPOS_Int RESERVED

INX_Int : Indicates that an index pulse was detected.
bits : 0 - 0 (1 bit)

TIM_Int : Indicates that a velocity timer overflow occurred
bits : 1 - 2 (2 bit)

VELC_Int : Indicates that captured velocity is less than compare velocity.
bits : 2 - 4 (3 bit)

DIR_Int : Indicates that a change of direction was detected.
bits : 3 - 6 (4 bit)

ERR_Int : Indicates that an encoder phase error was detected.
bits : 4 - 8 (5 bit)

ENCLK_Int : Indicates that and encoder clock pulse was detected.
bits : 5 - 10 (6 bit)

POS0_Int : Indicates that the position 0 compare value is equal to the current position.
bits : 6 - 12 (7 bit)

POS1_Int : Indicates that the position 1compare value is equal to the current position.
bits : 7 - 14 (8 bit)

POS2_Int : Indicates that the position 2 compare value is equal to the current position.
bits : 8 - 16 (9 bit)

REV_Int : Indicates that the index compare value is equal to the current index count.
bits : 9 - 18 (10 bit)

POS0REV_Int : Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set.
bits : 10 - 20 (11 bit)

POS1REV_Int : Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set.
bits : 11 - 22 (12 bit)

REV1_Int : Indicates that the index 1 compare value is equal to the current index count.
bits : 13 - 26 (14 bit)

REV2_Int : Indicates that the index 2 compare value is equal to the current index count.
bits : 14 - 28 (15 bit)

MAXPOS_Int : Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.
bits : 15 - 30 (16 bit)

RESERVED : Reserved
bits : 16 - 47 (32 bit)


SET

Interrupt status set register
address_offset : 0xFEC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SET SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INX_Int TIM_Int VELC_Int DIR_Int ERR_Int ENCLK_Int POS0_Int POS1_Int POS2_Int REV_Int POS0REV_Int POS1REV_Int POS2REV_Int REV1_Int REV2_Int MAXPOS_Int RESERVED

INX_Int : Indicates that an index pulse was detected.
bits : 0 - 0 (1 bit)

TIM_Int : Indicates that a velocity timer overflow occurred
bits : 1 - 2 (2 bit)

VELC_Int : Indicates that captured velocity is less than compare velocity.
bits : 2 - 4 (3 bit)

DIR_Int : Indicates that a change of direction was detected.
bits : 3 - 6 (4 bit)

ERR_Int : Indicates that an encoder phase error was detected.
bits : 4 - 8 (5 bit)

ENCLK_Int : Indicates that and encoder clock pulse was detected.
bits : 5 - 10 (6 bit)

POS0_Int : Indicates that the position 0 compare value is equal to the current position.
bits : 6 - 12 (7 bit)

POS1_Int : Indicates that the position 1compare value is equal to the current position.
bits : 7 - 14 (8 bit)

POS2_Int : Indicates that the position 2 compare value is equal to the current position.
bits : 8 - 16 (9 bit)

REV_Int : Indicates that the index compare value is equal to the current index count.
bits : 9 - 18 (10 bit)

POS0REV_Int : Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set.
bits : 10 - 20 (11 bit)

POS1REV_Int : Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set.
bits : 11 - 22 (12 bit)

POS2REV_Int : Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set.
bits : 12 - 24 (13 bit)

REV1_Int : Indicates that the index 1 compare value is equal to the current index count.
bits : 13 - 26 (14 bit)

REV2_Int : Indicates that the index 2 compare value is equal to the current index count.
bits : 14 - 28 (15 bit)

MAXPOS_Int : Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.
bits : 15 - 30 (16 bit)

RESERVED : Reserved
bits : 16 - 47 (32 bit)



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