CTRL

CFG2

CTLSTAT2

XFERCFG2

CFG3

CTLSTAT3

XFERCFG3

CFG4

CTLSTAT4

XFERCFG4

CFG5

CTLSTAT5

XFERCFG5

ENABLESET0

CFG6

CTLSTAT6

XFERCFG6

CFG7

CTLSTAT7

XFERCFG7

ENABLECLR0

CFG8

CTLSTAT8

XFERCFG8

CFG9

CTLSTAT9

XFERCFG9

ACTIVE0

CFG10

CTLSTAT10

XFERCFG10

BUSY0

CFG11

CTLSTAT11

XFERCFG11

CFG12

CTLSTAT12

XFERCFG12

INTSTAT

ERRINT0

CFG13

CTLSTAT13

XFERCFG13

CFG14

CTLSTAT14

XFERCFG14

INTENSET0

CFG15

CTLSTAT15

XFERCFG15

INTENCLR0

CFG16

CTLSTAT16

XFERCFG16

CFG17

CTLSTAT17

XFERCFG17

INTA0

CFG18

CTLSTAT18

XFERCFG18

CFG19

INTB0

CTLSTAT19

XFERCFG19

CFG20

CTLSTAT20

XFERCFG20

SETVALID0

CFG21

CTLSTAT21

XFERCFG21

SETTRIG0

ABORT0

SRAMBASE

CFG0

CTLSTAT0

XFERCFG0

CFG1

CTLSTAT1

XFERCFG1

ENABLE : DMA controller master enable.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 32 (32 bit)

PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 2 - 5 (4 bit)

TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)

BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)

SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)

Enumeration: ENUM

End of enumeration elements list.

DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)

VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)

TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)

Enumeration: ENUM

End of enumeration elements list.

SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 6 - 13 (8 bit)

WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)

SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)

Enumeration: ENUM

End of enumeration elements list.

DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)

PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 2 - 5 (4 bit)

TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)

BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)

SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)

Enumeration: ENUM

End of enumeration elements list.

DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)

VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)

TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)

Enumeration: ENUM

End of enumeration elements list.

SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 6 - 13 (8 bit)

WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)

SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)

Enumeration: ENUM

End of enumeration elements list.

DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)

PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 2 - 5 (4 bit)

TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)

BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)

SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)

Enumeration: ENUM

End of enumeration elements list.

DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)

VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)

TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)

Enumeration: ENUM

End of enumeration elements list.

SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 6 - 13 (8 bit)

WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)

SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)

Enumeration: ENUM

End of enumeration elements list.

DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)

PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 2 - 5 (4 bit)

TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)

BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)

SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)

Enumeration: ENUM

End of enumeration elements list.

DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)

VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)

TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)

Enumeration: ENUM

End of enumeration elements list.

SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 6 - 13 (8 bit)

WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)

SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)

Enumeration: ENUM

End of enumeration elements list.

DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)

ENA : Enable for DMA channels. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.
bits : 0 - 21 (22 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 22 - 53 (32 bit)

PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 2 - 5 (4 bit)

TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)

BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)

SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)

Enumeration: ENUM

End of enumeration elements list.

DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)

VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)

TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)

Enumeration: ENUM

End of enumeration elements list.

SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 6 - 13 (8 bit)

WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)

SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)

Enumeration: ENUM

End of enumeration elements list.

DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)

PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 2 - 5 (4 bit)

TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)

BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)

SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)

Enumeration: ENUM

End of enumeration elements list.

DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)

VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)

TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)

Enumeration: ENUM

End of enumeration elements list.

SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 6 - 13 (8 bit)

WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)

SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)

Enumeration: ENUM

End of enumeration elements list.

DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)

CLR : Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.
bits : 0 - 21 (22 bit)

RESERVED : Reserved.
bits : 22 - 53 (32 bit)

PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 2 - 5 (4 bit)

TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)

BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)

SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)

Enumeration: ENUM

End of enumeration elements list.

DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)

VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)

TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)

Enumeration: ENUM

End of enumeration elements list.

SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 6 - 13 (8 bit)

WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)

SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)

Enumeration: ENUM

End of enumeration elements list.

DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)

PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 2 - 5 (4 bit)

TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)

BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)

SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)

Enumeration: ENUM

End of enumeration elements list.

DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)

VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)

TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)

Enumeration: ENUM

End of enumeration elements list.

SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

End of enumeration elements list.

SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 6 - 13 (8 bit)

WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)

Enumeration: ENUM

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)

SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)

Enumeration: ENUM

End of enumeration elements list.

DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)

Enumeration: ENUM

End of enumeration elements list.

XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)

ACT : Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.
bits : 0 - 21 (22 bit)

RESERVED : Reserved.
bits : 22 - 53 (32 bit)

PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)

Enumeration: ENUM