Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDEN : Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : STOP
Stop. The watchdog timer is stopped.
1 : RUN
Run. The watchdog timer is running.
End of enumeration elements list.
WDRESET : Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : INTERRUPT
Interrupt. A watchdog time-out will not cause a
chip reset.
1 : RESET
Reset. A watchdog time-out will cause a chip
reset.
End of enumeration elements list.
WDTOF : Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1.
bits : 2 - 4 (3 bit)
WDINT : Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software.
bits : 3 - 6 (4 bit)
WDPROTECT : Watchdog update mode. This bit can be set once by software and is only cleared by a reset.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : FLEXIBLE
Flexible. The watchdog time-out value (TC) can be
changed at any time.
1 : THRESHOLD
Threshold. The watchdog time-out value (TC) can be
changed only after the counter is below the value of
WDWARNINT and WDWINDOW.
End of enumeration elements list.
LOCK : Once this bit is set to one and a watchdog feed is performed, disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset.
bits : 5 - 10 (6 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 6 - 37 (32 bit)
Watchdog Warning Interrupt compare value.
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WARNINT : Watchdog warning interrupt compare value.
bits : 0 - 9 (10 bit)
RESERVED : Reserved, only zero should be written.
bits : 10 - 41 (32 bit)
Watchdog Window compare value.
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WINDOW : Watchdog window value.
bits : 0 - 23 (24 bit)
RESERVED : Reserved, only zero should be written.
bits : 24 - 55 (32 bit)
Watchdog timer constant register. This 24-bit register determines the time-out value.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Watchdog time-out value.
bits : 0 - 23 (24 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 55 (32 bit)
Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.
address_offset : 0x8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FEED : Feed value should be 0xAA followed by 0x55.
bits : 0 - 7 (8 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 8 - 39 (32 bit)
Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer.
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Counter timer value.
bits : 0 - 23 (24 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 55 (32 bit)
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