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address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Compare value LSB register. Holds the 32 LSBs of the compare value.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RICOMP : Compare register. Holds the 32 LSBs of the value which is compared to the counter.
bits : 0 - 31 (32 bit)
Compare value MSB register. Holds the 16 MSBs of the compare value.
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RICOMP : Compare value MSB register. Holds the 16 MSBs of the value which is compared to the counter.
bits : 0 - 15 (16 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 16 - 47 (32 bit)
Mask MSB register. This register holds the 16 MSBs of the mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register.
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RIMASK : Mask register. This register holds the 16 MSBs of the mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true).
bits : 0 - 15 (16 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 16 - 47 (32 bit)
Counter MSB register. 16 MSBs of the counter.
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RICOUNTER : 16 LSBs of the up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software.
bits : 0 - 15 (16 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 16 - 47 (32 bit)
Mask LSB register. This register holds the 32 LSB s of the mask value. A 1 written to any bit will force the compare to be true for the corresponding bit of the counter and compare register.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RIMASK : Mask register. This register holds the 32 LSBs of the mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true).
bits : 0 - 31 (32 bit)
Control register.
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RITINT : Interrupt flag
bits : 0 - 0 (1 bit)
Enumeration: ENUM
1 : MATCH
This bit is set to 1 by hardware whenever the
counter value equals the masked compare value specified by
the contents of RICOMPVAL and RIMASK registers. Writing a 1
to this bit will clear it to 0. Writing a 0 has no
effect.
0 : NOMTCH
The counter value does not equal the masked compare
value.
End of enumeration elements list.
RITENCLR : Timer enable clear
bits : 1 - 2 (2 bit)
Enumeration: ENUM
1 : CLEAR
The timer will be cleared to 0 whenever the counter
value equals the masked compare value specified by the
contents of COMPVAL/COMPVAL_H and MASK/MASK_H registers.
This will occur on the same clock that sets the interrupt
flag.
0 : NOCLEAR
The timer will not be cleared to 0.
End of enumeration elements list.
RITENBR : Timer enable for debug
bits : 2 - 4 (3 bit)
Enumeration: ENUM
1 : HALT
The timer is halted when the processor is halted
for debugging.
0 : DEBUG
Debug has no effect on the timer
operation.
End of enumeration elements list.
RITEN : Timer enable.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
1 : TIMER_ENABLED
Timer enabled. This can be overruled by a debug
halt if enabled in bit 2.
0 : TIMER_DISABLED
Timer disabled.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 4 - 35 (32 bit)
Counter LSB register. 32 LSBs of the counter.
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RICOUNTER : 32 LSBs of the up counter. Counts continuously unless RITEN bit in CTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software.
bits : 0 - 31 (32 bit)
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