Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
MRTn Time interval value register. This value is loaded into the TIMER0 register.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVALUE : Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
bits : 0 - 23 (24 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 54 (31 bit)
LOAD : Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
bits : 31 - 62 (32 bit)
Enumeration: ENUM
0 : NO_FORCE_LOAD
No force load. The load from the INTVALn register
to the TIMERn register is processed at the end of the time
interval if the repeat mode is selected.
1 : FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is
immediately loaded into the TIMERn register while TIMERn is
running.
End of enumeration elements list.
MRTn Time interval value register. This value is loaded into the TIMER0 register.
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVALUE : Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
bits : 0 - 23 (24 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 54 (31 bit)
LOAD : Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
bits : 31 - 62 (32 bit)
Enumeration: ENUM
0 : NO_FORCE_LOAD
No force load. The load from the INTVALn register
to the TIMERn register is processed at the end of the time
interval if the repeat mode is selected.
1 : FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is
immediately loaded into the TIMERn register while TIMERn is
running.
End of enumeration elements list.
MRTn Control register. This register controls the MRTn modes.
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEN : Enable the TIMERn interrupt.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
TIMERn interrupt is disabled.
1 : ENABLED
TIMERn interrupt is enabled.
End of enumeration elements list.
MODE : Selects timer mode.
bits : 1 - 3 (3 bit)
Enumeration: ENUM
0x0 : REPEAT_INTERRUPT_MOD
Repeat interrupt mode.
0x1 : ONE_SHOT_INTERRUPT_M
One-shot interrupt mode.
0x2 : ONE_SHOT_STALL_MODE
One-shot stall mode.
0x3 : RESERVED
Reserved.
End of enumeration elements list.
RESERVED : Reserved.
bits : 3 - 34 (32 bit)
MRTn Status register.
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTFLAG : Monitors the interrupt flag.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent
to no operation.
1 : PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because
TIMERn has reached the end of the time interval. If the
INTEN bit in the CONTROLn is also set to 1, the interrupt
for timer channel n and the global interrupt are raised.
Writing a 1 to this bit clears the interrupt
request.
End of enumeration elements list.
RUN : Indicates the state of TIMERn. This bit is read-only.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : IDLE_STATE
Idle state. TIMERn is stopped.
1 : RUNNING
Running. TIMERn is running.
End of enumeration elements list.
INUSE : Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NO
This channel is not in use.
1 : YES
This channel is in use.
End of enumeration elements list.
RESERVED : Reserved.
bits : 2 - 33 (32 bit)
MRTn Timer register. This register reads the value of the down-counter.
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUE : Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
bits : 0 - 23 (24 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 55 (32 bit)
MRTn Control register. This register controls the MRTn modes.
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEN : Enable the TIMERn interrupt.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
TIMERn interrupt is disabled.
1 : ENABLED
TIMERn interrupt is enabled.
End of enumeration elements list.
MODE : Selects timer mode.
bits : 1 - 3 (3 bit)
Enumeration: ENUM
0x0 : REPEAT_INTERRUPT_MOD
Repeat interrupt mode.
0x1 : ONE_SHOT_INTERRUPT_M
One-shot interrupt mode.
0x2 : ONE_SHOT_STALL_MODE
One-shot stall mode.
0x3 : RESERVED
Reserved.
End of enumeration elements list.
RESERVED : Reserved.
bits : 3 - 34 (32 bit)
MRTn Time interval value register. This value is loaded into the TIMER0 register.
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVALUE : Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
bits : 0 - 23 (24 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 54 (31 bit)
LOAD : Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
bits : 31 - 62 (32 bit)
Enumeration: ENUM
0 : NO_FORCE_LOAD
No force load. The load from the INTVALn register
to the TIMERn register is processed at the end of the time
interval if the repeat mode is selected.
1 : FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is
immediately loaded into the TIMERn register while TIMERn is
running.
End of enumeration elements list.
MRTn Status register.
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTFLAG : Monitors the interrupt flag.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent
to no operation.
1 : PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because
TIMERn has reached the end of the time interval. If the
INTEN bit in the CONTROLn is also set to 1, the interrupt
for timer channel n and the global interrupt are raised.
Writing a 1 to this bit clears the interrupt
request.
End of enumeration elements list.
RUN : Indicates the state of TIMERn. This bit is read-only.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : IDLE_STATE
Idle state. TIMERn is stopped.
1 : RUNNING
Running. TIMERn is running.
End of enumeration elements list.
INUSE : Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NO
This channel is not in use.
1 : YES
This channel is in use.
End of enumeration elements list.
RESERVED : Reserved.
bits : 2 - 33 (32 bit)
MRTn Timer register. This register reads the value of the down-counter.
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUE : Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
bits : 0 - 23 (24 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 55 (32 bit)
MRTn Control register. This register controls the MRTn modes.
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEN : Enable the TIMERn interrupt.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
TIMERn interrupt is disabled.
1 : ENABLED
TIMERn interrupt is enabled.
End of enumeration elements list.
MODE : Selects timer mode.
bits : 1 - 3 (3 bit)
Enumeration: ENUM
0x0 : REPEAT_INTERRUPT_MOD
Repeat interrupt mode.
0x1 : ONE_SHOT_INTERRUPT_M
One-shot interrupt mode.
0x2 : ONE_SHOT_STALL_MODE
One-shot stall mode.
0x3 : RESERVED
Reserved.
End of enumeration elements list.
RESERVED : Reserved.
bits : 3 - 34 (32 bit)
MRTn Time interval value register. This value is loaded into the TIMER0 register.
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVALUE : Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
bits : 0 - 23 (24 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 54 (31 bit)
LOAD : Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
bits : 31 - 62 (32 bit)
Enumeration: ENUM
0 : NO_FORCE_LOAD
No force load. The load from the INTVALn register
to the TIMERn register is processed at the end of the time
interval if the repeat mode is selected.
1 : FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is
immediately loaded into the TIMERn register while TIMERn is
running.
End of enumeration elements list.
MRTn Status register.
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTFLAG : Monitors the interrupt flag.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent
to no operation.
1 : PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because
TIMERn has reached the end of the time interval. If the
INTEN bit in the CONTROLn is also set to 1, the interrupt
for timer channel n and the global interrupt are raised.
Writing a 1 to this bit clears the interrupt
request.
End of enumeration elements list.
RUN : Indicates the state of TIMERn. This bit is read-only.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : IDLE_STATE
Idle state. TIMERn is stopped.
1 : RUNNING
Running. TIMERn is running.
End of enumeration elements list.
INUSE : Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NO
This channel is not in use.
1 : YES
This channel is in use.
End of enumeration elements list.
RESERVED : Reserved.
bits : 2 - 33 (32 bit)
MRTn Timer register. This register reads the value of the down-counter.
address_offset : 0x74 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUE : Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
bits : 0 - 23 (24 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 55 (32 bit)
MRTn Timer register. This register reads the value of the down-counter.
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUE : Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
bits : 0 - 23 (24 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 55 (32 bit)
MRTn Control register. This register controls the MRTn modes.
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEN : Enable the TIMERn interrupt.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
TIMERn interrupt is disabled.
1 : ENABLED
TIMERn interrupt is enabled.
End of enumeration elements list.
MODE : Selects timer mode.
bits : 1 - 3 (3 bit)
Enumeration: ENUM
0x0 : REPEAT_INTERRUPT_MOD
Repeat interrupt mode.
0x1 : ONE_SHOT_INTERRUPT_M
One-shot interrupt mode.
0x2 : ONE_SHOT_STALL_MODE
One-shot stall mode.
0x3 : RESERVED
Reserved.
End of enumeration elements list.
RESERVED : Reserved.
bits : 3 - 34 (32 bit)
MRTn Status register.
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTFLAG : Monitors the interrupt flag.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent
to no operation.
1 : PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because
TIMERn has reached the end of the time interval. If the
INTEN bit in the CONTROLn is also set to 1, the interrupt
for timer channel n and the global interrupt are raised.
Writing a 1 to this bit clears the interrupt
request.
End of enumeration elements list.
RUN : Indicates the state of TIMERn. This bit is read-only.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : IDLE_STATE
Idle state. TIMERn is stopped.
1 : RUNNING
Running. TIMERn is running.
End of enumeration elements list.
INUSE : Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NO
This channel is not in use.
1 : YES
This channel is in use.
End of enumeration elements list.
RESERVED : Reserved.
bits : 2 - 33 (32 bit)
Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature.
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NOC : Identifies the number of channels in this MRT.
bits : 0 - 3 (4 bit)
NOB : Identifies the number of timer bits in this MRT.
bits : 4 - 12 (9 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 9 - 39 (31 bit)
MULTITASK : Selects the operating mode for the INUSE flags and the IDLE_CH register. See Idle channel register (IDLE_CH) for details.
bits : 31 - 62 (32 bit)
Enumeration: ENUM
0 : HARDWARE_STATUS_MODE
Hardware status mode. In this mode, the INUSE(n)
flags for all channels are reset.
1 : MULTI_TASK_MODE
Multi-task mode.
End of enumeration elements list.
Idle channel register. This register returns the number of the first idle channel.
address_offset : 0xF4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Reserved.
bits : 0 - 3 (4 bit)
RESERVED : Reserved.
bits : 0 - 3 (4 bit)
CHAN : Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details.
bits : 4 - 11 (8 bit)
Global interrupt flag register
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GFLAG0 : Monitors the interrupt flag of TIMER0.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent
to no operation.
1 : PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because
TIMER0 has reached the end of the time interval. If the
INTEN bit in the CONTROL0 register is also set to 1, the
interrupt for timer channel 0 and the global interrupt are
raised. Writing a 1 to this bit clears the interrupt
request.
End of enumeration elements list.
GFLAG1 : Monitors the interrupt flag of TIMER1. See description of channel 0.
bits : 1 - 2 (2 bit)
GFLAG2 : Monitors the interrupt flag of TIMER2. See description of channel 0.
bits : 2 - 4 (3 bit)
GFLAG3 : Monitors the interrupt flag of TIMER3. See description of channel 0.
bits : 3 - 6 (4 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 4 - 35 (32 bit)
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