Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected
Pin Interrupt Mode register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMODE : Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive
bits : 0 - 7 (8 bit)
RESERVED : Reserved.
bits : 8 - 39 (32 bit)
Pin interrupt active level or falling edge interrupt enable register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENAF : Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.
bits : 0 - 7 (8 bit)
RESERVED : Reserved.
bits : 8 - 39 (32 bit)
Pin interrupt active level or falling edge interrupt set register
address_offset : 0x14 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SETENAF : Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.
bits : 0 - 7 (8 bit)
RESERVED : Reserved.
bits : 8 - 39 (32 bit)
Pin interrupt active level (falling edge) interrupt clear register
address_offset : 0x18 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENAF : Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.
bits : 0 - 7 (8 bit)
RESERVED : Reserved.
bits : 8 - 39 (32 bit)
Pin interrupt rising edge register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDET : Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.
bits : 0 - 7 (8 bit)
RESERVED : Reserved.
bits : 8 - 39 (32 bit)
Pin interrupt falling edge register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FDET : Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.
bits : 0 - 7 (8 bit)
RESERVED : Reserved.
bits : 8 - 39 (32 bit)
Pin interrupt status register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSTAT : Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).
bits : 0 - 7 (8 bit)
RESERVED : Reserved.
bits : 8 - 39 (32 bit)
GPIO pattern match interrupt control register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL_PMATCH : Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : PIN_INTERRUPT_INTER
Pin interrupt. Interrupts are driven in response to the standard pin interrupt function
1 : PATTERN_MATCH_INTER
Pattern match. Interrupts are driven in response to pattern matches.
End of enumeration elements list.
ENA_RXEV : Enables the RxEv output to the ARM cpu and/or to a GPIO output when the specified boolean expression evaluates to true.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED_RXEV_OUTPU
Disabled. RxEv output to the cpu is disabled.
1 : ENABLED_RXEV_OUTPUT
Enabled. RxEv output to the cpu is enabled.
End of enumeration elements list.
RESERVED : Reserved. Do not write 1s to unused bits.
bits : 2 - 25 (24 bit)
PMAT : This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs.
bits : 24 - 55 (32 bit)
GPIO pattern match interrupt bit-slice source register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reserved : Software should not write 1s to unused bits.
bits : 0 - 7 (8 bit)
SRC0 : Selects the input source for bit slice 0
bits : 8 - 18 (11 bit)
Enumeration: ENUM
0x0 : INPUT_0_SELECTS_PIN
Input 0. Selects pin interrupt input 0 as the source to bit slice 0.
0x1 : INPUT_1_SELECTS_PIN
Input 1. Selects pin interrupt input 1 as the source to bit slice 0.
0x2 : INPUT_2_SELECTS_PIN
Input 2. Selects pin interrupt input 2 as the source to bit slice 0.
0x3 : INPUT_3_SELECTS_PIN
Input 3. Selects pin interrupt input 3 as the source to bit slice 0.
0x4 : INPUT_4_SELECTS_PIN
Input 4. Selects pin interrupt input 4 as the source to bit slice 0.
0x5 : INPUT_5_SELECTS_PIN
Input 5. Selects pin interrupt input 5 as the source to bit slice 0.
0x6 : INPUT_6_SELECTS_PIN
Input 6. Selects pin interrupt input 6 as the source to bit slice 0.
0x7 : INPUT_7_SELECTS_PIN
Input 7. Selects pin interrupt input 7 as the source to bit slice 0.
End of enumeration elements list.
SRC1 : Selects the input source for bit slice 1
bits : 11 - 24 (14 bit)
Enumeration: ENUM
0x0 : INPUT_0_SELECTS_PIN
Input 0. Selects pin interrupt input 0 as the source to bit slice 1.
0x1 : INPUT_1_SELECTS_PIN
Input 1. Selects pin interrupt input 1 as the source to bit slice 1.
0x2 : INPUT_2_SELECTS_PIN
Input 2. Selects pin interrupt input 2 as the source to bit slice 1.
0x3 : INPUT_3_SELECTS_PIN
Input 3. Selects pin interrupt input 3 as the source to bit slice 1.
0x4 : INPUT_4_SELECTS_PIN
Input 4. Selects pin interrupt input 4 as the source to bit slice 1.
0x5 : INPUT_5_SELECTS_PIN
Input 5. Selects pin interrupt input 5 as the source to bit slice 1.
0x6 : INPUT_6_SELECTS_PIN
Input 6. Selects pin interrupt input 6 as the source to bit slice 1.
0x7 : INPUT_7_SELECTS_PIN
Input 7. Selects pin interrupt input 7 as the source to bit slice 1.
End of enumeration elements list.
SRC2 : Selects the input source for bit slice 2
bits : 14 - 30 (17 bit)
Enumeration: ENUM
0x0 : INPUT_0_SELECTS_PIN
Input 0. Selects pin interrupt input 0 as the source to bit slice 2.
0x1 : INPUT_1_SELECTS_PIN
Input 1. Selects pin interrupt input 1 as the source to bit slice 2.
0x2 : INPUT_2_SELECTS_PIN
Input 2. Selects pin interrupt input 2 as the source to bit slice 2.
0x3 : INPUT_3_SELECTS_PIN
Input 3. Selects pin interrupt input 3 as the source to bit slice 2.
0x4 : INPUT_4_SELECTS_PIN
Input 4. Selects pin interrupt input 4 as the source to bit slice 2.
0x5 : INPUT_5_SELECTS_PIN
Input 5. Selects pin interrupt input 5 as the source to bit slice 2.
0x6 : INPUT_6_SELECTS_PIN
Input 6. Selects pin interrupt input 6 as the source to bit slice 2.
0x7 : INPUT_7_SELECTS_PIN
Input 7. Selects pin interrupt input 7 as the source to bit slice 2.
End of enumeration elements list.
SRC3 : Selects the input source for bit slice 3
bits : 17 - 36 (20 bit)
Enumeration: ENUM
0x0 : INPUT_0_SELECTS_PIN
Input 0. Selects pin interrupt input 0 as the source to bit slice 3.
0x1 : INPUT_1_SELECTS_PIN
Input 1. Selects pin interrupt input 1 as the source to bit slice 3.
0x2 : INPUT_2_SELECTS_PIN
Input 2. Selects pin interrupt input 2 as the source to bit slice 3.
0x3 : INPUT_3_SELECTS_PIN
Input 3. Selects pin interrupt input 3 as the source to bit slice 3.
0x4 : INPUT_4_SELECTS_PIN
Input 4. Selects pin interrupt input 4 as the source to bit slice 3.
0x5 : INPUT_5_SELECTS_PIN
Input 5. Selects pin interrupt input 5 as the source to bit slice 3.
0x6 : INPUT_6_SELECTS_PIN
Input 6. Selects pin interrupt input 6 as the source to bit slice 3.
0x7 : INPUT_7_SELECTS_PIN
Input 7. Selects pin interrupt input 7 as the source to bit slice 3.
End of enumeration elements list.
SRC4 : Selects the input source for bit slice 4
bits : 20 - 42 (23 bit)
Enumeration: ENUM
0x0 : INPUT_0_SELECTS_PIN
Input 0. Selects pin interrupt input 0 as the source to bit slice 4.
0x1 : INPUT_1_SELECTS_PIN
Input 1. Selects pin interrupt input 1 as the source to bit slice 4.
0x2 : INPUT_2_SELECTS_PIN
Input 2. Selects pin interrupt input 2 as the source to bit slice 4.
0x3 : INPUT_3_SELECTS_PIN
Input 3. Selects pin interrupt input 3 as the source to bit slice 4.
0x4 : INPUT_4_SELECTS_PIN
Input 4. Selects pin interrupt input 4 as the source to bit slice 4.
0x5 : INPUT_5_SELECTS_PIN
Input 5. Selects pin interrupt input 5 as the source to bit slice 4.
0x6 : INPUT_6_SELECTS_PIN
Input 6. Selects pin interrupt input 6 as the source to bit slice 4.
0x7 : INPUT_7_SELECTS_PIN
Input 7. Selects pin interrupt input 7 as the source to bit slice 4.
End of enumeration elements list.
SRC5 : Selects the input source for bit slice 5
bits : 23 - 48 (26 bit)
Enumeration: ENUM
0x0 : INPUT_0_SELECTS_PIN
Input 0. Selects pin interrupt input 0 as the source to bit slice 5.
0x1 : INPUT_1_SELECTS_PIN
Input 1. Selects pin interrupt input 1 as the source to bit slice 5.
0x2 : INPUT_2_SELECTS_PIN
Input 2. Selects pin interrupt input 2 as the source to bit slice 5.
0x3 : INPUT_3_SELECTS_PIN
Input 3. Selects pin interrupt input 3 as the source to bit slice 5.
0x4 : INPUT_4_SELECTS_PIN
Input 4. Selects pin interrupt input 4 as the source to bit slice 5.
0x5 : INPUT_5_SELECTS_PIN
Input 5. Selects pin interrupt input 5 as the source to bit slice 5.
0x6 : INPUT_6_SELECTS_PIN
Input 6. Selects pin interrupt input 6 as the source to bit slice 5.
0x7 : INPUT_7_SELECTS_PIN
Input 7. Selects pin interrupt input 7 as the source to bit slice 5.
End of enumeration elements list.
SRC6 : Selects the input source for bit slice 6
bits : 26 - 54 (29 bit)
Enumeration: ENUM
0x0 : INPUT_0_SELECTS_PIN
Input 0. Selects pin interrupt input 0 as the source to bit slice 6.
0x1 : INPUT_1_SELECTS_PIN
Input 1. Selects pin interrupt input 1 as the source to bit slice 6.
0x2 : INPUT_2_SELECTS_PIN
Input 2. Selects pin interrupt input 2 as the source to bit slice 6.
0x3 : INPUT_3_SELECTS_PIN
Input 3. Selects pin interrupt input 3 as the source to bit slice 6.
0x4 : INPUT_4_SELECTS_PIN
Input 4. Selects pin interrupt input 4 as the source to bit slice 6.
0x5 : INPUT_5_SELECTS_PIN
Input 5. Selects pin interrupt input 5 as the source to bit slice 6.
0x6 : INPUT_6_SELECTS_PIN
Input 6. Selects pin interrupt input 6 as the source to bit slice 6.
0x7 : INPUT_7_SELECTS_PIN
Input 7. Selects pin interrupt input 7 as the source to bit slice 6.
End of enumeration elements list.
SRC7 : Selects the input source for bit slice 7
bits : 29 - 60 (32 bit)
Enumeration: ENUM
0x0 : INPUT_0_SELECTS_PIN
Input 0. Selects pin interrupt input 0 as the source to bit slice 7.
0x1 : INPUT_1_SELECTS_PIN
Input 1. Selects pin interrupt input 1 as the source to bit slice 7.
0x2 : INPUT_2_SELECTS_PIN
Input 2. Selects pin interrupt input 2 as the source to bit slice 7.
0x3 : INPUT_3_SELECTS_PIN
Input 3. Selects pin interrupt input 3 as the source to bit slice 7.
0x4 : INPUT_4_SELECTS_PIN
Input 4. Selects pin interrupt input 4 as the source to bit slice 7.
0x5 : INPUT_5_SELECTS_PIN
Input 5. Selects pin interrupt input 5 as the source to bit slice 7.
0x6 : INPUT_6_SELECTS_PIN
Input 6. Selects pin interrupt input 6 as the source to bit slice 7.
0x7 : INPUT_7_SELECTS_PIN
Input 7. Selects pin interrupt input 7 as the source to bit slice 7.
End of enumeration elements list.
GPIO pattern match interrupt bit slice configuration register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROD_ENDPTS : A 1 in any bit of this field causes the corresponding bit slice to be the final component of a product term in the boolean expression. This has two effects: 1. The interrupt request associated with this bit-slice will be asserted whenever a match to that product term is detected. 2. The next bit slice will start a new, independent product term in the boolean expression (i.e. an OR will be inserted in the boolean expression following the element controlled by this bit slice).
bits : 0 - 6 (7 bit)
Reserved : (Bit slice 7 is automatically considered a product end point) Software should not write 1s to unused bits
bits : 7 - 14 (8 bit)
CFG0 : Specifies the match-contribution condition for bit slice 0.
bits : 8 - 18 (11 bit)
Enumeration: ENUM
0x0 : CONSTANT_1_THIS_BIT
Constant 1. This bit slice always contributes to a product term match.
0x1 : RISING_EDGE_MATCH_O
Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x2 : FALLING_EDGE_MATCH_
Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x3 : RISING_OR_FALLING_ED
Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x4 : HIGH_LEVEL_MATCH_F
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5 : LOW_LEVEL_MATCH_OCC
Low level. Match occurs when there is a low level on the specified input.
0x6 : CONSTANT_0_THIS_BIT
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)
0x7 : EVENT_MATCH_OCCURS_
Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3)
End of enumeration elements list.
CFG1 : Specifies the match-contribution condition for bit slice 1.
bits : 11 - 24 (14 bit)
Enumeration: ENUM
0x0 : CONSTANT_1_THIS_BIT
Constant 1. This bit slice always contributes to a product term match.
0x1 : RISING_EDGE_MATCH_O
Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x2 : FALLING_EDGE_MATCH_
Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x3 : RISING_OR_FALLING_ED
Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x4 : HIGH_LEVEL_MATCH_F
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5 : LOW_LEVEL_MATCH_OCC
Low level. Match occurs when there is a low level on the specified input.
0x6 : CONSTANT_0_THIS_BIT
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)
0x7 : EVENT_MATCH_OCCURS_
Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3)
End of enumeration elements list.
CFG2 : Specifies the match-contribution condition for bit slice 2.
bits : 14 - 30 (17 bit)
Enumeration: ENUM
0x0 : CONSTANT_1_THIS_BIT
Constant 1. This bit slice always contributes to a product term match.
0x1 : RISING_EDGE_MATCH_O
Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x2 : FALLING_EDGE_MATCH_
Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x3 : RISING_OR_FALLING_ED
Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x4 : HIGH_LEVEL_MATCH_F
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5 : LOW_LEVEL_MATCH_OCC
Low level. Match occurs when there is a low level on the specified input.
0x6 : CONSTANT_0_THIS_BIT
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)
0x7 : EVENT_MATCH_OCCURS_
Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3)
End of enumeration elements list.
CFG3 : Specifies the match-contribution condition for bit slice 3.
bits : 17 - 36 (20 bit)
Enumeration: ENUM
0x0 : CONSTANT_1_THIS_BIT
Constant 1. This bit slice always contributes to a product term match.
0x1 : RISING_EDGE_MATCH_O
Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x2 : FALLING_EDGE_MATCH_
Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x3 : RISING_OR_FALLING_ED
Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x4 : HIGH_LEVEL_MATCH_F
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5 : LOW_LEVEL_MATCH_OCC
Low level. Match occurs when there is a low level on the specified input.
0x6 : CONSTANT_0_THIS_BIT
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)
0x7 : EVENT_MATCH_OCCURS_
Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3)
End of enumeration elements list.
CFG4 : Specifies the match-contribution condition for bit slice 4.
bits : 20 - 42 (23 bit)
Enumeration: ENUM
0x0 : CONSTANT_1_THIS_BIT
Constant 1. This bit slice always contributes to a product term match.
0x1 : RISING_EDGE_MATCH_O
Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x2 : FALLING_EDGE_MATCH_
Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x3 : RISING_OR_FALLING_ED
Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x4 : HIGH_LEVEL_MATCH_F
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5 : LOW_LEVEL_MATCH_OCC
Low level. Match occurs when there is a low level on the specified input.
0x6 : CONSTANT_0_THIS_BIT
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)
0x7 : EVENT_MATCH_OCCURS_
Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3)
End of enumeration elements list.
CFG5 : Specifies the match-contribution condition for bit slice 5.
bits : 23 - 48 (26 bit)
Enumeration: ENUM
0x0 : CONSTANT_1_THIS_BIT
Constant 1. This bit slice always contributes to a product term match.
0x1 : RISING_EDGE_MATCH_O
Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x2 : FALLING_EDGE_MATCH_
Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x3 : RISING_OR_FALLING_ED
Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x4 : HIGH_LEVEL_MATCH_F
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5 : LOW_LEVEL_MATCH_OCC
Low level. Match occurs when there is a low level on the specified input.
0x6 : CONSTANT_0_THIS_BIT
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)
0x7 : EVENT_MATCH_OCCURS_
Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3)
End of enumeration elements list.
CFG6 : Specifies the match-contribution condition for bit slice 6.
bits : 26 - 54 (29 bit)
Enumeration: ENUM
0x0 : CONSTANT_1_THIS_BIT
Constant 1. This bit slice always contributes to a product term match.
0x1 : RISING_EDGE_MATCH_O
Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x2 : FALLING_EDGE_MATCH_
Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x3 : RISING_OR_FALLING_ED
Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x4 : HIGH_LEVEL_MATCH_F
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5 : LOW_LEVEL_MATCH_OCC
Low level. Match occurs when there is a low level on the specified input.
0x6 : CONSTANT_0_THIS_BIT
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)
0x7 : EVENT_MATCH_OCCURS_
Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3)
End of enumeration elements list.
CFG7 : Specifies the match-contribution condition for bit slice 7.
bits : 29 - 60 (32 bit)
Enumeration: ENUM
0x0 : CONSTANT_1_THIS_BIT
Constant 1. This bit slice always contributes to a product term match.
0x1 : RISING_EDGE_MATCH_O
Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x2 : FALLING_EDGE_MATCH_
Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x3 : RISING_OR_FALLING_ED
Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared.
0x4 : HIGH_LEVEL_MATCH_F
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x5 : LOW_LEVEL_MATCH_OCC
Low level. Match occurs when there is a low level on the specified input.
0x6 : CONSTANT_0_THIS_BIT
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)
0x7 : EVENT_MATCH_OCCURS_
Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3)
End of enumeration elements list.
Pin interrupt level or rising edge interrupt enable register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENRL : Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.
bits : 0 - 7 (8 bit)
RESERVED : Reserved.
bits : 8 - 39 (32 bit)
Pin interrupt level (rising edge) interrupt set register
address_offset : 0x8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SETENRL : Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.
bits : 0 - 7 (8 bit)
RESERVED : Reserved.
bits : 8 - 39 (32 bit)
Pin interrupt level or rising edge interrupt clear register
address_offset : 0xC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENRL : Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.
bits : 0 - 7 (8 bit)
RESERVED : Reserved.
bits : 8 - 39 (32 bit)
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