Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2D0 byte (0x0)
mem_usage : registers
protection : not protected
Miscellaneous Register 0
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFTOP_PWD : Control bit to power-down the analog bandgap reference circuitry
bits : 0 - 0 (1 bit)
access : read-write
REFTOP_SELFBIASOFF : Control bit to disable the self-bias circuit in the analog bandgap
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : REFTOP_SELFBIASOFF_0
Uses coarse bias currents for startup
0x1 : REFTOP_SELFBIASOFF_1
Uses bandgap-based bias currents for best performance.
End of enumeration elements list.
REFTOP_VBGADJ : Not related to oscillator.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : REFTOP_VBGADJ_0
Nominal VBG
0x1 : REFTOP_VBGADJ_1
VBG+0.78%
0x2 : REFTOP_VBGADJ_2
VBG+1.56%
0x3 : REFTOP_VBGADJ_3
VBG+2.34%
0x4 : REFTOP_VBGADJ_4
VBG-0.78%
0x5 : REFTOP_VBGADJ_5
VBG-1.56%
0x6 : REFTOP_VBGADJ_6
VBG-2.34%
0x7 : REFTOP_VBGADJ_7
VBG-3.12%
End of enumeration elements list.
REFTOP_VBGUP : Status bit that signals the analog bandgap voltage is up and stable
bits : 7 - 7 (1 bit)
access : read-write
STOP_MODE_CONFIG : Configure the analog behavior in stop mode.Not related to oscillator.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : STOP_MODE_CONFIG_0
All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
0x1 : STOP_MODE_CONFIG_1
Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
0x2 : STOP_MODE_CONFIG_2
XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
0x3 : STOP_MODE_CONFIG_3
XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
End of enumeration elements list.
DISCON_HIGH_SNVS : This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISCON_HIGH_SNVS_0
Turn on the switch
0x1 : DISCON_HIGH_SNVS_1
Turn off the switch
End of enumeration elements list.
OSC_I : This field determines the bias current in the 24MHz oscillator
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0 : NOMINAL
Nominal
0x1 : MINUS_12_5_PERCENT
Decrease current by 12.5%
0x2 : MINUS_25_PERCENT
Decrease current by 25.0%
0x3 : MINUS_37_5_PERCENT
Decrease current by 37.5%
End of enumeration elements list.
OSC_XTALOK : Status bit that signals that the output of the 24-MHz crystal oscillator is stable
bits : 15 - 15 (1 bit)
access : read-only
OSC_XTALOK_EN : This bit enables the detector that signals when the 24MHz crystal oscillator is stable.
bits : 16 - 16 (1 bit)
access : read-write
CLKGATE_CTRL : This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : ALLOW_AUTO_GATE
Allow the logic to automatically gate the clock when the XTAL is powered down.
0x1 : NO_AUTO_GATE
Prevent the logic from ever gating off the clock.
End of enumeration elements list.
CLKGATE_DELAY : This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block
bits : 26 - 28 (3 bit)
access : read-write
Enumeration:
0 : CLKGATE_DELAY_0
0.5ms
0x1 : CLKGATE_DELAY_1
1.0ms
0x2 : CLKGATE_DELAY_2
2.0ms
0x3 : CLKGATE_DELAY_3
3.0ms
0x4 : CLKGATE_DELAY_4
4.0ms
0x5 : CLKGATE_DELAY_5
5.0ms
0x6 : CLKGATE_DELAY_6
6.0ms
0x7 : CLKGATE_DELAY_7
7.0ms
End of enumeration elements list.
RTC_XTAL_SOURCE : This field indicates which chip source is being used for the rtc clock.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : RTC_XTAL_SOURCE_0
Internal ring oscillator
0x1 : RTC_XTAL_SOURCE_1
RTC_XTAL
End of enumeration elements list.
XTAL_24M_PWD : This field powers down the 24M crystal oscillator if set true.
bits : 30 - 30 (1 bit)
access : read-write
VID_PLL_PREDIV : Predivider for the source clock of the PLL's. Not related to oscillator.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VID_PLL_PREDIV_0
Divide by 1
0x1 : VID_PLL_PREDIV_1
Divide by 2
End of enumeration elements list.
Miscellaneous Register 0
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFTOP_PWD : Control bit to power-down the analog bandgap reference circuitry
bits : 0 - 0 (1 bit)
access : read-write
REFTOP_SELFBIASOFF : Control bit to disable the self-bias circuit in the analog bandgap
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : REFTOP_SELFBIASOFF_0
Uses coarse bias currents for startup
0x1 : REFTOP_SELFBIASOFF_1
Uses bandgap-based bias currents for best performance.
End of enumeration elements list.
REFTOP_VBGADJ : Not related to oscillator.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : REFTOP_VBGADJ_0
Nominal VBG
0x1 : REFTOP_VBGADJ_1
VBG+0.78%
0x2 : REFTOP_VBGADJ_2
VBG+1.56%
0x3 : REFTOP_VBGADJ_3
VBG+2.34%
0x4 : REFTOP_VBGADJ_4
VBG-0.78%
0x5 : REFTOP_VBGADJ_5
VBG-1.56%
0x6 : REFTOP_VBGADJ_6
VBG-2.34%
0x7 : REFTOP_VBGADJ_7
VBG-3.12%
End of enumeration elements list.
REFTOP_VBGUP : Status bit that signals the analog bandgap voltage is up and stable
bits : 7 - 7 (1 bit)
access : read-write
STOP_MODE_CONFIG : Configure the analog behavior in stop mode.Not related to oscillator.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : STOP_MODE_CONFIG_0
All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
0x1 : STOP_MODE_CONFIG_1
Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
0x2 : STOP_MODE_CONFIG_2
XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
0x3 : STOP_MODE_CONFIG_3
XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
End of enumeration elements list.
DISCON_HIGH_SNVS : This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISCON_HIGH_SNVS_0
Turn on the switch
0x1 : DISCON_HIGH_SNVS_1
Turn off the switch
End of enumeration elements list.
OSC_I : This field determines the bias current in the 24MHz oscillator
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0 : NOMINAL
Nominal
0x1 : MINUS_12_5_PERCENT
Decrease current by 12.5%
0x2 : MINUS_25_PERCENT
Decrease current by 25.0%
0x3 : MINUS_37_5_PERCENT
Decrease current by 37.5%
End of enumeration elements list.
OSC_XTALOK : Status bit that signals that the output of the 24-MHz crystal oscillator is stable
bits : 15 - 15 (1 bit)
access : read-only
OSC_XTALOK_EN : This bit enables the detector that signals when the 24MHz crystal oscillator is stable.
bits : 16 - 16 (1 bit)
access : read-write
CLKGATE_CTRL : This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : ALLOW_AUTO_GATE
Allow the logic to automatically gate the clock when the XTAL is powered down.
0x1 : NO_AUTO_GATE
Prevent the logic from ever gating off the clock.
End of enumeration elements list.
CLKGATE_DELAY : This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block
bits : 26 - 28 (3 bit)
access : read-write
Enumeration:
0 : CLKGATE_DELAY_0
0.5ms
0x1 : CLKGATE_DELAY_1
1.0ms
0x2 : CLKGATE_DELAY_2
2.0ms
0x3 : CLKGATE_DELAY_3
3.0ms
0x4 : CLKGATE_DELAY_4
4.0ms
0x5 : CLKGATE_DELAY_5
5.0ms
0x6 : CLKGATE_DELAY_6
6.0ms
0x7 : CLKGATE_DELAY_7
7.0ms
End of enumeration elements list.
RTC_XTAL_SOURCE : This field indicates which chip source is being used for the rtc clock.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : RTC_XTAL_SOURCE_0
Internal ring oscillator
0x1 : RTC_XTAL_SOURCE_1
RTC_XTAL
End of enumeration elements list.
XTAL_24M_PWD : This field powers down the 24M crystal oscillator if set true.
bits : 30 - 30 (1 bit)
access : read-write
VID_PLL_PREDIV : Predivider for the source clock of the PLL's. Not related to oscillator.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VID_PLL_PREDIV_0
Divide by 1
0x1 : VID_PLL_PREDIV_1
Divide by 2
End of enumeration elements list.
Miscellaneous Register 0
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFTOP_PWD : Control bit to power-down the analog bandgap reference circuitry
bits : 0 - 0 (1 bit)
access : read-write
REFTOP_SELFBIASOFF : Control bit to disable the self-bias circuit in the analog bandgap
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : REFTOP_SELFBIASOFF_0
Uses coarse bias currents for startup
0x1 : REFTOP_SELFBIASOFF_1
Uses bandgap-based bias currents for best performance.
End of enumeration elements list.
REFTOP_VBGADJ : Not related to oscillator.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : REFTOP_VBGADJ_0
Nominal VBG
0x1 : REFTOP_VBGADJ_1
VBG+0.78%
0x2 : REFTOP_VBGADJ_2
VBG+1.56%
0x3 : REFTOP_VBGADJ_3
VBG+2.34%
0x4 : REFTOP_VBGADJ_4
VBG-0.78%
0x5 : REFTOP_VBGADJ_5
VBG-1.56%
0x6 : REFTOP_VBGADJ_6
VBG-2.34%
0x7 : REFTOP_VBGADJ_7
VBG-3.12%
End of enumeration elements list.
REFTOP_VBGUP : Status bit that signals the analog bandgap voltage is up and stable
bits : 7 - 7 (1 bit)
access : read-write
STOP_MODE_CONFIG : Configure the analog behavior in stop mode.Not related to oscillator.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : STOP_MODE_CONFIG_0
All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
0x1 : STOP_MODE_CONFIG_1
Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
0x2 : STOP_MODE_CONFIG_2
XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
0x3 : STOP_MODE_CONFIG_3
XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
End of enumeration elements list.
DISCON_HIGH_SNVS : This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISCON_HIGH_SNVS_0
Turn on the switch
0x1 : DISCON_HIGH_SNVS_1
Turn off the switch
End of enumeration elements list.
OSC_I : This field determines the bias current in the 24MHz oscillator
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0 : NOMINAL
Nominal
0x1 : MINUS_12_5_PERCENT
Decrease current by 12.5%
0x2 : MINUS_25_PERCENT
Decrease current by 25.0%
0x3 : MINUS_37_5_PERCENT
Decrease current by 37.5%
End of enumeration elements list.
OSC_XTALOK : Status bit that signals that the output of the 24-MHz crystal oscillator is stable
bits : 15 - 15 (1 bit)
access : read-only
OSC_XTALOK_EN : This bit enables the detector that signals when the 24MHz crystal oscillator is stable.
bits : 16 - 16 (1 bit)
access : read-write
CLKGATE_CTRL : This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : ALLOW_AUTO_GATE
Allow the logic to automatically gate the clock when the XTAL is powered down.
0x1 : NO_AUTO_GATE
Prevent the logic from ever gating off the clock.
End of enumeration elements list.
CLKGATE_DELAY : This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block
bits : 26 - 28 (3 bit)
access : read-write
Enumeration:
0 : CLKGATE_DELAY_0
0.5ms
0x1 : CLKGATE_DELAY_1
1.0ms
0x2 : CLKGATE_DELAY_2
2.0ms
0x3 : CLKGATE_DELAY_3
3.0ms
0x4 : CLKGATE_DELAY_4
4.0ms
0x5 : CLKGATE_DELAY_5
5.0ms
0x6 : CLKGATE_DELAY_6
6.0ms
0x7 : CLKGATE_DELAY_7
7.0ms
End of enumeration elements list.
RTC_XTAL_SOURCE : This field indicates which chip source is being used for the rtc clock.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : RTC_XTAL_SOURCE_0
Internal ring oscillator
0x1 : RTC_XTAL_SOURCE_1
RTC_XTAL
End of enumeration elements list.
XTAL_24M_PWD : This field powers down the 24M crystal oscillator if set true.
bits : 30 - 30 (1 bit)
access : read-write
VID_PLL_PREDIV : Predivider for the source clock of the PLL's. Not related to oscillator.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VID_PLL_PREDIV_0
Divide by 1
0x1 : VID_PLL_PREDIV_1
Divide by 2
End of enumeration elements list.
Miscellaneous Register 0
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFTOP_PWD : Control bit to power-down the analog bandgap reference circuitry
bits : 0 - 0 (1 bit)
access : read-write
REFTOP_SELFBIASOFF : Control bit to disable the self-bias circuit in the analog bandgap
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : REFTOP_SELFBIASOFF_0
Uses coarse bias currents for startup
0x1 : REFTOP_SELFBIASOFF_1
Uses bandgap-based bias currents for best performance.
End of enumeration elements list.
REFTOP_VBGADJ : Not related to oscillator.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : REFTOP_VBGADJ_0
Nominal VBG
0x1 : REFTOP_VBGADJ_1
VBG+0.78%
0x2 : REFTOP_VBGADJ_2
VBG+1.56%
0x3 : REFTOP_VBGADJ_3
VBG+2.34%
0x4 : REFTOP_VBGADJ_4
VBG-0.78%
0x5 : REFTOP_VBGADJ_5
VBG-1.56%
0x6 : REFTOP_VBGADJ_6
VBG-2.34%
0x7 : REFTOP_VBGADJ_7
VBG-3.12%
End of enumeration elements list.
REFTOP_VBGUP : Status bit that signals the analog bandgap voltage is up and stable
bits : 7 - 7 (1 bit)
access : read-write
STOP_MODE_CONFIG : Configure the analog behavior in stop mode.Not related to oscillator.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : STOP_MODE_CONFIG_0
All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
0x1 : STOP_MODE_CONFIG_1
Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
0x2 : STOP_MODE_CONFIG_2
XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
0x3 : STOP_MODE_CONFIG_3
XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
End of enumeration elements list.
DISCON_HIGH_SNVS : This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISCON_HIGH_SNVS_0
Turn on the switch
0x1 : DISCON_HIGH_SNVS_1
Turn off the switch
End of enumeration elements list.
OSC_I : This field determines the bias current in the 24MHz oscillator
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0 : NOMINAL
Nominal
0x1 : MINUS_12_5_PERCENT
Decrease current by 12.5%
0x2 : MINUS_25_PERCENT
Decrease current by 25.0%
0x3 : MINUS_37_5_PERCENT
Decrease current by 37.5%
End of enumeration elements list.
OSC_XTALOK : Status bit that signals that the output of the 24-MHz crystal oscillator is stable
bits : 15 - 15 (1 bit)
access : read-only
OSC_XTALOK_EN : This bit enables the detector that signals when the 24MHz crystal oscillator is stable.
bits : 16 - 16 (1 bit)
access : read-write
CLKGATE_CTRL : This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : ALLOW_AUTO_GATE
Allow the logic to automatically gate the clock when the XTAL is powered down.
0x1 : NO_AUTO_GATE
Prevent the logic from ever gating off the clock.
End of enumeration elements list.
CLKGATE_DELAY : This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block
bits : 26 - 28 (3 bit)
access : read-write
Enumeration:
0 : CLKGATE_DELAY_0
0.5ms
0x1 : CLKGATE_DELAY_1
1.0ms
0x2 : CLKGATE_DELAY_2
2.0ms
0x3 : CLKGATE_DELAY_3
3.0ms
0x4 : CLKGATE_DELAY_4
4.0ms
0x5 : CLKGATE_DELAY_5
5.0ms
0x6 : CLKGATE_DELAY_6
6.0ms
0x7 : CLKGATE_DELAY_7
7.0ms
End of enumeration elements list.
RTC_XTAL_SOURCE : This field indicates which chip source is being used for the rtc clock.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : RTC_XTAL_SOURCE_0
Internal ring oscillator
0x1 : RTC_XTAL_SOURCE_1
RTC_XTAL
End of enumeration elements list.
XTAL_24M_PWD : This field powers down the 24M crystal oscillator if set true.
bits : 30 - 30 (1 bit)
access : read-write
VID_PLL_PREDIV : Predivider for the source clock of the PLL's. Not related to oscillator.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VID_PLL_PREDIV_0
Divide by 1
0x1 : VID_PLL_PREDIV_1
Divide by 2
End of enumeration elements list.
XTAL OSC (LP) Control Register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC_OSC_EN : RC Osc. enable control.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RC_OSC_EN_0
Use XTAL OSC to source the 24MHz clock
0x1 : RC_OSC_EN_1
Use RC OSC
End of enumeration elements list.
OSC_SEL : Select the source for the 24MHz clock.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : OSC_SEL_0
XTAL OSC
0x1 : OSC_SEL_1
RC OSC
End of enumeration elements list.
LPBG_SEL : Bandgap select. Not related to oscillator.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : LPBG_SEL_0
Normal power bandgap
0x1 : LPBG_SEL_1
Low power bandgap
End of enumeration elements list.
LPBG_TEST : Low power bandgap test bit. Not related to oscillator.
bits : 6 - 6 (1 bit)
access : read-write
REFTOP_IBIAS_OFF : Low power reftop ibias disable. Not related to oscillator.
bits : 7 - 7 (1 bit)
access : read-write
L1_PWRGATE : L1 power gate control. Used as software override. Not related to oscillator.
bits : 8 - 8 (1 bit)
access : read-write
L2_PWRGATE : L2 power gate control. Used as software override. Not related to oscillator.
bits : 9 - 9 (1 bit)
access : read-write
CPU_PWRGATE : CPU power gate control. Used as software override. Test purpose only Not related to oscillator.
bits : 10 - 10 (1 bit)
access : read-write
DISPLAY_PWRGATE : Display logic power gate control. Used as software override. Not related to oscillator.
bits : 11 - 11 (1 bit)
access : read-write
RCOSC_CG_OVERRIDE : For debug purposes only
bits : 13 - 13 (1 bit)
access : read-write
XTALOSC_PWRUP_DELAY : Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : XTALOSC_PWRUP_DELAY_0
0.25ms
0x1 : XTALOSC_PWRUP_DELAY_1
0.5ms
0x2 : XTALOSC_PWRUP_DELAY_2
1ms
0x3 : XTALOSC_PWRUP_DELAY_3
2ms
End of enumeration elements list.
XTALOSC_PWRUP_STAT : Status of the 24MHz xtal oscillator.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : XTALOSC_PWRUP_STAT_0
Not stable
0x1 : XTALOSC_PWRUP_STAT_1
Stable and ready to use
End of enumeration elements list.
MIX_PWRGATE : Display power gate control. Used as software mask. Set to zero to force ungated.
bits : 17 - 17 (1 bit)
access : read-write
GPU_PWRGATE : GPU power gate control. Used as software mask. Set to zero to force ungated.
bits : 18 - 18 (1 bit)
access : read-write
XTAL OSC (LP) Control Register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC_OSC_EN : RC Osc. enable control.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RC_OSC_EN_0
Use XTAL OSC to source the 24MHz clock
0x1 : RC_OSC_EN_1
Use RC OSC
End of enumeration elements list.
OSC_SEL : Select the source for the 24MHz clock.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : OSC_SEL_0
XTAL OSC
0x1 : OSC_SEL_1
RC OSC
End of enumeration elements list.
LPBG_SEL : Bandgap select. Not related to oscillator.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : LPBG_SEL_0
Normal power bandgap
0x1 : LPBG_SEL_1
Low power bandgap
End of enumeration elements list.
LPBG_TEST : Low power bandgap test bit. Not related to oscillator.
bits : 6 - 6 (1 bit)
access : read-write
REFTOP_IBIAS_OFF : Low power reftop ibias disable. Not related to oscillator.
bits : 7 - 7 (1 bit)
access : read-write
L1_PWRGATE : L1 power gate control. Used as software override. Not related to oscillator.
bits : 8 - 8 (1 bit)
access : read-write
L2_PWRGATE : L2 power gate control. Used as software override. Not related to oscillator.
bits : 9 - 9 (1 bit)
access : read-write
CPU_PWRGATE : CPU power gate control. Used as software override. Test purpose only Not related to oscillator.
bits : 10 - 10 (1 bit)
access : read-write
DISPLAY_PWRGATE : Display logic power gate control. Used as software override. Not related to oscillator.
bits : 11 - 11 (1 bit)
access : read-write
RCOSC_CG_OVERRIDE : For debug purposes only
bits : 13 - 13 (1 bit)
access : read-write
XTALOSC_PWRUP_DELAY : Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : XTALOSC_PWRUP_DELAY_0
0.25ms
0x1 : XTALOSC_PWRUP_DELAY_1
0.5ms
0x2 : XTALOSC_PWRUP_DELAY_2
1ms
0x3 : XTALOSC_PWRUP_DELAY_3
2ms
End of enumeration elements list.
XTALOSC_PWRUP_STAT : Status of the 24MHz xtal oscillator.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : XTALOSC_PWRUP_STAT_0
Not stable
0x1 : XTALOSC_PWRUP_STAT_1
Stable and ready to use
End of enumeration elements list.
MIX_PWRGATE : Display power gate control. Used as software mask. Set to zero to force ungated.
bits : 17 - 17 (1 bit)
access : read-write
GPU_PWRGATE : GPU power gate control. Used as software mask. Set to zero to force ungated.
bits : 18 - 18 (1 bit)
access : read-write
XTAL OSC (LP) Control Register
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC_OSC_EN : RC Osc. enable control.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RC_OSC_EN_0
Use XTAL OSC to source the 24MHz clock
0x1 : RC_OSC_EN_1
Use RC OSC
End of enumeration elements list.
OSC_SEL : Select the source for the 24MHz clock.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : OSC_SEL_0
XTAL OSC
0x1 : OSC_SEL_1
RC OSC
End of enumeration elements list.
LPBG_SEL : Bandgap select. Not related to oscillator.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : LPBG_SEL_0
Normal power bandgap
0x1 : LPBG_SEL_1
Low power bandgap
End of enumeration elements list.
LPBG_TEST : Low power bandgap test bit. Not related to oscillator.
bits : 6 - 6 (1 bit)
access : read-write
REFTOP_IBIAS_OFF : Low power reftop ibias disable. Not related to oscillator.
bits : 7 - 7 (1 bit)
access : read-write
L1_PWRGATE : L1 power gate control. Used as software override. Not related to oscillator.
bits : 8 - 8 (1 bit)
access : read-write
L2_PWRGATE : L2 power gate control. Used as software override. Not related to oscillator.
bits : 9 - 9 (1 bit)
access : read-write
CPU_PWRGATE : CPU power gate control. Used as software override. Test purpose only Not related to oscillator.
bits : 10 - 10 (1 bit)
access : read-write
DISPLAY_PWRGATE : Display logic power gate control. Used as software override. Not related to oscillator.
bits : 11 - 11 (1 bit)
access : read-write
RCOSC_CG_OVERRIDE : For debug purposes only
bits : 13 - 13 (1 bit)
access : read-write
XTALOSC_PWRUP_DELAY : Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : XTALOSC_PWRUP_DELAY_0
0.25ms
0x1 : XTALOSC_PWRUP_DELAY_1
0.5ms
0x2 : XTALOSC_PWRUP_DELAY_2
1ms
0x3 : XTALOSC_PWRUP_DELAY_3
2ms
End of enumeration elements list.
XTALOSC_PWRUP_STAT : Status of the 24MHz xtal oscillator.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : XTALOSC_PWRUP_STAT_0
Not stable
0x1 : XTALOSC_PWRUP_STAT_1
Stable and ready to use
End of enumeration elements list.
MIX_PWRGATE : Display power gate control. Used as software mask. Set to zero to force ungated.
bits : 17 - 17 (1 bit)
access : read-write
GPU_PWRGATE : GPU power gate control. Used as software mask. Set to zero to force ungated.
bits : 18 - 18 (1 bit)
access : read-write
XTAL OSC (LP) Control Register
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC_OSC_EN : RC Osc. enable control.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RC_OSC_EN_0
Use XTAL OSC to source the 24MHz clock
0x1 : RC_OSC_EN_1
Use RC OSC
End of enumeration elements list.
OSC_SEL : Select the source for the 24MHz clock.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : OSC_SEL_0
XTAL OSC
0x1 : OSC_SEL_1
RC OSC
End of enumeration elements list.
LPBG_SEL : Bandgap select. Not related to oscillator.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : LPBG_SEL_0
Normal power bandgap
0x1 : LPBG_SEL_1
Low power bandgap
End of enumeration elements list.
LPBG_TEST : Low power bandgap test bit. Not related to oscillator.
bits : 6 - 6 (1 bit)
access : read-write
REFTOP_IBIAS_OFF : Low power reftop ibias disable. Not related to oscillator.
bits : 7 - 7 (1 bit)
access : read-write
L1_PWRGATE : L1 power gate control. Used as software override. Not related to oscillator.
bits : 8 - 8 (1 bit)
access : read-write
L2_PWRGATE : L2 power gate control. Used as software override. Not related to oscillator.
bits : 9 - 9 (1 bit)
access : read-write
CPU_PWRGATE : CPU power gate control. Used as software override. Test purpose only Not related to oscillator.
bits : 10 - 10 (1 bit)
access : read-write
DISPLAY_PWRGATE : Display logic power gate control. Used as software override. Not related to oscillator.
bits : 11 - 11 (1 bit)
access : read-write
RCOSC_CG_OVERRIDE : For debug purposes only
bits : 13 - 13 (1 bit)
access : read-write
XTALOSC_PWRUP_DELAY : Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : XTALOSC_PWRUP_DELAY_0
0.25ms
0x1 : XTALOSC_PWRUP_DELAY_1
0.5ms
0x2 : XTALOSC_PWRUP_DELAY_2
1ms
0x3 : XTALOSC_PWRUP_DELAY_3
2ms
End of enumeration elements list.
XTALOSC_PWRUP_STAT : Status of the 24MHz xtal oscillator.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : XTALOSC_PWRUP_STAT_0
Not stable
0x1 : XTALOSC_PWRUP_STAT_1
Stable and ready to use
End of enumeration elements list.
MIX_PWRGATE : Display power gate control. Used as software mask. Set to zero to force ungated.
bits : 17 - 17 (1 bit)
access : read-write
GPU_PWRGATE : GPU power gate control. Used as software mask. Set to zero to force ungated.
bits : 18 - 18 (1 bit)
access : read-write
XTAL OSC Configuration 0 Register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.
bits : 0 - 0 (1 bit)
access : read-write
ENABLE : Enables the tuning logic to calculate new RC tuning values
bits : 1 - 1 (1 bit)
access : read-write
BYPASS : Bypasses any calculated RC tuning value and uses the programmed register value.
bits : 2 - 2 (1 bit)
access : read-write
INVERT : Invert the stepping of the calculated RC tuning value.
bits : 3 - 3 (1 bit)
access : read-write
RC_OSC_PROG : RC osc. tuning values.
bits : 4 - 11 (8 bit)
access : read-write
HYST_PLUS : Positive hysteresis value
bits : 12 - 15 (4 bit)
access : read-write
HYST_MINUS : Negative hysteresis value
bits : 16 - 19 (4 bit)
access : read-write
RC_OSC_PROG_CUR : The current tuning value in use.
bits : 24 - 31 (8 bit)
access : read-write
XTAL OSC Configuration 0 Register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.
bits : 0 - 0 (1 bit)
access : read-write
ENABLE : Enables the tuning logic to calculate new RC tuning values
bits : 1 - 1 (1 bit)
access : read-write
BYPASS : Bypasses any calculated RC tuning value and uses the programmed register value.
bits : 2 - 2 (1 bit)
access : read-write
INVERT : Invert the stepping of the calculated RC tuning value.
bits : 3 - 3 (1 bit)
access : read-write
RC_OSC_PROG : RC osc. tuning values.
bits : 4 - 11 (8 bit)
access : read-write
HYST_PLUS : Positive hysteresis value
bits : 12 - 15 (4 bit)
access : read-write
HYST_MINUS : Negative hysteresis value
bits : 16 - 19 (4 bit)
access : read-write
RC_OSC_PROG_CUR : The current tuning value in use.
bits : 24 - 31 (8 bit)
access : read-write
XTAL OSC Configuration 0 Register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.
bits : 0 - 0 (1 bit)
access : read-write
ENABLE : Enables the tuning logic to calculate new RC tuning values
bits : 1 - 1 (1 bit)
access : read-write
BYPASS : Bypasses any calculated RC tuning value and uses the programmed register value.
bits : 2 - 2 (1 bit)
access : read-write
INVERT : Invert the stepping of the calculated RC tuning value.
bits : 3 - 3 (1 bit)
access : read-write
RC_OSC_PROG : RC osc. tuning values.
bits : 4 - 11 (8 bit)
access : read-write
HYST_PLUS : Positive hysteresis value
bits : 12 - 15 (4 bit)
access : read-write
HYST_MINUS : Negative hysteresis value
bits : 16 - 19 (4 bit)
access : read-write
RC_OSC_PROG_CUR : The current tuning value in use.
bits : 24 - 31 (8 bit)
access : read-write
XTAL OSC Configuration 0 Register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.
bits : 0 - 0 (1 bit)
access : read-write
ENABLE : Enables the tuning logic to calculate new RC tuning values
bits : 1 - 1 (1 bit)
access : read-write
BYPASS : Bypasses any calculated RC tuning value and uses the programmed register value.
bits : 2 - 2 (1 bit)
access : read-write
INVERT : Invert the stepping of the calculated RC tuning value.
bits : 3 - 3 (1 bit)
access : read-write
RC_OSC_PROG : RC osc. tuning values.
bits : 4 - 11 (8 bit)
access : read-write
HYST_PLUS : Positive hysteresis value
bits : 12 - 15 (4 bit)
access : read-write
HYST_MINUS : Negative hysteresis value
bits : 16 - 19 (4 bit)
access : read-write
RC_OSC_PROG_CUR : The current tuning value in use.
bits : 24 - 31 (8 bit)
access : read-write
XTAL OSC Configuration 1 Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT_RC_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write
COUNT_RC_CUR : The current tuning value in use.
bits : 20 - 31 (12 bit)
access : read-write
XTAL OSC Configuration 1 Register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT_RC_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write
COUNT_RC_CUR : The current tuning value in use.
bits : 20 - 31 (12 bit)
access : read-write
XTAL OSC Configuration 1 Register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT_RC_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write
COUNT_RC_CUR : The current tuning value in use.
bits : 20 - 31 (12 bit)
access : read-write
XTAL OSC Configuration 1 Register
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT_RC_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write
COUNT_RC_CUR : The current tuning value in use.
bits : 20 - 31 (12 bit)
access : read-write
XTAL OSC Configuration 2 Register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT_1M_TRG : The target count used to tune the 1MHz clock frequency
bits : 0 - 11 (12 bit)
access : read-write
ENABLE_1M : Enable the 1MHz clock output. 0 - disabled; 1 - enabled.
bits : 16 - 16 (1 bit)
access : read-write
MUX_1M : Mux the corrected or uncorrected 1MHz clock to the output
bits : 17 - 17 (1 bit)
access : read-write
CLK_1M_ERR_FL : Flag indicates that the count_1m count wasn't reached within 1 32kHz period
bits : 31 - 31 (1 bit)
access : read-write
XTAL OSC Configuration 2 Register
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT_1M_TRG : The target count used to tune the 1MHz clock frequency
bits : 0 - 11 (12 bit)
access : read-write
ENABLE_1M : Enable the 1MHz clock output. 0 - disabled; 1 - enabled.
bits : 16 - 16 (1 bit)
access : read-write
MUX_1M : Mux the corrected or uncorrected 1MHz clock to the output
bits : 17 - 17 (1 bit)
access : read-write
CLK_1M_ERR_FL : Flag indicates that the count_1m count wasn't reached within 1 32kHz period
bits : 31 - 31 (1 bit)
access : read-write
XTAL OSC Configuration 2 Register
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT_1M_TRG : The target count used to tune the 1MHz clock frequency
bits : 0 - 11 (12 bit)
access : read-write
ENABLE_1M : Enable the 1MHz clock output. 0 - disabled; 1 - enabled.
bits : 16 - 16 (1 bit)
access : read-write
MUX_1M : Mux the corrected or uncorrected 1MHz clock to the output
bits : 17 - 17 (1 bit)
access : read-write
CLK_1M_ERR_FL : Flag indicates that the count_1m count wasn't reached within 1 32kHz period
bits : 31 - 31 (1 bit)
access : read-write
XTAL OSC Configuration 2 Register
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT_1M_TRG : The target count used to tune the 1MHz clock frequency
bits : 0 - 11 (12 bit)
access : read-write
ENABLE_1M : Enable the 1MHz clock output. 0 - disabled; 1 - enabled.
bits : 16 - 16 (1 bit)
access : read-write
MUX_1M : Mux the corrected or uncorrected 1MHz clock to the output
bits : 17 - 17 (1 bit)
access : read-write
CLK_1M_ERR_FL : Flag indicates that the count_1m count wasn't reached within 1 32kHz period
bits : 31 - 31 (1 bit)
access : read-write
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