\n
address_offset : 0x0 Bytes (0x0)
size : 0x8F4 byte (0x0)
mem_usage : registers
protection : not protected
OTP Controller Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : ADDR
bits : 0 - 5 (6 bit)
access : read-write
RSVD0 : RSVD0
bits : 6 - 7 (2 bit)
access : read-only
BUSY : BUSY
bits : 8 - 8 (1 bit)
access : read-only
ERROR : ERROR
bits : 9 - 9 (1 bit)
access : read-write
RELOAD_SHADOWS : RELOAD_SHADOWS
bits : 10 - 10 (1 bit)
access : read-write
CRC_TEST : CRC_TEST
bits : 11 - 11 (1 bit)
access : read-write
CRC_FAIL : CRC_FAIL
bits : 12 - 12 (1 bit)
access : read-write
RSVD1 : RSVD1
bits : 13 - 15 (3 bit)
access : read-only
WR_UNLOCK : WR_UNLOCK
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0x3E77 : KEY
Key needed to unlock HW_OCOTP_DATA register.
End of enumeration elements list.
OTP Controller Timing Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STROBE_PROG : STROBE_PROG
bits : 0 - 11 (12 bit)
access : read-write
RELAX : RELAX
bits : 12 - 15 (4 bit)
access : read-write
STROBE_READ : STROBE_READ
bits : 16 - 21 (6 bit)
access : read-write
WAIT : WAIT
bits : 22 - 27 (6 bit)
access : read-write
RSRVD0 : RSRVD0
bits : 28 - 31 (4 bit)
access : read-only
OTP Controller Timing Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELAX_PROG : RELAX_PROG
bits : 0 - 11 (12 bit)
access : read-write
RSRVD0 : RSRVD0
bits : 12 - 15 (4 bit)
access : read-only
RELAX_READ : RELAX_READ
bits : 16 - 21 (6 bit)
access : read-write
RSRVD1 : RSRVD0
bits : 22 - 31 (10 bit)
access : read-only
OTP Controller Write Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : DATA
bits : 0 - 31 (32 bit)
access : read-write
OTP Controller Write Data Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_FUSE : READ_FUSE
bits : 0 - 0 (1 bit)
access : read-write
RSVD0 : RSVD0
bits : 1 - 31 (31 bit)
access : read-only
OTP Controller Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : ADDR
bits : 0 - 5 (6 bit)
access : read-write
RSVD0 : RSVD0
bits : 6 - 7 (2 bit)
access : read-only
BUSY : BUSY
bits : 8 - 8 (1 bit)
access : read-only
ERROR : ERROR
bits : 9 - 9 (1 bit)
access : read-write
RELOAD_SHADOWS : RELOAD_SHADOWS
bits : 10 - 10 (1 bit)
access : read-write
CRC_TEST : CRC_TEST
bits : 11 - 11 (1 bit)
access : read-write
CRC_FAIL : CRC_FAIL
bits : 12 - 12 (1 bit)
access : read-write
RSVD1 : RSVD1
bits : 13 - 15 (3 bit)
access : read-only
WR_UNLOCK : WR_UNLOCK
bits : 16 - 31 (16 bit)
access : read-write
OTP Controller Read Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : DATA
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank0 Word0 (Lock controls)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TESTER : TESTER
bits : 0 - 1 (2 bit)
access : read-only
BOOT_CFG : BOOT_CFG
bits : 2 - 3 (2 bit)
access : read-only
MEM_TRIM : MEM_TRIM
bits : 4 - 5 (2 bit)
access : read-only
SJC_RESP : SJC_RESP
bits : 6 - 6 (1 bit)
access : read-only
GP4_RLOCK : GP4_RLOCK
bits : 7 - 7 (1 bit)
access : read-only
MAC_ADDR : MAC_ADDR
bits : 8 - 9 (2 bit)
access : read-only
GP1 : GP1
bits : 10 - 11 (2 bit)
access : read-only
GP2 : GP2
bits : 12 - 13 (2 bit)
access : read-only
ROM_PATCH : ROM_PATCH
bits : 15 - 15 (1 bit)
access : read-only
SW_GP1 : SW_GP1
bits : 16 - 16 (1 bit)
access : read-only
OTPMK : OTPMK
bits : 17 - 17 (1 bit)
access : read-only
ANALOG : ANALOG
bits : 18 - 19 (2 bit)
access : read-only
OTPMK_CRC : OTPMK_CRC
bits : 20 - 20 (1 bit)
access : read-only
SW_GP2_LOCK : SW_GP2_LOCK
bits : 21 - 21 (1 bit)
access : read-only
MISC_CONF : MISC_CONF
bits : 22 - 22 (1 bit)
access : read-only
SW_GP2_RLOCK : SW_GP2_RLOCK
bits : 23 - 23 (1 bit)
access : read-only
GP4 : GP4
bits : 24 - 25 (2 bit)
access : read-only
GP3 : GP3
bits : 26 - 27 (2 bit)
access : read-only
FIELD_RETURN : FIELD_RETURN
bits : 28 - 31 (4 bit)
access : read-write
Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.)
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.)
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.)
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.)
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.)
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.)
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.)
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank1 Word0 (Memory Related Info.)
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank1 Word1 (Memory Related Info.)
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank1 Word2 (Memory Related Info.)
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank1 Word3 (Memory Related Info.)
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank1 Word4 (Memory Related Info.)
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank1 Word5 (Memory Related Info.)
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.)
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.)
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Sticky bit Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLOCK_DTCP_KEY : BLOCK_DTCP_KEY
bits : 0 - 0 (1 bit)
access : read-write
SRK_REVOKE_LOCK : SRK_REVOKE_LOCK
bits : 1 - 1 (1 bit)
access : read-write
FIELD_RETURN_LOCK : FIELD_RETURN_LOCK
bits : 2 - 2 (1 bit)
access : read-write
BLOCK_ROM_PART : BLOCK_ROM_PART
bits : 3 - 3 (1 bit)
access : read-write
JTAG_BLOCK_RELEASE : JTAG_BLOCK_RELEASE
bits : 4 - 4 (1 bit)
access : read-write
RSVD0 : RSVD0
bits : 5 - 31 (27 bit)
access : read-only
Value of OTP Bank2 Word0 (OTPMK Key)
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank2 Word1 (OTPMK Key)
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank2 Word2 (OTPMK Key)
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank2 Word3 (OTPMK Key)
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank2 Word4 (OTPMK Key)
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank2 Word5 (OTPMK Key)
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank2 Word6 (OTPMK Key)
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank2 Word7 (OTPMK Key)
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Shadow Register for OTP Bank3 Word0 (SRK Hash)
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Shadow Register for OTP Bank3 Word1 (SRK Hash)
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Shadow Register for OTP Bank3 Word2 (SRK Hash)
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Shadow Register for OTP Bank3 Word3 (SRK Hash)
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Shadow Register for OTP Bank3 Word4 (SRK Hash)
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Shadow Register for OTP Bank3 Word5 (SRK Hash)
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Shadow Register for OTP Bank3 Word6 (SRK Hash)
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Shadow Register for OTP Bank3 Word7 (SRK Hash)
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Software Controllable Signals Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HAB_JDE : HAB_JDE
bits : 0 - 0 (1 bit)
access : read-write
SPARE : SPARE
bits : 1 - 30 (30 bit)
access : read-write
LOCK : LOCK
bits : 31 - 31 (1 bit)
access : read-write
Value of OTP Bank4 Word0 (Secure JTAG Response Field)
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank4 Word1 (Secure JTAG Response Field)
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank4 Word2 (MAC Address)
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank4 Word3 (MAC Address)
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Software Controllable Signals Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HAB_JDE : HAB_JDE
bits : 0 - 0 (1 bit)
access : read-write
SPARE : SPARE
bits : 1 - 30 (30 bit)
access : read-write
LOCK : LOCK
bits : 31 - 31 (1 bit)
access : read-write
Value of OTP Bank4 Word4 (MAC2 Address)
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank4 Word5 (CRC Key)
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank4 Word6 (General Purpose Customer Defined Info)
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank4 Word7 (General Purpose Customer Defined Info)
address_offset : 0x670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Software Controllable Signals Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HAB_JDE : HAB_JDE
bits : 0 - 0 (1 bit)
access : read-write
SPARE : SPARE
bits : 1 - 30 (30 bit)
access : read-write
LOCK : LOCK
bits : 31 - 31 (1 bit)
access : read-write
Value of OTP Bank5 Word0 (SW GP1)
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank5 Word1 (SW GP2)
address_offset : 0x690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank5 Word2 (SW GP2)
address_offset : 0x6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank5 Word3 (SW GP2)
address_offset : 0x6B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Software Controllable Signals Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HAB_JDE : HAB_JDE
bits : 0 - 0 (1 bit)
access : read-write
SPARE : SPARE
bits : 1 - 30 (30 bit)
access : read-write
LOCK : LOCK
bits : 31 - 31 (1 bit)
access : read-write
Value of OTP Bank5 Word4 (SW GP2)
address_offset : 0x6C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank5 Word5 (Misc Conf)
address_offset : 0x6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank5 Word6 (Misc Conf)
address_offset : 0x6E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank5 Word7 (SRK Revoke)
address_offset : 0x6F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
OTP Controller CRC test address
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_START_ADDR : DATA_START_ADDR
bits : 0 - 7 (8 bit)
access : read-write
DATA_END_ADDR : DATA_END_ADDR
bits : 8 - 15 (8 bit)
access : read-write
CRC_ADDR : CRC_ADDR
bits : 16 - 23 (8 bit)
access : read-write
OTPMK_CRC : OTPMK_CRC
bits : 24 - 24 (1 bit)
access : read-write
RSVD0 : RSVD0
bits : 25 - 31 (7 bit)
access : read-only
OTP Controller Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : ADDR
bits : 0 - 5 (6 bit)
access : read-write
RSVD0 : RSVD0
bits : 6 - 7 (2 bit)
access : read-only
BUSY : BUSY
bits : 8 - 8 (1 bit)
access : read-only
ERROR : ERROR
bits : 9 - 9 (1 bit)
access : read-write
RELOAD_SHADOWS : RELOAD_SHADOWS
bits : 10 - 10 (1 bit)
access : read-write
CRC_TEST : CRC_TEST
bits : 11 - 11 (1 bit)
access : read-write
CRC_FAIL : CRC_FAIL
bits : 12 - 12 (1 bit)
access : read-write
RSVD1 : RSVD1
bits : 13 - 15 (3 bit)
access : read-only
WR_UNLOCK : WR_UNLOCK
bits : 16 - 31 (16 bit)
access : read-write
OTP Controller CRC Value Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : DATA
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank6 Word0 (ROM Patch)
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank6 Word1 (ROM Patch)
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank6 Word2 (ROM Patch)
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank6 Word3 (ROM Patch)
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank6 Word4 (ROM Patch)
address_offset : 0x840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank6 Word5 (ROM Patch)
address_offset : 0x850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank6 Word6 (ROM Patch)
address_offset : 0x860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank6 Word7 (ROM Patch)
address_offset : 0x870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank7 Word0 (GP3)
address_offset : 0x880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank7 Word1 (GP3)
address_offset : 0x890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank7 Word2 (GP3)
address_offset : 0x8A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank7 Word3 (GP3)
address_offset : 0x8B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank7 Word4 (GP4)
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank7 Word5 (GP4)
address_offset : 0x8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank7 Word6 (GP4)
address_offset : 0x8E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
Value of OTP Bank7 Word7 (GP4)
address_offset : 0x8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write
OTP Controller Version Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STEP : STEP
bits : 0 - 15 (16 bit)
access : read-only
MINOR : MINOR
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : MAJOR
bits : 24 - 31 (8 bit)
access : read-only
OTP Controller Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : ADDR
bits : 0 - 5 (6 bit)
access : read-write
RSVD0 : RSVD0
bits : 6 - 7 (2 bit)
access : read-only
BUSY : BUSY
bits : 8 - 8 (1 bit)
access : read-only
ERROR : ERROR
bits : 9 - 9 (1 bit)
access : read-write
RELOAD_SHADOWS : RELOAD_SHADOWS
bits : 10 - 10 (1 bit)
access : read-write
CRC_TEST : CRC_TEST
bits : 11 - 11 (1 bit)
access : read-write
CRC_FAIL : CRC_FAIL
bits : 12 - 12 (1 bit)
access : read-write
RSVD1 : RSVD1
bits : 13 - 15 (3 bit)
access : read-only
WR_UNLOCK : WR_UNLOCK
bits : 16 - 31 (16 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.