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OCOTP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8F4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

TIMING

TIMING2

DATA

READ_CTRL

CTRL_SET

READ_FUSE_DATA

LOCK

CFG0

CFG1

CFG2

CFG3

CFG4

CFG5

CFG6

MEM0

MEM1

MEM2

MEM3

MEM4

ANA0

ANA1

ANA2

SW_STICKY

OTPMK0

OTPMK1

OTPMK2

OTPMK3

OTPMK4

OTPMK5

OTPMK6

OTPMK7

SRK0

SRK1

SRK2

SRK3

SRK4

SRK5

SRK6

SRK7

SCS

SJC_RESP0

SJC_RESP1

MAC0

MAC1

SCS_SET

MAC2

OTPMK_CRC32

GP1

GP2

SCS_CLR

SW_GP1

SW_GP20

SW_GP21

SW_GP22

SCS_TOG

SW_GP23

MISC_CONF0

MISC_CONF1

SRK_REVOKE

CRC_ADDR

CTRL_CLR

CRC_VALUE

ROM_PATCH0

ROM_PATCH1

ROM_PATCH2

ROM_PATCH3

ROM_PATCH4

ROM_PATCH5

ROM_PATCH6

ROM_PATCH7

GP30

GP31

GP32

GP33

GP40

GP41

GP42

GP43

VERSION

CTRL_TOG


CTRL

OTP Controller Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR RSVD0 BUSY ERROR RELOAD_SHADOWS CRC_TEST CRC_FAIL RSVD1 WR_UNLOCK

ADDR : ADDR
bits : 0 - 5 (6 bit)
access : read-write

RSVD0 : RSVD0
bits : 6 - 7 (2 bit)
access : read-only

BUSY : BUSY
bits : 8 - 8 (1 bit)
access : read-only

ERROR : ERROR
bits : 9 - 9 (1 bit)
access : read-write

RELOAD_SHADOWS : RELOAD_SHADOWS
bits : 10 - 10 (1 bit)
access : read-write

CRC_TEST : CRC_TEST
bits : 11 - 11 (1 bit)
access : read-write

CRC_FAIL : CRC_FAIL
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : RSVD1
bits : 13 - 15 (3 bit)
access : read-only

WR_UNLOCK : WR_UNLOCK
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0x3E77 : KEY

Key needed to unlock HW_OCOTP_DATA register.

End of enumeration elements list.


TIMING

OTP Controller Timing Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMING TIMING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STROBE_PROG RELAX STROBE_READ WAIT RSRVD0

STROBE_PROG : STROBE_PROG
bits : 0 - 11 (12 bit)
access : read-write

RELAX : RELAX
bits : 12 - 15 (4 bit)
access : read-write

STROBE_READ : STROBE_READ
bits : 16 - 21 (6 bit)
access : read-write

WAIT : WAIT
bits : 22 - 27 (6 bit)
access : read-write

RSRVD0 : RSRVD0
bits : 28 - 31 (4 bit)
access : read-only


TIMING2

OTP Controller Timing Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMING2 TIMING2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RELAX_PROG RSRVD0 RELAX_READ RSRVD1

RELAX_PROG : RELAX_PROG
bits : 0 - 11 (12 bit)
access : read-write

RSRVD0 : RSRVD0
bits : 12 - 15 (4 bit)
access : read-only

RELAX_READ : RELAX_READ
bits : 16 - 21 (6 bit)
access : read-write

RSRVD1 : RSRVD0
bits : 22 - 31 (10 bit)
access : read-only


DATA

OTP Controller Write Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 31 (32 bit)
access : read-write


READ_CTRL

OTP Controller Write Data Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

READ_CTRL READ_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_FUSE RSVD0

READ_FUSE : READ_FUSE
bits : 0 - 0 (1 bit)
access : read-write

RSVD0 : RSVD0
bits : 1 - 31 (31 bit)
access : read-only


CTRL_SET

OTP Controller Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_SET CTRL_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR RSVD0 BUSY ERROR RELOAD_SHADOWS CRC_TEST CRC_FAIL RSVD1 WR_UNLOCK

ADDR : ADDR
bits : 0 - 5 (6 bit)
access : read-write

RSVD0 : RSVD0
bits : 6 - 7 (2 bit)
access : read-only

BUSY : BUSY
bits : 8 - 8 (1 bit)
access : read-only

ERROR : ERROR
bits : 9 - 9 (1 bit)
access : read-write

RELOAD_SHADOWS : RELOAD_SHADOWS
bits : 10 - 10 (1 bit)
access : read-write

CRC_TEST : CRC_TEST
bits : 11 - 11 (1 bit)
access : read-write

CRC_FAIL : CRC_FAIL
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : RSVD1
bits : 13 - 15 (3 bit)
access : read-only

WR_UNLOCK : WR_UNLOCK
bits : 16 - 31 (16 bit)
access : read-write


READ_FUSE_DATA

OTP Controller Read Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

READ_FUSE_DATA READ_FUSE_DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 31 (32 bit)
access : read-write


LOCK

Value of OTP Bank0 Word0 (Lock controls)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TESTER BOOT_CFG MEM_TRIM SJC_RESP GP4_RLOCK MAC_ADDR GP1 GP2 ROM_PATCH SW_GP1 OTPMK ANALOG OTPMK_CRC SW_GP2_LOCK MISC_CONF SW_GP2_RLOCK GP4 GP3 FIELD_RETURN

TESTER : TESTER
bits : 0 - 1 (2 bit)
access : read-only

BOOT_CFG : BOOT_CFG
bits : 2 - 3 (2 bit)
access : read-only

MEM_TRIM : MEM_TRIM
bits : 4 - 5 (2 bit)
access : read-only

SJC_RESP : SJC_RESP
bits : 6 - 6 (1 bit)
access : read-only

GP4_RLOCK : GP4_RLOCK
bits : 7 - 7 (1 bit)
access : read-only

MAC_ADDR : MAC_ADDR
bits : 8 - 9 (2 bit)
access : read-only

GP1 : GP1
bits : 10 - 11 (2 bit)
access : read-only

GP2 : GP2
bits : 12 - 13 (2 bit)
access : read-only

ROM_PATCH : ROM_PATCH
bits : 15 - 15 (1 bit)
access : read-only

SW_GP1 : SW_GP1
bits : 16 - 16 (1 bit)
access : read-only

OTPMK : OTPMK
bits : 17 - 17 (1 bit)
access : read-only

ANALOG : ANALOG
bits : 18 - 19 (2 bit)
access : read-only

OTPMK_CRC : OTPMK_CRC
bits : 20 - 20 (1 bit)
access : read-only

SW_GP2_LOCK : SW_GP2_LOCK
bits : 21 - 21 (1 bit)
access : read-only

MISC_CONF : MISC_CONF
bits : 22 - 22 (1 bit)
access : read-only

SW_GP2_RLOCK : SW_GP2_RLOCK
bits : 23 - 23 (1 bit)
access : read-only

GP4 : GP4
bits : 24 - 25 (2 bit)
access : read-only

GP3 : GP3
bits : 26 - 27 (2 bit)
access : read-only

FIELD_RETURN : FIELD_RETURN
bits : 28 - 31 (4 bit)
access : read-write


CFG0

Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.)
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG0 CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


CFG1

Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.)
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG1 CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


CFG2

Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.)
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG2 CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


CFG3

Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.)
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG3 CFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


CFG4

Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.)
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG4 CFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


CFG5

Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.)
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG5 CFG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


CFG6

Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.)
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG6 CFG6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


MEM0

Value of OTP Bank1 Word0 (Memory Related Info.)
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM0 MEM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


MEM1

Value of OTP Bank1 Word1 (Memory Related Info.)
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM1 MEM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


MEM2

Value of OTP Bank1 Word2 (Memory Related Info.)
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM2 MEM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


MEM3

Value of OTP Bank1 Word3 (Memory Related Info.)
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM3 MEM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


MEM4

Value of OTP Bank1 Word4 (Memory Related Info.)
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM4 MEM4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


ANA0

Value of OTP Bank1 Word5 (Memory Related Info.)
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANA0 ANA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


ANA1

Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.)
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANA1 ANA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


ANA2

Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.)
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANA2 ANA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


SW_STICKY

Sticky bit Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_STICKY SW_STICKY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLOCK_DTCP_KEY SRK_REVOKE_LOCK FIELD_RETURN_LOCK BLOCK_ROM_PART JTAG_BLOCK_RELEASE RSVD0

BLOCK_DTCP_KEY : BLOCK_DTCP_KEY
bits : 0 - 0 (1 bit)
access : read-write

SRK_REVOKE_LOCK : SRK_REVOKE_LOCK
bits : 1 - 1 (1 bit)
access : read-write

FIELD_RETURN_LOCK : FIELD_RETURN_LOCK
bits : 2 - 2 (1 bit)
access : read-write

BLOCK_ROM_PART : BLOCK_ROM_PART
bits : 3 - 3 (1 bit)
access : read-write

JTAG_BLOCK_RELEASE : JTAG_BLOCK_RELEASE
bits : 4 - 4 (1 bit)
access : read-write

RSVD0 : RSVD0
bits : 5 - 31 (27 bit)
access : read-only


OTPMK0

Value of OTP Bank2 Word0 (OTPMK Key)
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK0 OTPMK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


OTPMK1

Value of OTP Bank2 Word1 (OTPMK Key)
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK1 OTPMK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


OTPMK2

Value of OTP Bank2 Word2 (OTPMK Key)
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK2 OTPMK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


OTPMK3

Value of OTP Bank2 Word3 (OTPMK Key)
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK3 OTPMK3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


OTPMK4

Value of OTP Bank2 Word4 (OTPMK Key)
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK4 OTPMK4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


OTPMK5

Value of OTP Bank2 Word5 (OTPMK Key)
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK5 OTPMK5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


OTPMK6

Value of OTP Bank2 Word6 (OTPMK Key)
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK6 OTPMK6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


OTPMK7

Value of OTP Bank2 Word7 (OTPMK Key)
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK7 OTPMK7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


SRK0

Shadow Register for OTP Bank3 Word0 (SRK Hash)
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK0 SRK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


SRK1

Shadow Register for OTP Bank3 Word1 (SRK Hash)
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK1 SRK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


SRK2

Shadow Register for OTP Bank3 Word2 (SRK Hash)
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK2 SRK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


SRK3

Shadow Register for OTP Bank3 Word3 (SRK Hash)
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK3 SRK3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


SRK4

Shadow Register for OTP Bank3 Word4 (SRK Hash)
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK4 SRK4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


SRK5

Shadow Register for OTP Bank3 Word5 (SRK Hash)
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK5 SRK5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


SRK6

Shadow Register for OTP Bank3 Word6 (SRK Hash)
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK6 SRK6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


SRK7

Shadow Register for OTP Bank3 Word7 (SRK Hash)
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK7 SRK7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


SCS

Software Controllable Signals Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCS SCS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAB_JDE SPARE LOCK

HAB_JDE : HAB_JDE
bits : 0 - 0 (1 bit)
access : read-write

SPARE : SPARE
bits : 1 - 30 (30 bit)
access : read-write

LOCK : LOCK
bits : 31 - 31 (1 bit)
access : read-write


SJC_RESP0

Value of OTP Bank4 Word0 (Secure JTAG Response Field)
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SJC_RESP0 SJC_RESP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


SJC_RESP1

Value of OTP Bank4 Word1 (Secure JTAG Response Field)
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SJC_RESP1 SJC_RESP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


MAC0

Value of OTP Bank4 Word2 (MAC Address)
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC0 MAC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


MAC1

Value of OTP Bank4 Word3 (MAC Address)
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC1 MAC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


SCS_SET

Software Controllable Signals Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCS_SET SCS_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAB_JDE SPARE LOCK

HAB_JDE : HAB_JDE
bits : 0 - 0 (1 bit)
access : read-write

SPARE : SPARE
bits : 1 - 30 (30 bit)
access : read-write

LOCK : LOCK
bits : 31 - 31 (1 bit)
access : read-write


MAC2

Value of OTP Bank4 Word4 (MAC2 Address)
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC2 MAC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


OTPMK_CRC32

Value of OTP Bank4 Word5 (CRC Key)
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK_CRC32 OTPMK_CRC32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


GP1

Value of OTP Bank4 Word6 (General Purpose Customer Defined Info)
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP1 GP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


GP2

Value of OTP Bank4 Word7 (General Purpose Customer Defined Info)
address_offset : 0x670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP2 GP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


SCS_CLR

Software Controllable Signals Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCS_CLR SCS_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAB_JDE SPARE LOCK

HAB_JDE : HAB_JDE
bits : 0 - 0 (1 bit)
access : read-write

SPARE : SPARE
bits : 1 - 30 (30 bit)
access : read-write

LOCK : LOCK
bits : 31 - 31 (1 bit)
access : read-write


SW_GP1

Value of OTP Bank5 Word0 (SW GP1)
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_GP1 SW_GP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


SW_GP20

Value of OTP Bank5 Word1 (SW GP2)
address_offset : 0x690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_GP20 SW_GP20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


SW_GP21

Value of OTP Bank5 Word2 (SW GP2)
address_offset : 0x6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_GP21 SW_GP21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


SW_GP22

Value of OTP Bank5 Word3 (SW GP2)
address_offset : 0x6B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_GP22 SW_GP22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


SCS_TOG

Software Controllable Signals Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCS_TOG SCS_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAB_JDE SPARE LOCK

HAB_JDE : HAB_JDE
bits : 0 - 0 (1 bit)
access : read-write

SPARE : SPARE
bits : 1 - 30 (30 bit)
access : read-write

LOCK : LOCK
bits : 31 - 31 (1 bit)
access : read-write


SW_GP23

Value of OTP Bank5 Word4 (SW GP2)
address_offset : 0x6C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_GP23 SW_GP23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


MISC_CONF0

Value of OTP Bank5 Word5 (Misc Conf)
address_offset : 0x6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MISC_CONF0 MISC_CONF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


MISC_CONF1

Value of OTP Bank5 Word6 (Misc Conf)
address_offset : 0x6E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MISC_CONF1 MISC_CONF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


SRK_REVOKE

Value of OTP Bank5 Word7 (SRK Revoke)
address_offset : 0x6F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK_REVOKE SRK_REVOKE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


CRC_ADDR

OTP Controller CRC test address
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC_ADDR CRC_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_START_ADDR DATA_END_ADDR CRC_ADDR OTPMK_CRC RSVD0

DATA_START_ADDR : DATA_START_ADDR
bits : 0 - 7 (8 bit)
access : read-write

DATA_END_ADDR : DATA_END_ADDR
bits : 8 - 15 (8 bit)
access : read-write

CRC_ADDR : CRC_ADDR
bits : 16 - 23 (8 bit)
access : read-write

OTPMK_CRC : OTPMK_CRC
bits : 24 - 24 (1 bit)
access : read-write

RSVD0 : RSVD0
bits : 25 - 31 (7 bit)
access : read-only


CTRL_CLR

OTP Controller Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_CLR CTRL_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR RSVD0 BUSY ERROR RELOAD_SHADOWS CRC_TEST CRC_FAIL RSVD1 WR_UNLOCK

ADDR : ADDR
bits : 0 - 5 (6 bit)
access : read-write

RSVD0 : RSVD0
bits : 6 - 7 (2 bit)
access : read-only

BUSY : BUSY
bits : 8 - 8 (1 bit)
access : read-only

ERROR : ERROR
bits : 9 - 9 (1 bit)
access : read-write

RELOAD_SHADOWS : RELOAD_SHADOWS
bits : 10 - 10 (1 bit)
access : read-write

CRC_TEST : CRC_TEST
bits : 11 - 11 (1 bit)
access : read-write

CRC_FAIL : CRC_FAIL
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : RSVD1
bits : 13 - 15 (3 bit)
access : read-only

WR_UNLOCK : WR_UNLOCK
bits : 16 - 31 (16 bit)
access : read-write


CRC_VALUE

OTP Controller CRC Value Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC_VALUE CRC_VALUE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 31 (32 bit)
access : read-write


ROM_PATCH0

Value of OTP Bank6 Word0 (ROM Patch)
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROM_PATCH0 ROM_PATCH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


ROM_PATCH1

Value of OTP Bank6 Word1 (ROM Patch)
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROM_PATCH1 ROM_PATCH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


ROM_PATCH2

Value of OTP Bank6 Word2 (ROM Patch)
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROM_PATCH2 ROM_PATCH2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


ROM_PATCH3

Value of OTP Bank6 Word3 (ROM Patch)
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROM_PATCH3 ROM_PATCH3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


ROM_PATCH4

Value of OTP Bank6 Word4 (ROM Patch)
address_offset : 0x840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROM_PATCH4 ROM_PATCH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


ROM_PATCH5

Value of OTP Bank6 Word5 (ROM Patch)
address_offset : 0x850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROM_PATCH5 ROM_PATCH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


ROM_PATCH6

Value of OTP Bank6 Word6 (ROM Patch)
address_offset : 0x860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROM_PATCH6 ROM_PATCH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


ROM_PATCH7

Value of OTP Bank6 Word7 (ROM Patch)
address_offset : 0x870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROM_PATCH7 ROM_PATCH7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


GP30

Value of OTP Bank7 Word0 (GP3)
address_offset : 0x880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP30 GP30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


GP31

Value of OTP Bank7 Word1 (GP3)
address_offset : 0x890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP31 GP31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


GP32

Value of OTP Bank7 Word2 (GP3)
address_offset : 0x8A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP32 GP32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


GP33

Value of OTP Bank7 Word3 (GP3)
address_offset : 0x8B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP33 GP33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


GP40

Value of OTP Bank7 Word4 (GP4)
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP40 GP40 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


GP41

Value of OTP Bank7 Word5 (GP4)
address_offset : 0x8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP41 GP41 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


GP42

Value of OTP Bank7 Word6 (GP4)
address_offset : 0x8E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP42 GP42 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


GP43

Value of OTP Bank7 Word7 (GP4)
address_offset : 0x8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP43 GP43 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : BITS
bits : 0 - 31 (32 bit)
access : read-write


VERSION

OTP Controller Version Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STEP MINOR MAJOR

STEP : STEP
bits : 0 - 15 (16 bit)
access : read-only

MINOR : MINOR
bits : 16 - 23 (8 bit)
access : read-only

MAJOR : MAJOR
bits : 24 - 31 (8 bit)
access : read-only


CTRL_TOG

OTP Controller Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_TOG CTRL_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR RSVD0 BUSY ERROR RELOAD_SHADOWS CRC_TEST CRC_FAIL RSVD1 WR_UNLOCK

ADDR : ADDR
bits : 0 - 5 (6 bit)
access : read-write

RSVD0 : RSVD0
bits : 6 - 7 (2 bit)
access : read-only

BUSY : BUSY
bits : 8 - 8 (1 bit)
access : read-only

ERROR : ERROR
bits : 9 - 9 (1 bit)
access : read-write

RELOAD_SHADOWS : RELOAD_SHADOWS
bits : 10 - 10 (1 bit)
access : read-write

CRC_TEST : CRC_TEST
bits : 11 - 11 (1 bit)
access : read-write

CRC_FAIL : CRC_FAIL
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : RSVD1
bits : 13 - 15 (3 bit)
access : read-only

WR_UNLOCK : WR_UNLOCK
bits : 16 - 31 (16 bit)
access : read-write



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