Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected
Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0INT : Interrupt flag for match channel 0.
bits : 0 - 0 (1 bit)
MR1INT : Interrupt flag for match channel 1.
bits : 1 - 2 (2 bit)
MR2INT : Interrupt flag for match channel 2.
bits : 2 - 4 (3 bit)
MR3INT : Interrupt flag for match channel 3.
bits : 3 - 6 (4 bit)
CR0INT : Interrupt flag for capture channel 0 event.
bits : 4 - 8 (5 bit)
CR1INT : Interrupt flag for capture channel 1 event.
bits : 5 - 10 (6 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 6 - 37 (32 bit)
Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC : Prescale counter value.
bits : 0 - 31 (32 bit)
Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0I : Interrupt on MR0
bits : 0 - 0 (1 bit)
Enumeration: ENUM
1 : INTERRUPT_IS_GENERAT
Interrupt is generated when MR0 matches the value in the TC.
0 : INTERRUPT_IS_DISABLE
Interrupt is disabled
End of enumeration elements list.
MR0R : Reset on MR0
bits : 1 - 2 (2 bit)
Enumeration: ENUM
1 : TC_WILL_BE_RESET_IF_
TC will be reset if MR0 matches it.
0 : FEATURE_DISABLED_
Feature disabled.
End of enumeration elements list.
MR0S : Stop on MR0
bits : 2 - 4 (3 bit)
Enumeration: ENUM
1 : TC_AND_PC_WILL_BE_ST
TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
0 : FEATURE_DISABLED_
Feature disabled.
End of enumeration elements list.
MR1I : Interrupt on MR1
bits : 3 - 6 (4 bit)
Enumeration: ENUM
1 : INTERRUPT_IS_GENERAT
Interrupt is generated when MR1 matches the value in the TC.
0 : INTERRUPT_IS_DISABLE
Interrupt is disabled.
End of enumeration elements list.
MR1R : Reset on MR1
bits : 4 - 8 (5 bit)
Enumeration: ENUM
1 : TC_WILL_BE_RESET_IF_
TC will be reset if MR1 matches it.
0 : FEATURE_DISABLED_
Feature disabled.
End of enumeration elements list.
MR1S : Stop on MR1
bits : 5 - 10 (6 bit)
Enumeration: ENUM
1 : TC_AND_PC_WILL_BE_ST
TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
0 : FEATURE_DISABLED_
Feature disabled.
End of enumeration elements list.
MR2I : Interrupt on MR2
bits : 6 - 12 (7 bit)
Enumeration: ENUM
1 : INTERRUPT_IS_GENERAT
Interrupt is generated when MR2 matches the value in the TC.
0 : INTERRUPT_IS_DISABLE
Interrupt is disabled
End of enumeration elements list.
MR2R : Reset on MR2
bits : 7 - 14 (8 bit)
Enumeration: ENUM
1 : TC_WILL_BE_RESET_IF_
TC will be reset if MR2 matches it.
0 : FEATURE_DISABLED_
Feature disabled.
End of enumeration elements list.
MR2S : Stop on MR2.
bits : 8 - 16 (9 bit)
Enumeration: ENUM
1 : TC_AND_PC_WILL_BE_ST
TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC
0 : FEATURE_DISABLED_
Feature disabled.
End of enumeration elements list.
MR3I : Interrupt on MR3
bits : 9 - 18 (10 bit)
Enumeration: ENUM
1 : INTERRUPT_IS_GENERAT
Interrupt is generated when MR3 matches the value in the TC.
0 : THIS_INTERRUPT_IS_DI
This interrupt is disabled
End of enumeration elements list.
MR3R : Reset on MR3
bits : 10 - 20 (11 bit)
Enumeration: ENUM
1 : TC_WILL_BE_RESET_IF_
TC will be reset if MR3 matches it.
0 : FEATURE_DISABLED_
Feature disabled.
End of enumeration elements list.
MR3S : Stop on MR3
bits : 11 - 22 (12 bit)
Enumeration: ENUM
1 : TC_AND_PC_WILL_BE_ST
TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
0 : FEATURE_DISABLED_
Feature disabled.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 12 - 43 (32 bit)
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAP0RE : Capture on CAPn.0 rising edge
bits : 0 - 0 (1 bit)
Enumeration: ENUM
1 : ENABLE
A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC.
0 : DISABLE
This feature is disabled.
End of enumeration elements list.
CAP0FE : Capture on CAPn.0 falling edge
bits : 1 - 2 (2 bit)
Enumeration: ENUM
1 : ENABLE
A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC.
0 : DISABLE
This feature is disabled.
End of enumeration elements list.
CAP0I : Interrupt on CAPn.0 event
bits : 2 - 4 (3 bit)
Enumeration: ENUM
1 : ENABLE
A CR0 load due to a CAPn.0 event will generate an interrupt.
0 : DISABLE
This feature is disabled.
End of enumeration elements list.
CAP1RE : Capture on CAPn.1 rising edge
bits : 3 - 6 (4 bit)
Enumeration: ENUM
1 : ENABLE
A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC.
0 : DISABLE
This feature is disabled.
End of enumeration elements list.
CAP1FE : Capture on CAPn.1 falling edge
bits : 4 - 8 (5 bit)
Enumeration: ENUM
1 : ENABLE
A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC.
0 : DISABLE
This feature is disabled.
End of enumeration elements list.
CAP1I : Interrupt on CAPn.1 event
bits : 5 - 10 (6 bit)
Enumeration: ENUM
1 : ENABLE
A CR1 load due to a CAPn.1 event will generate an interrupt.
0 : DISABLE
This feature is disabled.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 6 - 37 (32 bit)
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP : Timer counter capture value.
bits : 0 - 31 (32 bit)
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP : Timer counter capture value.
bits : 0 - 31 (32 bit)
External Match Register. The EMR controls the external match pins.
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM0 : External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).
bits : 0 - 0 (1 bit)
EM1 : External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high).
bits : 1 - 2 (2 bit)
EM2 : External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).
bits : 2 - 4 (3 bit)
EM3 : External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).
bits : 3 - 6 (4 bit)
EMC0 : External Match Control 0. Determines the functionality of External Match 0.
bits : 4 - 9 (6 bit)
Enumeration: ENUM
0x0 : DO_NOTHING_
Do Nothing.
0x1 : CLEAR_THE_CORRESPOND
Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).
0x2 : SET_THE_CORRESPONDIN
Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).
0x3 : TOGGLE_THE_CORRESPON
Toggle the corresponding External Match bit/output.
End of enumeration elements list.
EMC1 : External Match Control 1. Determines the functionality of External Match 1.
bits : 6 - 13 (8 bit)
Enumeration: ENUM
0x0 : DO_NOTHING_
Do Nothing.
0x1 : CLEAR_THE_CORRESPOND
Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).
0x2 : SET_THE_CORRESPONDIN
Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).
0x3 : TOGGLE_THE_CORRESPON
Toggle the corresponding External Match bit/output.
End of enumeration elements list.
EMC2 : External Match Control 2. Determines the functionality of External Match 2.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : DO_NOTHING_
Do Nothing.
0x1 : CLEAR_THE_CORRESPOND
Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).
0x2 : SET_THE_CORRESPONDIN
Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).
0x3 : TOGGLE_THE_CORRESPON
Toggle the corresponding External Match bit/output.
End of enumeration elements list.
EMC3 : External Match Control 3. Determines the functionality of External Match 3.
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : DO_NOTHING_
Do Nothing.
0x1 : CLEAR_THE_CORRESPOND
Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).
0x2 : SET_THE_CORRESPONDIN
Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).
0x3 : TOGGLE_THE_CORRESPON
Toggle the corresponding External Match bit/output.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 12 - 43 (32 bit)
Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
bits : 0 - 0 (1 bit)
CRST : When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
bits : 1 - 2 (2 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 2 - 33 (32 bit)
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
address_offset : 0x58 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP : Timer counter capture value.
bits : 0 - 31 (32 bit)
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTMODE : Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.
bits : 0 - 1 (2 bit)
Enumeration: ENUM
0x0 : TIMER_MODE_EVERY_RI
Timer Mode: every rising PCLK edge
0x1 : RISING
Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.
0x2 : FALLING
Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.
0x3 : DUALEDGE
Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.
End of enumeration elements list.
CINSEL : Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.
bits : 2 - 5 (4 bit)
Enumeration: ENUM
0x0 : CAPN_0_FOR_TIMERN
CAPn.0 for TIMERn
0x1 : CAPN_1_FOR_TIMERN
CAPn.1 for TIMERn
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 4 - 35 (32 bit)
Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Timer counter value.
bits : 0 - 31 (32 bit)
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
address_offset : 0x88 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP : Timer counter capture value.
bits : 0 - 31 (32 bit)
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PM : Prescale counter maximum value.
bits : 0 - 31 (32 bit)
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