Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected
DLAB =0 Receiver Buffer Register. Contains the next received character to be read.
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RBR : The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO.
bits : 0 - 7 (8 bit)
RESERVED : Reserved, the value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)
DLAB =0. Transmit Holding Register. The next character to be transmitted is written here.
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
alternate_register : RBR
reset_Mask : 0x0
THR : Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available.
bits : 0 - 7 (8 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 8 - 39 (32 bit)
DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : RBR
reset_Mask : 0x0
DLLSB : The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1.
bits : 0 - 7 (8 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 8 - 39 (32 bit)
Modem Control Register. Contains controls for flow control handshaking and loopback mode.
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRCTRL : DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active.
bits : 0 - 0 (1 bit)
RTSCTRL : RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active.
bits : 1 - 2 (2 bit)
LMS : Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : DISABLE_MODEM_LOOPBA
Disable modem loopback mode.
1 : ENABLE_MODEM_LOOPBAC
Enable modem loopback mode.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 5 - 10 (6 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 5 - 10 (6 bit)
RTSEN : RTS enable.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : DISABLE_AUTO_RTS_FLO
Disable auto-rts flow control.
1 : ENABLE_AUTO_RTS_FLOW
Enable auto-rts flow control.
End of enumeration elements list.
CTSEN : CTS enable.
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : DISABLE_AUTO_CTS_FLO
Disable auto-cts flow control.
1 : ENABLE_AUTO_CTS_FLOW
Enable auto-cts flow control.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)
Line Status Register. Contains flags for transmit and receive status, including line errors.
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : EMPTY
The UART1 receiver FIFO is empty.
1 : NOTEMPTY
The UART1 receiver FIFO is not empty.
End of enumeration elements list.
OE : Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : INACTIVE
Overrun error status is inactive.
1 : ACTIVE
Overrun error status is active.
End of enumeration elements list.
PE : Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : INACTIVE
Parity error status is inactive.
1 : ACTIVE
Parity error status is active.
End of enumeration elements list.
FE : Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : INACTIVE
Framing error status is inactive.
1 : ACTIVE
Framing error status is active.
End of enumeration elements list.
BI : Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : INACTIVE
Break interrupt status is inactive.
1 : ACTIVE
Break interrupt status is active.
End of enumeration elements list.
THRE : Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : VALID
THR contains valid data.
1 : THR_IS_EMPTY_
THR is empty.
End of enumeration elements list.
TEMT : Transmitter Empty. TEMT is set when both THR and TSR are empty TEMT is cleared when either the TSR or the THR contain valid data.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : VALID
THR and/or the TSR contains valid data.
1 : EMPTY
THR and the TSR are empty.
End of enumeration elements list.
RXFE : Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : NOERROR
RBR contains no UART1 RX errors or FCR[0]=0.
1 : ERRORS
UART1 RBR contains at least one UART1 RX error.
End of enumeration elements list.
RESERVED : Reserved, the value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)
Modem Status Register. Contains handshake signal status flags.
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCTS : Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_CHANGE_DETECTED_O
No change detected on modem input, CTS.
1 : STATE_CHANGE_DETECTE
State change detected on modem input, CTS.
End of enumeration elements list.
DDSR : Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : NO_CHANGE_DETECTED_O
No change detected on modem input, DSR.
1 : STATE_CHANGE_DETECTE
State change detected on modem input, DSR.
End of enumeration elements list.
TERI : Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NO_CHANGE_DETECTED_O
No change detected on modem input, RI.
1 : LOW_TO_HIGH_TRANSITI
Low-to-high transition detected on RI.
End of enumeration elements list.
DDCD : Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NO_CHANGE_DETECTED_O
No change detected on modem input, DCD.
1 : STATE_CHANGE_DETECTE
State change detected on modem input, DCD.
End of enumeration elements list.
CTS : Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode.
bits : 4 - 8 (5 bit)
DSR : Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode.
bits : 5 - 10 (6 bit)
RI : Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode.
bits : 6 - 12 (7 bit)
DCD : Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode.
bits : 7 - 14 (8 bit)
RESERVED : Reserved, the value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)
Scratch Pad Register. 8-bit temporary storage for software.
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Pad : A readable, writable byte.
bits : 0 - 7 (8 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 8 - 39 (32 bit)
Auto-baud Control Register. Contains controls for the auto-baud feature.
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Auto-baud start bit. This bit is automatically cleared after auto-baud completion.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : STOP
Auto-baud stop (auto-baud is not running).
1 : START
Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.
End of enumeration elements list.
MODE : Auto-baud mode select bit.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : MODE_0_
Mode 0.
1 : MODE_1_
Mode 1.
End of enumeration elements list.
AUTORESTART : Auto-baud restart bit.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NO_RESTART
No restart
1 : RESTART_IN_CASE_OF_T
Restart in case of time-out (counter restarts at next UART1 Rx falling edge)
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 3 - 10 (8 bit)
ABEOINTCLR : End of auto-baud interrupt clear bit (write-only).
bits : 8 - 16 (9 bit)
Enumeration: ENUM
0 : WRITING_A_0_HAS_NO_I
Writing a 0 has no impact.
1 : WRITING_A_1_WILL_CLE
Writing a 1 will clear the corresponding interrupt in the IIR.
End of enumeration elements list.
ABTOINTCLR : Auto-baud time-out interrupt clear bit (write-only).
bits : 9 - 18 (10 bit)
Enumeration: ENUM
0 : WRITING_A_0_HAS_NO_I
Writing a 0 has no impact.
1 : WRITING_A_1_WILL_CLE
Writing a 1 will clear the corresponding interrupt in the IIR.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 10 - 41 (32 bit)
Fractional Divider Register. Generates a clock input for the baud rate divider.
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVADDVAL : Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate.
bits : 0 - 3 (4 bit)
MULVAL : Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not.
bits : 4 - 11 (8 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 8 - 39 (32 bit)
Transmit Enable Register. Turns off UART transmitter for use with software flow control.
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 0 - 6 (7 bit)
TXEN : When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character.
bits : 7 - 14 (8 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 8 - 39 (32 bit)
DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLMSB : The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1.
bits : 0 - 7 (8 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 8 - 39 (32 bit)
DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : DLM
reset_Mask : 0x0
RBRIE : RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLE_THE_RDA_INTE
Disable the RDA interrupts.
1 : ENABLE_THE_RDA_INTER
Enable the RDA interrupts.
End of enumeration elements list.
THREIE : THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLE_THE_THRE_INT
Disable the THRE interrupts.
1 : ENABLE_THE_THRE_INTE
Enable the THRE interrupts.
End of enumeration elements list.
RXIE : RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : DISABLE_THE_RX_LINE_
Disable the RX line status interrupts.
1 : ENABLE_THE_RX_LINE_S
Enable the RX line status interrupts.
End of enumeration elements list.
MSIE : Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : DISABLE_THE_MODEM_IN
Disable the modem interrupt.
1 : ENABLE_THE_MODEM_INT
Enable the modem interrupt.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 4 - 10 (7 bit)
CTSIE : CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : DISABLE_THE_CTS_INTE
Disable the CTS interrupt.
1 : ENABLE_THE_CTS_INTER
Enable the CTS interrupt.
End of enumeration elements list.
ABEOIE : Enables the end of auto-baud interrupt.
bits : 8 - 16 (9 bit)
Enumeration: ENUM
0 : DISABLE_END_OF_AUTO_
Disable end of auto-baud Interrupt.
1 : ENABLE_END_OF_AUTO_B
Enable end of auto-baud Interrupt.
End of enumeration elements list.
ABTOIE : Enables the auto-baud time-out interrupt.
bits : 9 - 18 (10 bit)
Enumeration: ENUM
0 : DISABLE_AUTO_BAUD_TI
Disable auto-baud time-out Interrupt.
1 : ENABLE_AUTO_BAUD_TIM
Enable auto-baud time-out Interrupt.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 10 - 41 (32 bit)
RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMMEN : RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED_
Disabled.
1 : ENABLED_IN_THIS_MOD
Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt.
End of enumeration elements list.
RXDIS : Receive enable.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : ENABLED_
Enabled.
1 : DISABLED_
Disabled.
End of enumeration elements list.
AADEN : Auto Address Detect (AAD) enable.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : DISABLED_
Disabled.
1 : ENABLED_
Enabled.
End of enumeration elements list.
SEL : Direction control.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : RTS_IF_DIRECTION_CO
RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control.
1 : DTR_IF_DIRECTION_CO
DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.
End of enumeration elements list.
DCTRL : Direction control enable.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : DISABLE_AUTO_DIRECTI
Disable Auto Direction Control.
1 : ENABLE_AUTO_DIRECTIO
Enable Auto Direction Control.
End of enumeration elements list.
OINV : Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : LOW_THE_DIRECTION_C
LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.
1 : HIGH_THE_DIRECTION_
HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 6 - 37 (32 bit)
RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADRMATCH : Contains the address match value.
bits : 0 - 7 (8 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 8 - 39 (32 bit)
RS-485/EIA-485 direction control delay.
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.
bits : 0 - 7 (8 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 8 - 39 (32 bit)
Interrupt ID Register. Identifies which interrupt(s) are pending.
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTSTATUS : Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : AT_LEAST_ONE_INTERRU
At least one interrupt is pending.
1 : NO_INTERRUPT_IS_PEND
No interrupt is pending.
End of enumeration elements list.
INTID : Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).
bits : 1 - 4 (4 bit)
Enumeration: ENUM
0x3 : RLS
1 - Receive Line Status (RLS).
0x2 : RDA
2a - Receive Data Available (RDA).
0x6 : CTI
2b - Character Time-out Indicator (CTI).
0x1 : THRE
3 - THRE Interrupt.
0x0 : MODEM
4 - Modem Interrupt.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 4 - 9 (6 bit)
FIFOENABLE : Copies of FCR[0].
bits : 6 - 13 (8 bit)
ABEOINT : End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.
bits : 8 - 16 (9 bit)
ABTOINT : Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.
bits : 9 - 18 (10 bit)
RESERVED : Reserved, the value read from a reserved bit is not defined.
bits : 10 - 41 (32 bit)
FIFO Control Register. Controls UART1 FIFO usage and modes.
address_offset : 0x8 Bytes (0x0)
access : write-only
reset_value : 0x0
alternate_register : IIR
reset_Mask : 0x0
FIFOEN : FIFO enable.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : MUST_NOT_BE_USED_IN_
Must not be used in the application.
1 : ACTIVE_HIGH_ENABLE_F
Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs.
End of enumeration elements list.
RXFIFORES : RX FIFO Reset.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : NO_IMPACT_ON_EITHER_
No impact on either of UART1 FIFOs.
1 : WRITING_A_LOGIC_1_TO
Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing.
End of enumeration elements list.
TXFIFORES : TX FIFO Reset.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NO_IMPACT_ON_EITHER_
No impact on either of UART1 FIFOs.
1 : WRITING_A_LOGIC_1_TO
Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing.
End of enumeration elements list.
DMAMODE : DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1.
bits : 3 - 6 (4 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 4 - 9 (6 bit)
RXTRIGLVL : RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.
bits : 6 - 13 (8 bit)
Enumeration: ENUM
0x0 : TRIGGER_LEVEL_0_1_C
Trigger level 0 (1 character or 0x01).
0x1 : TRIGGER_LEVEL_1_4_C
Trigger level 1 (4 characters or 0x04).
0x2 : TRIGGER_LEVEL_2_8_C
Trigger level 2 (8 characters or 0x08).
0x3 : TRIGGER_LEVEL_3_14_
Trigger level 3 (14 characters or 0x0E).
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits.
bits : 8 - 39 (32 bit)
Line Control Register. Contains controls for frame formatting and break generation.
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WLS : Word Length Select.
bits : 0 - 1 (2 bit)
Enumeration: ENUM
0x0 : 5_BIT_CHARACTER_LENG
5-bit character length.
0x1 : 6_BIT_CHARACTER_LENG
6-bit character length.
0x2 : 7_BIT_CHARACTER_LENG
7-bit character length.
0x3 : 8_BIT_CHARACTER_LENG
8-bit character length.
End of enumeration elements list.
SBS : Stop Bit Select.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : 1_STOP_BIT_
1 stop bit.
1 : 2_STOP_BITS_1_5_IF_
2 stop bits (1.5 if LCR[1:0]=00).
End of enumeration elements list.
PE : Parity Enable.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : DISABLE_PARITY_GENER
Disable parity generation and checking.
1 : ENABLE_PARITY_GENERA
Enable parity generation and checking.
End of enumeration elements list.
PS : Parity Select.
bits : 4 - 9 (6 bit)
Enumeration: ENUM
0x0 : ODD_PARITY_NUMBER_O
Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.
0x1 : EVEN_PARITY_NUMBER_
Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.
0x2 : FORCED1STICK_PAR
Forced 1 stick parity.
0x3 : FORCED0STICK_PAR
Forced 0 stick parity.
End of enumeration elements list.
BC : Break Control.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : DISABLE_BREAK_TRANSM
Disable break transmission.
1 : ENABLE_BREAK_TRANSMI
Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high.
End of enumeration elements list.
DLAB : Divisor Latch Access Bit (DLAB)
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : DISABLE_ACCESS_TO_DI
Disable access to Divisor Latches.
1 : ENABLE_ACCESS_TO_DIV
Enable access to Divisor Latches.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)
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