CR0

CPSR

IMSC

RIS

MIS

ICR

DMACR

CR1

DR

SR

DSS : Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.
bits : 0 - 3 (4 bit)

Enumeration: ENUM

End of enumeration elements list.

FRF : Frame Format.
bits : 4 - 9 (6 bit)

Enumeration: ENUM

End of enumeration elements list.

CPOL : Clock Out Polarity. This bit is only used in SPI mode.
bits : 6 - 12 (7 bit)

Enumeration: ENUM

End of enumeration elements list.

CPHA : Clock Out Phase. This bit is only used in SPI mode.
bits : 7 - 14 (8 bit)

Enumeration: ENUM

End of enumeration elements list.

SCR : Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]).
bits : 8 - 23 (16 bit)

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 16 - 47 (32 bit)

CPSDVSR : This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.
bits : 0 - 7 (8 bit)

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)

RORIM : Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
bits : 0 - 0 (1 bit)

RTIM : Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).
bits : 1 - 2 (2 bit)

RXIM : Software should set this bit to enable interrupt when the Rx FIFO is at least half full.
bits : 2 - 4 (3 bit)

TXIM : Software should set this bit to enable interrupt when the Tx FIFO is at least half empty.
bits : 3 - 6 (4 bit)

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 4 - 35 (32 bit)

RORRIS : This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
bits : 0 - 0 (1 bit)

RTRIS : This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).
bits : 1 - 2 (2 bit)

RXRIS : This bit is 1 if the Rx FIFO is at least half full.
bits : 2 - 4 (3 bit)

TXRIS : This bit is 1 if the Tx FIFO is at least half empty.
bits : 3 - 6 (4 bit)

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 4 - 35 (32 bit)

RORMIS : This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.
bits : 0 - 0 (1 bit)

RTMIS : This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).
bits : 1 - 2 (2 bit)

RXMIS : This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled.
bits : 2 - 4 (3 bit)

TXMIS : This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.
bits : 3 - 6 (4 bit)

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 4 - 35 (32 bit)

RORIC : Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt.
bits : 0 - 0 (1 bit)

RTIC : Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]).
bits : 1 - 2 (2 bit)

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 2 - 33 (32 bit)

RXDMAE : Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled.
bits : 0 - 0 (1 bit)

TXDMAE : Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled
bits : 1 - 2 (2 bit)

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 2 - 33 (32 bit)

LBM : Loop Back Mode.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

End of enumeration elements list.

SSE : SSP Enable.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

End of enumeration elements list.

MS : Master/Slave Mode.This bit can only be written when the SSE bit is 0.
bits : 2 - 4 (3 bit)

Enumeration: ENUM

End of enumeration elements list.

SOD : Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO).
bits : 3 - 6 (4 bit)

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 4 - 35 (32 bit)

DATA : Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s.
bits : 0 - 15 (16 bit)

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 16 - 47 (32 bit)

TFE : Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.
bits : 0 - 0 (1 bit)

TNF : Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.
bits : 1 - 2 (2 bit)

RNE : Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.
bits : 2 - 4 (3 bit)

RFF : Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.
bits : 3 - 6 (4 bit)

BSY : Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.
bits : 4 - 8 (5 bit)

RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 5 - 36 (32 bit)