INTSTAT

INTERRCLR

SRCADDR0

DESTADDR0

LLI0

CONTROL0

CONFIG0

SRCADDR1

DESTADDR1

LLI1

CONTROL1

CONFIG1

RAWINTTCSTAT

SRCADDR2

DESTADDR2

LLI2

CONTROL2

CONFIG2

SRCADDR3

DESTADDR3

LLI3

CONTROL3

CONFIG3

RAWINTERRSTAT

SRCADDR4

DESTADDR4

LLI4

CONTROL4

CONFIG4

SRCADDR5

DESTADDR5

LLI5

CONTROL5

CONFIG5

ENBLDCHNS

SRCADDR6

DESTADDR6

LLI6

CONTROL6

CONFIG6

SRCADDR7

DESTADDR7

LLI7

CONTROL7

CONFIG7

SOFTBREQ

SOFTSREQ

SOFTLBREQ

SOFTLSREQ

CONFIG

SYNC

INTTCSTAT

INTTCCLEAR

INTERRSTAT

INTSTAT0 : Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
bits : 0 - 0 (1 bit)

INTSTAT1 : Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
bits : 1 - 2 (2 bit)

INTSTAT2 : Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
bits : 2 - 4 (3 bit)

INTSTAT3 : Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
bits : 3 - 6 (4 bit)

INTSTAT4 : Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
bits : 4 - 8 (5 bit)

INTSTAT5 : Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
bits : 5 - 10 (6 bit)

INTSTAT6 : Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
bits : 6 - 12 (7 bit)

INTSTAT7 : Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
bits : 7 - 14 (8 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)

INTERRCLR0 : Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
bits : 0 - 0 (1 bit)

INTERRCLR1 : Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
bits : 1 - 2 (2 bit)

INTERRCLR2 : Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
bits : 2 - 4 (3 bit)

INTERRCLR3 : Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
bits : 3 - 6 (4 bit)

INTERRCLR4 : Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
bits : 4 - 8 (5 bit)

INTERRCLR5 : Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
bits : 5 - 10 (6 bit)

INTERRCLR6 : Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
bits : 6 - 12 (7 bit)

INTERRCLR7 : Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
bits : 7 - 14 (8 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 8 - 39 (32 bit)

SRCADDR : DMA source address. Reading this register will return the current source address.
bits : 0 - 31 (32 bit)

DESTADDR : DMA Destination address. Reading this register will return the current destination address.
bits : 0 - 31 (32 bit)

RESERVED : Reserved, and must be written as 0.
bits : 0 - 1 (2 bit)

LLI : Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.
bits : 2 - 33 (32 bit)

TRANSFERSIZE : Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller.
bits : 0 - 11 (12 bit)

SBSIZE : Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256
bits : 12 - 26 (15 bit)

DBSIZE : Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256
bits : 15 - 32 (18 bit)

SWIDTH : Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved
bits : 18 - 38 (21 bit)

DWIDTH : Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved
bits : 21 - 44 (24 bit)

RESERVED : Reserved, and must be written as 0.
bits : 24 - 49 (26 bit)

SI : Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer.
bits : 26 - 52 (27 bit)

DI : Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer.
bits : 27 - 54 (28 bit)

PROT1 : This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode.
bits : 28 - 56 (29 bit)

PROT2 : This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable.
bits : 29 - 58 (30 bit)

PROT3 : This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable.
bits : 30 - 60 (31 bit)

I : Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled.
bits : 31 - 62 (32 bit)

E : Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.
bits : 0 - 0 (1 bit)

SRCPERIPHERAL : Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification.
bits : 1 - 6 (6 bit)

DESTPERIPHERAL : Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification.
bits : 6 - 16 (11 bit)

TRANSFERTYPE : This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field.
bits : 11 - 24 (14 bit)

IE : Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel.
bits : 14 - 28 (15 bit)

ITC : Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel.
bits : 15 - 30 (16 bit)

L : Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x.
bits : 16 - 32 (17 bit)

A : Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit.
bits : 17 - 34 (18 bit)

H : Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.
bits : 18 - 36 (19 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)

SRCADDR : DMA source address. Reading this register will return the current source address.
bits : 0 - 31 (32 bit)

DESTADDR : DMA Destination address. Reading this register will return the current destination address.
bits : 0 - 31 (32 bit)

RESERVED : Reserved, and must be written as 0.
bits : 0 - 1 (2 bit)

LLI : Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.
bits : 2 - 33 (32 bit)

TRANSFERSIZE : Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller.
bits : 0 - 11 (12 bit)

SBSIZE : Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256
bits : 12 - 26 (15 bit)

DBSIZE : Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256
bits : 15 - 32 (18 bit)

SWIDTH : Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved
bits : 18 - 38 (21 bit)

DWIDTH : Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved
bits : 21 - 44 (24 bit)

RESERVED : Reserved, and must be written as 0.
bits : 24 - 49 (26 bit)

SI : Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer.
bits : 26 - 52 (27 bit)

DI : Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer.
bits : 27 - 54 (28 bit)

PROT1 : This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode.
bits : 28 - 56 (29 bit)

PROT2 : This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable.
bits : 29 - 58 (30 bit)

PROT3 : This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable.
bits : 30 - 60 (31 bit)

I : Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled.
bits : 31 - 62 (32 bit)

E : Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.
bits : 0 - 0 (1 bit)

SRCPERIPHERAL : Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification.
bits : 1 - 6 (6 bit)

DESTPERIPHERAL : Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification.
bits : 6 - 16 (11 bit)

TRANSFERTYPE : This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field.
bits : 11 - 24 (14 bit)

IE : Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel.
bits : 14 - 28 (15 bit)

ITC : Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel.
bits : 15 - 30 (16 bit)

L : Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x.
bits : 16 - 32 (17 bit)

A : Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit.
bits : 17 - 34 (18 bit)

H : Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.
bits : 18 - 36 (19 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)

RAWINTTCSTAT0 : Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
bits : 0 - 0 (1 bit)

RAWINTTCSTAT1 : Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
bits : 1 - 2 (2 bit)

RAWINTTCSTAT2 : Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
bits : 2 - 4 (3 bit)

RAWINTTCSTAT3 : Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
bits : 3 - 6 (4 bit)

RAWINTTCSTAT4 : Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
bits : 4 - 8 (5 bit)

RAWINTTCSTAT5 : Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
bits : 5 - 10 (6 bit)

RAWINTTCSTAT6 : Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
bits : 6 - 12 (7 bit)

RAWINTTCSTAT7 : Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
bits : 7 - 14 (8 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)

SRCADDR : DMA source address. Reading this register will return the current source address.
bits : 0 - 31 (32 bit)

DESTADDR : DMA Destination address. Reading this register will return the current destination address.
bits : 0 - 31 (32 bit)

RESERVED : Reserved, and must be written as 0.
bits : 0 - 1 (2 bit)

LLI : Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.
bits : 2 - 33 (32 bit)

TRANSFERSIZE : Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller.
bits : 0 - 11 (12 bit)

SBSIZE : Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256
bits : 12 - 26 (15 bit)

DBSIZE : Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256
bits : 15 - 32 (18 bit)

SWIDTH : Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved
bits : 18 - 38 (21 bit)

DWIDTH : Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved
bits : 21 - 44 (24 bit)

RESERVED : Reserved, and must be written as 0.
bits : 24 - 49 (26 bit)

SI : Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer.
bits : 26 - 52 (27 bit)

DI : Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer.
bits : 27 - 54 (28 bit)

PROT1 : This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode.
bits : 28 - 56 (29 bit)

PROT2 : This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable.
bits : 29 - 58 (30 bit)

PROT3 : This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable.
bits : 30 - 60 (31 bit)

I : Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled.
bits : 31 - 62 (32 bit)

E : Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.
bits : 0 - 0 (1 bit)

SRCPERIPHERAL : Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification.
bits : 1 - 6 (6 bit)

DESTPERIPHERAL : Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification.
bits : 6 - 16 (11 bit)

TRANSFERTYPE : This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field.
bits : 11 - 24 (14 bit)

IE : Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel.
bits : 14 - 28 (15 bit)

ITC : Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel.
bits : 15 - 30 (16 bit)

L : Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x.
bits : 16 - 32 (17 bit)

A : Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit.
bits : 17 - 34 (18 bit)

H : Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.
bits : 18 - 36 (19 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)

SRCADDR : DMA source address. Reading this register will return the current source address.
bits : 0 - 31 (32 bit)

DESTADDR : DMA Destination address. Reading this register will return the current destination address.
bits : 0 - 31 (32 bit)

RESERVED : Reserved, and must be written as 0.
bits : 0 - 1 (2 bit)

LLI : Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.
bits : 2 - 33 (32 bit)

TRANSFERSIZE : Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller.
bits : 0 - 11 (12 bit)

SBSIZE : Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256
bits : 12 - 26 (15 bit)

DBSIZE : Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256
bits : 15 - 32 (18 bit)

SWIDTH : Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved
bits : 18 - 38 (21 bit)

DWIDTH : Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved
bits : 21 - 44 (24 bit)

RESERVED : Reserved, and must be written as 0.
bits : 24 - 49 (26 bit)

SI : Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer.
bits : 26 - 52 (27 bit)

DI : Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer.
bits : 27 - 54 (28 bit)

PROT1 : This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode.
bits : 28 - 56 (29 bit)

PROT2 : This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable.
bits : 29 - 58 (30 bit)

PROT3 : This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable.
bits : 30 - 60 (31 bit)

I : Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled.
bits : 31 - 62 (32 bit)

E : Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.
bits : 0 - 0 (1 bit)

SRCPERIPHERAL : Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification.
bits : 1 - 6 (6 bit)

DESTPERIPHERAL : Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification.
bits : 6 - 16 (11 bit)

TRANSFERTYPE : This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field.
bits : 11 - 24 (14 bit)

IE : Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel.
bits : 14 - 28 (15 bit)

ITC : Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel.
bits : 15 - 30 (16 bit)

L : Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x.
bits : 16 - 32 (17 bit)

A : Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit.
bits : 17 - 34 (18 bit)

H : Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.
bits : 18 - 36 (19 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)

RAWINTERRSTAT0 : Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
bits : 0 - 0 (1 bit)

RAWINTERRSTAT1 : Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
bits : 1 - 2 (2 bit)

RAWINTERRSTAT2 : Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
bits : 2 - 4 (3 bit)

RAWINTERRSTAT3 : Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
bits : 3 - 6 (4 bit)

RAWINTERRSTAT4 : Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
bits : 4 - 8 (5 bit)

RAWINTERRSTAT5 : Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
bits : 5 - 10 (6 bit)

RAWINTERRSTAT6 : Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
bits : 6 - 12 (7 bit)

RAWINTERRSTAT7 : Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
bits : 7 - 14 (8 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)

SRCADDR : DMA source address. Reading this register will return the current source address.
bits : 0 - 31 (32 bit)

DESTADDR : DMA Destination address. Reading this register will return the current destination address.
bits : 0 - 31 (32 bit)

RESERVED : Reserved, and must be written as 0.
bits : 0 - 1 (2 bit)

LLI : Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.
bits : 2 - 33 (32 bit)

TRANSFERSIZE : Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller.
bits : 0 - 11 (12 bit)

SBSIZE : Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256
bits : 12 - 26 (15 bit)

DBSIZE : Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256
bits : 15 - 32 (18 bit)

SWIDTH : Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved
bits : 18 - 38 (21 bit)

DWIDTH : Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved
bits : 21 - 44 (24 bit)

RESERVED : Reserved, and must be written as 0.
bits : 24 - 49 (26 bit)

SI : Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer.
bits : 26 - 52 (27 bit)

DI : Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer.
bits : 27 - 54 (28 bit)

PROT1 : This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode.
bits : 28 - 56 (29 bit)

PROT2 : This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable.
bits : 29 - 58 (30 bit)

PROT3 : This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable.
bits : 30 - 60 (31 bit)

I : Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled.
bits : 31 - 62 (32 bit)

E : Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.
bits : 0 - 0 (1 bit)

SRCPERIPHERAL : Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification.
bits : 1 - 6 (6 bit)

DESTPERIPHERAL : Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification.
bits : 6 - 16 (11 bit)

TRANSFERTYPE : This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field.
bits : 11 - 24 (14 bit)

IE : Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel.
bits : 14 - 28 (15 bit)

ITC : Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel.
bits : 15 - 30 (16 bit)

L : Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x.
bits : 16 - 32 (17 bit)

A : Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit.
bits : 17 - 34 (18 bit)

H : Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.
bits : 18 - 36 (19 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)

SRCADDR : DMA source address. Reading this register will return the current source address.
bits : 0 - 31 (32 bit)

DESTADDR : DMA Destination address. Reading this register will return the current destination address.
bits : 0 - 31 (32 bit)

RESERVED : Reserved, and must be written as 0.
bits : 0 - 1 (2 bit)

LLI : Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.
bits : 2 - 33 (32 bit)

TRANSFERSIZE : Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller.
bits : 0 - 11 (12 bit)

SBSIZE : Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256
bits : 12 - 26 (15 bit)

DBSIZE : Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256
bits : 15 - 32 (18 bit)

SWIDTH : Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved
bits : 18 - 38 (21 bit)

DWIDTH : Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved
bits : 21 - 44 (24 bit)

RESERVED : Reserved, and must be written as 0.
bits : 24 - 49 (26 bit)

SI : Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer.
bits : 26 - 52 (27 bit)

DI : Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer.
bits : 27 - 54 (28 bit)

PROT1 : This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode.
bits : 28 - 56 (29 bit)

PROT2 : This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable.
bits : 29 - 58 (30 bit)

PROT3 : This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable.
bits : 30 - 60 (31 bit)

I : Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled.
bits : 31 - 62 (32 bit)

E : Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.
bits : 0 - 0 (1 bit)

SRCPERIPHERAL : Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification.
bits : 1 - 6 (6 bit)

DESTPERIPHERAL : Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification.
bits : 6 - 16 (11 bit)

TRANSFERTYPE : This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field.
bits : 11 - 24 (14 bit)

IE : Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel.
bits : 14 - 28 (15 bit)

ITC : Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel.
bits : 15 - 30 (16 bit)

L : Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x.
bits : 16 - 32 (17 bit)

A : Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit.
bits : 17 - 34 (18 bit)

H : Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.
bits : 18 - 36 (19 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)

ENABLEDCHANNELS0 : Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
bits : 0 - 0 (1 bit)

ENABLEDCHANNELS1 : Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
bits : 1 - 2 (2 bit)

ENABLEDCHANNELS2 : Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
bits : 2 - 4 (3 bit)

ENABLEDCHANNELS3 : Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
bits : 3 - 6 (4 bit)

ENABLEDCHANNELS4 : Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
bits : 4 - 8 (5 bit)

ENABLEDCHANNELS5 : Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
bits : 5 - 10 (6 bit)

ENABLEDCHANNELS6 : Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
bits : 6 - 12 (7 bit)

ENABLEDCHANNELS7 : Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
bits : 7 - 14 (8 bit)

RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)

SRCADDR : DMA source address. Reading this register will return the current source address.
bits : 0 - 31 (32 bit)

DESTADDR : DMA Destination address. Reading this register will return the current destination address.
bits : 0 - 31 (32 bit)

RESERVED : Reserved, and must be written as 0.
bits : 0 - 1 (2 bit)

LLI : Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.
bits : 2 - 33 (32 bit)

TRANSFERSIZE : Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller.
bits : 0 - 11 (12 bit)

SBSIZE : Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256
bits : 12 - 26 (15 bit)

DBSIZE : Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256
bits : 15 - 32 (18 bit)

SWIDTH : Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved
bits : 18 - 38 (21 bit)

DWIDTH : Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved
bits : 21 - 44 (24 bit)

RESERVED : Reserved, and must be written as 0.
bits : 24 - 49 (26 bit)

SI : Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer.
bits : 26 - 52 (27 bit)

DI : Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer.
bits : 27 - 54 (28 bit)

PROT1 : This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode.
bits : 28 - 56 (29 bit)

PROT2 : This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable.
bits : 29 - 58 (30 bit)

PROT3 : This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable.
bits : 30 - 60 (31 bit)

I : Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled.
bits : 31 - 62 (32 bit)

E : Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.
bits : 0 - 0 (1 bit)

SRCPERIPHERAL : Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification.
bits : 1 - 6 (6 bit)

DESTPERIPHERAL : Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification.
bits : 6 - 16 (11 bit)

TRANSFERTYPE : This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field.
bits : 11 - 24 (14 bit)

IE : Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel.
bits : 14 - 28 (15 bit)

ITC : Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel.
bits : 15 - 30 (16 bit)

L : Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x.
bits : 16 - 32 (17 bit)

A : Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit.
bits : 17 - 34 (18 bit)

H : Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.
bits : 18 - 36 (19 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)

SRCADDR : DMA source address. Reading this register will return the current source address.
bits : 0 - 31 (32 bit)

DESTADDR : DMA Destination address. Reading this register will return the current destination address.
bits : 0 - 31 (32 bit)