Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected
Capability register length
address_offset : 0x100 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPLENGTH : Indicates offset to add to the register base address at the beginning of the Operational Register
bits : 0 - 7 (8 bit)
HCIVERSION : BCD encoding of the EHCI revision number supported by this host controller.
bits : 8 - 31 (24 bit)
RESERVED : These bits are reserved and should be set to zero.
bits : 24 - 55 (32 bit)
Host controller structural parameters
address_offset : 0x104 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
N_PORTS : Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller.
bits : 0 - 3 (4 bit)
PPC : Port Power Control. This field indicates whether the host controller implementation includes port power control.
bits : 4 - 8 (5 bit)
N_PCC : Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller.
bits : 8 - 19 (12 bit)
N_CC : Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller.
bits : 12 - 27 (16 bit)
PI : Port indicators. This bit indicates whether the ports support port indicator control.
bits : 16 - 32 (17 bit)
RESERVED : These bits are reserved and should be set to zero.
bits : 17 - 36 (20 bit)
RESERVED : These bits are reserved and should be set to zero.
bits : 17 - 36 (20 bit)
N_PTT : Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller.
bits : 20 - 43 (24 bit)
N_TT : Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller.
bits : 24 - 51 (28 bit)
RESERVED : These bits are reserved and should be set to zero.
bits : 28 - 59 (32 bit)
Host controller capability parameters
address_offset : 0x108 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADC : 64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported.
bits : 0 - 0 (1 bit)
PFL : Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous.
bits : 1 - 2 (2 bit)
ASP : Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register.
bits : 2 - 4 (3 bit)
IST : Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule.
bits : 4 - 11 (8 bit)
EECP : EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list.
bits : 8 - 23 (16 bit)
RESERVED : These bits are reserved and should be set to zero.
bits : 16 - 47 (32 bit)
Device interface version number
address_offset : 0x120 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCIVERSION : The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register.
bits : 0 - 15 (16 bit)
RESERVED : These bits are reserved and should be set to zero.
bits : 16 - 47 (32 bit)
USB command (device mode)
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RS : Run/Stop
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DETACH
Writing a 0 to this bit will cause a detach event.
1 : ATACH
Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized.
End of enumeration elements list.
RST : Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : RESETCOMPLETE
Set to 0 by hardware when the reset process is complete.
1 : RESET
When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0.
End of enumeration elements list.
RESERVED : Not used in device mode.
bits : 4 - 8 (5 bit)
RESERVED : Not used in device mode.
bits : 5 - 10 (6 bit)
RESERVED : Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results.
bits : 6 - 12 (7 bit)
RESERVED : Reserved. These bits should be set to 0.
bits : 7 - 14 (8 bit)
RESERVED : Not used in Device mode.
bits : 8 - 17 (10 bit)
RESERVED : Reserved.These bits should be set to 0.
bits : 10 - 20 (11 bit)
RESERVED : Not used in Device mode.
bits : 11 - 22 (12 bit)
RESERVED : Reserved.These bits should be set to 0.
bits : 12 - 24 (13 bit)
RESERVED : Reserved.These bits should be set to 0.
bits : 12 - 24 (13 bit)
SUTW : Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10).
bits : 13 - 26 (14 bit)
ATDTW : Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized.
bits : 14 - 28 (15 bit)
FS2 : Not used in device mode.
bits : 15 - 30 (16 bit)
ITC : Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames.
bits : 16 - 39 (24 bit)
RESERVED : Reserved
bits : 24 - 55 (32 bit)
USB command (host mode)
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : USBCMD_D
reset_Mask : 0x0
RS : Run/Stop
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : HALT
When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one).
1 : PROCEED
When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one.
End of enumeration elements list.
RST : Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : RESETCOMPLETE
This bit is set to zero by hardware when the reset process is complete.
1 : RESET
When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior.
End of enumeration elements list.
FS0 : Bit 0 of the Frame List Size bits. See Table 281. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2.
bits : 2 - 4 (3 bit)
FS1 : Bit 1 of the Frame List Size bits. See Table 281
bits : 3 - 6 (4 bit)
PSE : This bit controls whether the host controller skips processing the periodic schedule.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : DO_NOT_PROCESS_THE_P
Do not process the periodic schedule.
1 : USE_THE_PERIODICLIST
Use the PERIODICLISTBASE register to access the periodic schedule.
End of enumeration elements list.
ASE : This bit controls whether the host controller skips processing the asynchronous schedule.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : DO_NOT_PROCESS_THE_A
Do not process the asynchronous schedule.
1 : USE_THE_ASYNCLISTADD
Use the ASYNCLISTADDR to access the asynchronous schedule.
End of enumeration elements list.
IAA : This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : ST
The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one.
1 : DOORBELL
Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results.
End of enumeration elements list.
ASP1_0 : Asynchronous schedule park mode. Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3. Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior.
bits : 8 - 17 (10 bit)
RESERVED : Reserved.
bits : 10 - 20 (11 bit)
ASPE : Asynchronous Schedule Park Mode Enable
bits : 11 - 22 (12 bit)
Enumeration: ENUM
0 : PARK_MODE_IS_DISABLE
Park mode is disabled.
1 : PARK_MODE_IS_ENABLED
Park mode is enabled.
End of enumeration elements list.
RESERVED : Reserved.
bits : 12 - 24 (13 bit)
RESERVED : Not used in Host mode.
bits : 13 - 26 (14 bit)
RESERVED : Reserved.
bits : 14 - 28 (15 bit)
RESERVED : Reserved.
bits : 14 - 28 (15 bit)
FS2 : Bit 2 of the Frame List Size bits. See Table 281.
bits : 15 - 30 (16 bit)
ITC : Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames.
bits : 16 - 39 (24 bit)
RESERVED : Reserved
bits : 24 - 55 (32 bit)
USB status (device mode)
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UI : USB interrupt
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : ST
This bit is cleared by software writing a one to it.
1 : CLEAR
This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes.
End of enumeration elements list.
UEI : USB error interrupt
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : ST
This bit is cleared by software writing a one to it.
1 : CLEAR
When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6).
End of enumeration elements list.
PCI : Port change detect.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : ST
This bit is cleared by software writing a one to it.
1 : CLEAR
The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively.
End of enumeration elements list.
RESERVED : Reserved.
bits : 4 - 8 (5 bit)
RESERVED : Not used in Device mode.
bits : 5 - 10 (6 bit)
URI : USB reset received
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : ST
This bit is cleared by software writing a one to it.
1 : CLEAR
When the device controller detects a USB Reset and enters the default state, this bit will be set to a one.
End of enumeration elements list.
SRI : SOF received
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : ST
This bit is cleared by software writing a one to it.
1 : CLEAR
When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp.
End of enumeration elements list.
SLI : DCSuspend
bits : 8 - 16 (9 bit)
Enumeration: ENUM
0 : ST
The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it.
1 : CLEAR
When a device controller enters a suspend state from an active state, this bit will be set to a one.
End of enumeration elements list.
RESERVED : Reserved. Software should only write 0 to reserved bits.
bits : 9 - 20 (12 bit)
RESERVED : Not used in Device mode.
bits : 12 - 24 (13 bit)
RESERVED : Not used in Device mode.
bits : 13 - 26 (14 bit)
RESERVED : Not used in Device mode.
bits : 14 - 28 (15 bit)
RESERVED : Not used in Device mode.
bits : 15 - 30 (16 bit)
NAKI : NAK interrupt bit
bits : 16 - 32 (17 bit)
Enumeration: ENUM
0 : ENDPCLEAR
This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared.
1 : SET
It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set.
End of enumeration elements list.
RESERVED : Reserved. Software should only write 0 to reserved bits.
bits : 17 - 34 (18 bit)
RESERVED : Not used in Device mode.
bits : 18 - 36 (19 bit)
RESERVED : Not used in Device mode.
bits : 19 - 38 (20 bit)
RESERVED : Not used in Device mode.
bits : 19 - 38 (20 bit)
RESERVED : Reserved. Software should only write 0 to reserved bits.
bits : 20 - 51 (32 bit)
USB status (host mode)
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : USBSTS_D
reset_Mask : 0x0
UI : USB interrupt (USBINT)
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : ST
This bit is cleared by software writing a one to it.
1 : CLEAR
This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes.
End of enumeration elements list.
UEI : USB error interrupt (USBERRINT)
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : ST
This bit is cleared by software writing a one to it.
1 : CLEAR
When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set.
End of enumeration elements list.
PCI : Port change detect.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : ST
This bit is cleared by software writing a one to it.
1 : CLEAR
The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port.
End of enumeration elements list.
FRI : Frame list roll-over
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : ST
This bit is cleared by software writing a one to it.
1 : CLEAR
The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 19.6.5).
End of enumeration elements list.
AAI : Interrupt on async advance
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : ST
This bit is cleared by software writing a one to it.
1 : CLEAR
System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source.
End of enumeration elements list.
RESERVED : Not used by the Host controller.
bits : 6 - 12 (7 bit)
SRI : SOF received
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : ST
This bit is cleared by software writing a one to it.
1 : CLEAR
In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base.
End of enumeration elements list.
SLI : Not used by the Host controller.
bits : 8 - 16 (9 bit)
RESERVED : Reserved.
bits : 9 - 20 (12 bit)
HCH : HCHalted
bits : 12 - 24 (13 bit)
Enumeration: ENUM
0 : RS
The RS bit in USBCMD is set to zero. Set by the host controller.
1 : STOP
The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error).
End of enumeration elements list.
RCL : Reclamation
bits : 13 - 26 (14 bit)
Enumeration: ENUM
0 : NO_EMPTY_ASYNCHRONOU
No empty asynchronous schedule detected.
1 : EMPTY_ASYNCHRONOU
An empty asynchronous schedule is detected. Set by the host controller.
End of enumeration elements list.
PS : Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0).
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
The periodic schedule status is disabled.
1 : ENABLED
The periodic schedule status is enabled.
End of enumeration elements list.
AS : Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0).
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Asynchronous schedule status is disabled.
1 : ENABLED
Asynchronous schedule status is enabled.
End of enumeration elements list.
RESERVED : Not used on Host mode.
bits : 16 - 32 (17 bit)
RESERVED : Reserved.
bits : 17 - 34 (18 bit)
RESERVED : Reserved.
bits : 17 - 34 (18 bit)
UAI : USB host asynchronous interrupt (USBHSTASYNCINT)
bits : 18 - 36 (19 bit)
Enumeration: ENUM
0 : ST
This bit is cleared by software writing a one to it.
1 : CLEAR
This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes.
End of enumeration elements list.
UPI : USB host periodic interrupt (USBHSTPERINT)
bits : 19 - 38 (20 bit)
Enumeration: ENUM
0 : ST
This bit is cleared by software writing a one to it.
1 : CLEAR
This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes.
End of enumeration elements list.
RESERVED : Reserved.
bits : 20 - 51 (32 bit)
USB interrupt enable (device mode)
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UE : USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS.
bits : 0 - 0 (1 bit)
UEE : USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register.
bits : 1 - 2 (2 bit)
PCE : Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS.
bits : 2 - 4 (3 bit)
RESERVED : Reserved
bits : 4 - 8 (5 bit)
RESERVED : Not used by the Device controller.
bits : 5 - 10 (6 bit)
URE : USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit.
bits : 6 - 12 (7 bit)
SRE : SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit.
bits : 7 - 14 (8 bit)
SLE : Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit.
bits : 8 - 16 (9 bit)
RESERVED : Reserved
bits : 9 - 24 (16 bit)
NAKE : NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated.
bits : 16 - 32 (17 bit)
RESERVED : Reserved
bits : 17 - 34 (18 bit)
RESERVED : Reserved
bits : 17 - 34 (18 bit)
UAIE : Not used by the Device controller.
bits : 18 - 36 (19 bit)
UPIA : Not used by the Device controller.
bits : 19 - 38 (20 bit)
RESERVED : Reserved
bits : 20 - 51 (32 bit)
USB interrupt enable (host mode)
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : USBINTR_D
reset_Mask : 0x0
UE : USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS.
bits : 0 - 0 (1 bit)
UEE : USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register.
bits : 1 - 2 (2 bit)
PCE : Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS.
bits : 2 - 4 (3 bit)
FRE : Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit.
bits : 3 - 6 (4 bit)
AAE : Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit.
bits : 5 - 10 (6 bit)
RESERVED : Not used by the Host controller.
bits : 6 - 12 (7 bit)
SRE : If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register.
bits : 7 - 14 (8 bit)
RESERVED : Not used by the Host controller.
bits : 8 - 16 (9 bit)
RESERVED : Reserved
bits : 9 - 24 (16 bit)
RESERVED : Not used by the host controller.
bits : 16 - 32 (17 bit)
RESERVED : Reserved
bits : 17 - 34 (18 bit)
RESERVED : Reserved
bits : 17 - 34 (18 bit)
UAIE : USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit.
bits : 18 - 36 (19 bit)
UPIA : USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit.
bits : 19 - 38 (20 bit)
RESERVED : Reserved
bits : 20 - 51 (32 bit)
USB frame index (device mode)
address_offset : 0x14C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRINDEX2_0 : Current micro frame number
bits : 0 - 2 (3 bit)
FRINDEX13_3 : Current frame number of the last frame transmitted
bits : 3 - 16 (14 bit)
RESERVED : Reserved
bits : 14 - 45 (32 bit)
USB frame index (host mode)
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : FRINDEX_D
reset_Mask : 0x0
FRINDEX2_0 : Current micro frame number
bits : 0 - 2 (3 bit)
FRINDEX12_3 : Frame list current index for 1024 elements.
bits : 3 - 15 (13 bit)
RESERVED : Reserved
bits : 13 - 44 (32 bit)
USB device address
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : reserved
bits : 0 - 23 (24 bit)
USBADRA : Device address advance
bits : 24 - 48 (25 bit)
Enumeration: ENUM
0 : ADVANCE
Any write to USBADR are instantaneous.
1 : HOLD
When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement.
End of enumeration elements list.
USBADR : USB device address
bits : 25 - 56 (32 bit)
Frame list base address
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : DEVICEADDR
reset_Mask : 0x0
RESERVED : Reserved
bits : 0 - 11 (12 bit)
PERBASE31_12 : Base Address (Low) These bits correspond to the memory address signals[31:12].
bits : 12 - 43 (32 bit)
Address of endpoint list in memory (device mode)
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : reserved
bits : 0 - 10 (11 bit)
EPBASE31_11 : Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)
bits : 11 - 42 (32 bit)
Address of endpoint list in memory (host mode)
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : ENDPOINTLISTADDR
reset_Mask : 0x0
RESERVED : Reserved
bits : 0 - 4 (5 bit)
ASYBASE31_5 : Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH).
bits : 5 - 36 (32 bit)
Asynchronous buffer status for embedded TT (host mode)
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Reserved.
bits : 0 - 23 (24 bit)
TTHA : Hub address when FS or LS device are connected directly.
bits : 24 - 54 (31 bit)
RESERVED : Reserved.
bits : 31 - 62 (32 bit)
Programmable burst size
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXPBURST : Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory.
bits : 0 - 7 (8 bit)
TXPBURST : Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus.
bits : 8 - 23 (16 bit)
RESERVED : reserved
bits : 16 - 47 (32 bit)
Host transmit pre-buffer packet tuning (host mode)
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXSCHOH : FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set.
bits : 0 - 7 (8 bit)
TXSCHEATLTH : Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31.
bits : 8 - 20 (13 bit)
RESERVED : Reserved
bits : 13 - 28 (16 bit)
TXFIFOTHRES : Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267 ms when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333 ms when a device is connected in Low/Full Speed Mode.
bits : 16 - 37 (22 bit)
RESERVED : Reserved
bits : 22 - 53 (32 bit)
ULPI viewport
address_offset : 0x170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULPIDATWR : When a write operation is commanded, the data to be sent is written to this field.
bits : 0 - 7 (8 bit)
ULPIDATRD : After a read operation completes, the result is placed in this field.
bits : 8 - 23 (16 bit)
ULPIADDR : When a read or write operation is commanded, the address of the operation is written to this field.
bits : 16 - 39 (24 bit)
ULPIPORT : For the wakeup or read/write operation to be executed, this value must be written as 0.
bits : 24 - 50 (27 bit)
ULPISS : ULPI sync state. This bit represents the state of the ULPI interface.
bits : 27 - 54 (28 bit)
Enumeration: ENUM
0 : IN_ANOTHER_STATE
In another state (ie. carkit, serial, low power)
1 : NORMAL_SYNC_STATE_
Normal Sync. State.
End of enumeration elements list.
RESERVED : Reserved
bits : 28 - 56 (29 bit)
ULPIRW : ULPI Read/Write control. This bit selects between running a read or write operation.
bits : 29 - 58 (30 bit)
Enumeration: ENUM
0 : READ
Read
1 : WRITE
Write
End of enumeration elements list.
ULPIRUN : ULPI Read/Write Run. Writing the 1 to this bit will begin the read/write operation. The bit will automatically transition to 0 after the read/write is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at the same time.
bits : 30 - 60 (31 bit)
ULPIWU : ULPI Wake-up. Writing the 1 to this bit will begin the wakeup operation. The bit will automatically transition to 0 after the wakeup is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at the same time.
bits : 31 - 62 (32 bit)
Length of virtual frame
address_offset : 0x174 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BINT : bInterval value
bits : 0 - 3 (4 bit)
RESERVED : Reserved
bits : 4 - 35 (32 bit)
Endpoint NAK (device mode)
address_offset : 0x178 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPRN0 : Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.
bits : 0 - 0 (1 bit)
EPRN1 : Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.
bits : 1 - 2 (2 bit)
EPRN2 : Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.
bits : 2 - 4 (3 bit)
EPRN3 : Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.
bits : 3 - 6 (4 bit)
RESERVED : Reserved
bits : 4 - 19 (16 bit)
EPTN16 : Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.
bits : 16 - 32 (17 bit)
EPTN17 : Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.
bits : 17 - 34 (18 bit)
EPTN18 : Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.
bits : 18 - 36 (19 bit)
EPTN19 : Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.
bits : 19 - 38 (20 bit)
RESERVED : Reserved
bits : 20 - 51 (32 bit)
Endpoint NAK Enable (device mode)
address_offset : 0x17C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPRNE0 : Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.
bits : 0 - 0 (1 bit)
EPRNE1 : Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.
bits : 1 - 2 (2 bit)
EPRNE2 : Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.
bits : 2 - 4 (3 bit)
EPRNE3 : Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.
bits : 3 - 6 (4 bit)
RESERVED : Reserved
bits : 4 - 19 (16 bit)
EPTNE16 : Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.
bits : 16 - 32 (17 bit)
EPTNE17 : Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.
bits : 17 - 34 (18 bit)
EPTNE18 : Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.
bits : 18 - 36 (19 bit)
EPTNE19 : Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.
bits : 19 - 38 (20 bit)
RESERVED : Reserved
bits : 20 - 51 (32 bit)
Port 1 status/control (device mode)
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCS : Current connect status
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DEVICE_NOT_ATTACHED_
Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended.
1 : DEVICE_ATTACHED__A_
Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register.
End of enumeration elements list.
CSC : Not used in device mode
bits : 1 - 2 (2 bit)
PE : Port enable. This bit is always 1. The device port is always enabled.
bits : 2 - 4 (3 bit)
PEC : Port enable/disable change This bit is always 0. The device port is always enabled.
bits : 3 - 6 (4 bit)
FPR : Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : NO_RESUME
No resume (K-state) detected/driven on port.
1 : RESUME_DETECTED
Resume detected/driven on port.
End of enumeration elements list.
SUSP : Suspend In device mode, this is a read-only status bit .
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : PORT_NOT_IN_SUSPEND_
Port not in suspend state
1 : PORT_IN_SUSPEND_STAT
Port in suspend state
End of enumeration elements list.
PR : Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register.
bits : 8 - 16 (9 bit)
Enumeration: ENUM
0 : PORT_IS_NOT_IN_THE_R
Port is not in the reset state.
1 : PORT_IS_IN_THE_RESET
Port is in the reset state.
End of enumeration elements list.
HSP : High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons.
bits : 9 - 18 (10 bit)
Enumeration: ENUM
0 : NOHISPEED
Host/device connected to the port is not in High-speed mode.
1 : HISPEED
Host/device connected to the port is in High-speed mode.
End of enumeration elements list.
LS : Not used in device mode.
bits : 10 - 21 (12 bit)
PP : Not used in device mode.
bits : 12 - 24 (13 bit)
RESERVED : Reserved
bits : 13 - 26 (14 bit)
PIC1_0 : Port indicator control Writing to this field effects the value of the USB1_IND1:0 pins.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : OFF
Port indicators are off.
0x1 : AMBER
amber
0x2 : GREEN
green
0x3 : UNDEFINED
undefined
End of enumeration elements list.
PTC3_0 : Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x7 to 0xF are reserved.
bits : 16 - 35 (20 bit)
Enumeration: ENUM
0x0 : TEST_MODE_DISABLE
TEST_MODE_DISABLE
0x1 : J_STATE
J_STATE
0x2 : K_STATE
K_STATE
0x3 : SE0
SE0 (host)/NAK (device)
0x4 : PACKET
Packet
0x5 : FORCE_ENABLE_HS
FORCE_ENABLE_HS
0x6 : FORCE_ENABLE_FS
FORCE_ENABLE_FS
End of enumeration elements list.
RESERVED : Not used in device mode. This bit is always 0 in device mode.
bits : 20 - 40 (21 bit)
RESERVED : Not used in device mode. This bit is always 0 in device mode.
bits : 21 - 42 (22 bit)
RESERVED : Not used in device mode. This bit is always 0 in device mode.
bits : 22 - 44 (23 bit)
PHCD : PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.
bits : 23 - 46 (24 bit)
Enumeration: ENUM
0 : ENABLED
Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled).
1 : DISABLED
Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled).
End of enumeration elements list.
PFSC : Port force full speed connect
bits : 24 - 48 (25 bit)
Enumeration: ENUM
0 : ANYSPEED
Port connects at any speed.
1 : FULLSPEED
Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device.
End of enumeration elements list.
RESERVED : Reserved
bits : 25 - 50 (26 bit)
RESERVED : Reserved
bits : 25 - 50 (26 bit)
PSPD : Port speed This register field indicates the speed at which the port is operating.
bits : 26 - 53 (28 bit)
Enumeration: ENUM
0x1 : FULL_SPEED
Full-speed
0x2 : INVALID_IN_DEVICE_MO
invalid in device mode
0x3 : HIGH_SPEED
High-speed
End of enumeration elements list.
RESERVED : Reserved
bits : 28 - 57 (30 bit)
PTS : Parallel transceiver select. All other values are reserved.
bits : 30 - 61 (32 bit)
Enumeration: ENUM
0x2 : ULPI
ULPI
0x3 : SERIAL
Serial/ 1.1 PHY (Full-speed only)
End of enumeration elements list.
Port 1 status/control (host mode)
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PORTSC1_D
reset_Mask : 0x0
CCS : Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_DEVICE_IS_PRESENT
No device is present.
1 : DEVICE_IS_PRESENT_ON
Device is present on the port.
End of enumeration elements list.
CSC : Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : NO_CHANGE_IN_CURRENT
No change in current status.
1 : CHANGE_IN_CURRENT_ST
Change in current status.
End of enumeration elements list.
PE : Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : PORT_DISABLED_
Port disabled.
1 : PORT_ENABLED_
Port enabled.
End of enumeration elements list.
PEC : Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NO_CHANGE_
No change.
1 : CHANGED
Port enabled/disabled status has changed.
End of enumeration elements list.
OCA : Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : THE_PORT_DOES_NOT_HA
The port does not have an over-current condition.
1 : THE_PORT_HAS_CURRENT
The port has currently an over-current condition.
End of enumeration elements list.
OCC : Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position.
bits : 5 - 10 (6 bit)
FPR : Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : NO_RESUME
No resume (K-state) detected/driven on port.
1 : RESUME_DETECTED
Resume detected/driven on port.
End of enumeration elements list.
SUSP : Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 302 Port states as described by the PE and SUSP bits in the PORTSC1 register. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0.
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : PORT_NOT_IN_SUSPEND_
Port not in suspend state
1 : PORT_IN_SUSPEND_STAT
Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.
End of enumeration elements list.
PR : Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0.
bits : 8 - 16 (9 bit)
Enumeration: ENUM
0 : NOT_IN_RESET
Port is not in the reset state.
1 : PORT_IS_IN_THE_RESET
Port is in the reset state.
End of enumeration elements list.
HSP : High-speed status
bits : 9 - 18 (10 bit)
Enumeration: ENUM
0 : NOHIGHSPEED
Host/device connected to the port is not in High-speed mode.
1 : HIGHSPEED
Host/device connected to the port is in High-speed mode.
End of enumeration elements list.
LS : Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS.
bits : 10 - 21 (12 bit)
Enumeration: ENUM
0x0 : SE0
SE0 (USB_DP and USB_DM LOW)
0x1 : J_STATE
J-state (USB_DP HIGH and USB_DM LOW)
0x2 : K_STATE
K-state (USB_DP LOW and USB_DM HIGH)
0x3 : UNDEFINED
Undefined
End of enumeration elements list.
PP : Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).
bits : 12 - 24 (13 bit)
Enumeration: ENUM
0 : PORT_POWER_OFF_
Port power off.
1 : PORT_POWER_ON_
Port power on.
End of enumeration elements list.
PIC1_0 : Port indicator control Writing to this field controls the value of the pins USB1_IND1 and USB1_IND0.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : OFF
Port indicators are off.
0x1 : AMBER
Amber
0x2 : GREEN
Green
0x3 : UNDEFINED
Undefined
End of enumeration elements list.
PTC3_0 : Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved.
bits : 16 - 35 (20 bit)
Enumeration: ENUM
0x0 : TEST_MODE_DISABLE
TEST_MODE_DISABLE
0x1 : J_STATE
J_STATE
0x2 : K_STATE
K_STATE
0x3 : SE0_NAK
SE0 (host)/NAK (device)
0x4 : PACKET
Packet
0x5 : FORCE_ENABLE_HS
FORCE_ENABLE_HS
0x6 : FORCE_ENABLE_FS
FORCE_ENABLE_FS
0x7 : FORCE_ENABLE_LS
FORCE_ENABLE_LS
End of enumeration elements list.
WKCN : Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0
bits : 20 - 40 (21 bit)
Enumeration: ENUM
0 : DISABLES_THE_PORT_TO
Disables the port to wake up on device connects.
1 : ENABLE_DEVICE_CON
Writing this bit to a one enables the port to be sensitive to device connects as wake-up events.
End of enumeration elements list.
WKDC : Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.
bits : 21 - 42 (22 bit)
Enumeration: ENUM
0 : DISABLES_THE_PORT_TO
Disables the port to wake up on device disconnects.
1 : ENABLE_DEVICE_CON
Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events.
End of enumeration elements list.
WKOC : Wake on over-current enable (WKOC_E)
bits : 22 - 44 (23 bit)
Enumeration: ENUM
0 : DISABLES_OVERCURRENT
Disables the port to wake up on over-current events.
1 : ENABLE_OVERCURRENT
Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events.
End of enumeration elements list.
PHCD : PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software.
bits : 23 - 46 (24 bit)
Enumeration: ENUM
0 : ENABLE_PHY_CLK
Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled).
1 : DISABLE_PHY_CLK
Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled).
End of enumeration elements list.
PFSC : Port force full speed connect
bits : 24 - 48 (25 bit)
Enumeration: ENUM
0 : ANYSPEED
Port connects at any speed.
1 : FULLSPEED
Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device.
End of enumeration elements list.
RESERVED : Reserved
bits : 25 - 50 (26 bit)
RESERVED : Reserved
bits : 25 - 50 (26 bit)
PSPD : Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator.
bits : 26 - 53 (28 bit)
Enumeration: ENUM
0x0 : FULL_SPEED
Full-speed
0x1 : LOW_SPEED
Low-speed
0x2 : HIGH_SPEED
High-speed
End of enumeration elements list.
RESERVED : Reserved
bits : 28 - 57 (30 bit)
PTS : Parallel transceiver select. All other values are reserved.
bits : 30 - 61 (32 bit)
Enumeration: ENUM
0x2 : ULPI
ULPI
0x3 : SERIAL
Serial/ 1.1 PHY (Full-speed only)
End of enumeration elements list.
USB mode (device mode)
address_offset : 0x1A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM1_0 : Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.
bits : 0 - 1 (2 bit)
Enumeration: ENUM
0x0 : IDLE
Idle
0x1 : RESERVED
Reserved
0x2 : DEVICE_CONTROLLER
Device controller
0x3 : HOST_CONTROLLER
Host controller
End of enumeration elements list.
ES : Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : LITTLE_ENDIAN_FIRST
Little endian: first byte referenced in least significant byte of 32-bit word.
1 : BIG_ENDIAN_FIRST_BY
Big endian: first byte referenced in most significant byte of 32-bit word.
End of enumeration elements list.
SLOM : Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : SETUP_LOCKOUTS_ON
Setup Lockouts on
1 : SETUP_LOCKOUTS_OFF
Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD)
End of enumeration elements list.
SDIS : Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NOT_DISABLED
Not disabled
1 : DISABLED_SETTING_TH
Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active.
End of enumeration elements list.
RESERVED : Not used in device mode.
bits : 5 - 10 (6 bit)
RESERVED : Reserved
bits : 6 - 37 (32 bit)
USB mode (host mode)
address_offset : 0x1A8 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : USBMODE_D
reset_Mask : 0x0
CM1_0 : Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.
bits : 0 - 1 (2 bit)
Enumeration: ENUM
0x0 : IDLE
Idle
0x1 : RESERVED
Reserved
0x2 : DEVICE_CONTROLLER
Device controller
0x3 : HOST_CONTROLLER
Host controller
End of enumeration elements list.
ES : Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : LITTLE_ENDIAN_FIRST
Little endian: first byte referenced in least significant byte of 32-bit word.
1 : BIG_ENDIAN_FIRST_BY
Big endian: first byte referenced in most significant byte of 32-bit word.
End of enumeration elements list.
RESERVED : Not used in host mode
bits : 3 - 6 (4 bit)
SDIS : Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NOT_DISABLED
Not disabled
1 : DISABLED_SETTING_TO
Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature.
End of enumeration elements list.
VBPS : VBUS power select
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : LOW
vbus_pwr_select is set LOW.
1 : HIGH
vbus_pwr_select is set HIGH
End of enumeration elements list.
RESERVED : Reserved
bits : 6 - 37 (32 bit)
Endpoint setup status
address_offset : 0x1AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDPTSETUPSTAT0 : Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged.
bits : 0 - 0 (1 bit)
ENDPTSETUPSTAT1 : Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged.
bits : 1 - 2 (2 bit)
ENDPTSETUPSTAT2 : Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged.
bits : 2 - 4 (3 bit)
ENDPTSETUPSTAT3 : Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged.
bits : 3 - 6 (4 bit)
RESERVED : Reserved
bits : 4 - 35 (32 bit)
Endpoint initialization
address_offset : 0x1B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERB0 : Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3
bits : 0 - 0 (1 bit)
PERB1 : Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3
bits : 1 - 2 (2 bit)
PERB2 : Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3
bits : 2 - 4 (3 bit)
PERB3 : Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3
bits : 3 - 6 (4 bit)
RESERVED : Reserved
bits : 4 - 19 (16 bit)
PETB0 : Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3
bits : 16 - 32 (17 bit)
PETB1 : Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3
bits : 17 - 34 (18 bit)
PETB2 : Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3
bits : 18 - 36 (19 bit)
PETB3 : Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3
bits : 19 - 38 (20 bit)
RESERVED : Reserved
bits : 20 - 51 (32 bit)
Endpoint de-initialization
address_offset : 0x1B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FERB0 : Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3
bits : 0 - 0 (1 bit)
FERB1 : Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3
bits : 1 - 2 (2 bit)
FERB2 : Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3
bits : 2 - 4 (3 bit)
FERB3 : Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3
bits : 3 - 6 (4 bit)
RESERVED : Reserved
bits : 4 - 19 (16 bit)
FETB0 : Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3
bits : 16 - 32 (17 bit)
FETB1 : Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3
bits : 17 - 34 (18 bit)
FETB2 : Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3
bits : 18 - 36 (19 bit)
FETB3 : Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3
bits : 19 - 38 (20 bit)
RESERVED : Reserved
bits : 20 - 51 (32 bit)
Endpoint status
address_offset : 0x1B8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERBR0 : Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3
bits : 0 - 0 (1 bit)
ERBR1 : Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3
bits : 1 - 2 (2 bit)
ERBR2 : Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3
bits : 2 - 4 (3 bit)
ERBR3 : Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3
bits : 3 - 6 (4 bit)
RESERVED : Reserved
bits : 4 - 19 (16 bit)
ETBR0 : Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3
bits : 16 - 32 (17 bit)
ETBR1 : Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3
bits : 17 - 34 (18 bit)
ETBR2 : Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3
bits : 18 - 36 (19 bit)
ETBR3 : Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3
bits : 19 - 38 (20 bit)
RESERVED : Reserved
bits : 20 - 51 (32 bit)
Endpoint complete
address_offset : 0x1BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERCE0 : Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3
bits : 0 - 0 (1 bit)
ERCE1 : Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3
bits : 1 - 2 (2 bit)
ERCE2 : Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3
bits : 2 - 4 (3 bit)
ERCE3 : Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3
bits : 3 - 6 (4 bit)
RESERVED : Reserved
bits : 4 - 19 (16 bit)
ETCE0 : Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3
bits : 16 - 32 (17 bit)
ETCE1 : Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3
bits : 17 - 34 (18 bit)
ETCE2 : Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3
bits : 18 - 36 (19 bit)
ETCE3 : Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3
bits : 19 - 38 (20 bit)
RESERVED : Reserved
bits : 20 - 51 (32 bit)
Endpoint control 0
address_offset : 0x1C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXS : Rx endpoint stall
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : ENDPOINT_OK_
Endpoint ok.
1 : ENDPOINT_STALLED_SOF
Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]
End of enumeration elements list.
RXT : Endpoint type Endpoint 0 is always a control endpoint.
bits : 2 - 5 (4 bit)
RESERVED : Reserved
bits : 4 - 10 (7 bit)
RXE : Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1.
bits : 7 - 14 (8 bit)
RESERVED : Reserved
bits : 8 - 23 (16 bit)
TXS : Tx endpoint stall
bits : 16 - 32 (17 bit)
Enumeration: ENUM
0 : ENDPOINT_OK_
Endpoint ok.
1 : ENDPOINT_STALLED_SOF
Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]
End of enumeration elements list.
RESERVED : Reserved
bits : 17 - 34 (18 bit)
TXT : Endpoint type Endpoint 0 is always a control endpoint.
bits : 18 - 37 (20 bit)
RESERVED : Reserved
bits : 20 - 42 (23 bit)
RESERVED : Reserved
bits : 20 - 42 (23 bit)
TXE : Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1.
bits : 23 - 46 (24 bit)
RESERVED : Reserved
bits : 24 - 55 (32 bit)
Endpoint control
address_offset : 0x1C4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXS : Rx endpoint stall
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : ENDPOINT_OK_THIS_BI
Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared.
1 : ENDPOINT_STALLED_SOF
Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]
End of enumeration elements list.
RXT : Endpoint type
bits : 2 - 5 (4 bit)
Enumeration: ENUM
0x0 : CONTROL
Control
0x1 : ISOCHRONOUS
Isochronous
0x2 : BULK
Bulk
0x3 : RESERVED
Reserved
End of enumeration elements list.
RESERVED : Reserved
bits : 4 - 8 (5 bit)
RXI : Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : DISABLED
Disabled
1 : ENABLED
Enabled
End of enumeration elements list.
RXR : Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device.
bits : 6 - 12 (7 bit)
RXE : Rx endpoint enable An endpoint should be enabled only after it has been configured.
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : ENDPOINT_DISABLED_
Endpoint disabled.
1 : ENDPOINT_ENABLED_
Endpoint enabled.
End of enumeration elements list.
RESERVED : Reserved
bits : 8 - 23 (16 bit)
TXS : Tx endpoint stall
bits : 16 - 32 (17 bit)
Enumeration: ENUM
0 : ENDPOINT_OK_THIS_BI
Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared.
1 : ENDPOINT_STALLED_SOF
Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]
End of enumeration elements list.
RESERVED : Reserved
bits : 17 - 34 (18 bit)
TXT : Tx endpoint type
bits : 18 - 37 (20 bit)
Enumeration: ENUM
0x0 : CONTROL
Control
0x1 : ISOCHRONOUS
Isochronous
0x2 : BULK
Bulk
0x3 : INTERRUPT
Interrupt
End of enumeration elements list.
RESERVED : Reserved
bits : 20 - 40 (21 bit)
RESERVED : Reserved
bits : 20 - 40 (21 bit)
TXI : Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.
bits : 21 - 42 (22 bit)
Enumeration: ENUM
0 : ENABLED
Enabled
1 : DISABLED
Disabled
End of enumeration elements list.
TXR : Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device.
bits : 22 - 44 (23 bit)
TXE : Tx endpoint enable An endpoint should be enabled only after it has been configured
bits : 23 - 46 (24 bit)
Enumeration: ENUM
0 : ENDPOINT_DISABLED_
Endpoint disabled.
1 : ENDPOINT_ENABLED_
Endpoint enabled.
End of enumeration elements list.
RESERVED : Reserved
bits : 24 - 55 (32 bit)
Endpoint control
address_offset : 0x1C8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXS : Rx endpoint stall
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : ENDPOINT_OK_THIS_BI
Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared.
1 : ENDPOINT_STALLED_SOF
Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]
End of enumeration elements list.
RXT : Endpoint type
bits : 2 - 5 (4 bit)
Enumeration: ENUM
0x0 : CONTROL
Control
0x1 : ISOCHRONOUS
Isochronous
0x2 : BULK
Bulk
0x3 : RESERVED
Reserved
End of enumeration elements list.
RESERVED : Reserved
bits : 4 - 8 (5 bit)
RXI : Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : DISABLED
Disabled
1 : ENABLED
Enabled
End of enumeration elements list.
RXR : Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device.
bits : 6 - 12 (7 bit)
RXE : Rx endpoint enable An endpoint should be enabled only after it has been configured.
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : ENDPOINT_DISABLED_
Endpoint disabled.
1 : ENDPOINT_ENABLED_
Endpoint enabled.
End of enumeration elements list.
RESERVED : Reserved
bits : 8 - 23 (16 bit)
TXS : Tx endpoint stall
bits : 16 - 32 (17 bit)
Enumeration: ENUM
0 : ENDPOINT_OK_THIS_BI
Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared.
1 : ENDPOINT_STALLED_SOF
Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]
End of enumeration elements list.
RESERVED : Reserved
bits : 17 - 34 (18 bit)
TXT : Tx endpoint type
bits : 18 - 37 (20 bit)
Enumeration: ENUM
0x0 : CONTROL
Control
0x1 : ISOCHRONOUS
Isochronous
0x2 : BULK
Bulk
0x3 : INTERRUPT
Interrupt
End of enumeration elements list.
RESERVED : Reserved
bits : 20 - 40 (21 bit)
RESERVED : Reserved
bits : 20 - 40 (21 bit)
TXI : Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.
bits : 21 - 42 (22 bit)
Enumeration: ENUM
0 : ENABLED
Enabled
1 : DISABLED
Disabled
End of enumeration elements list.
TXR : Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device.
bits : 22 - 44 (23 bit)
TXE : Tx endpoint enable An endpoint should be enabled only after it has been configured
bits : 23 - 46 (24 bit)
Enumeration: ENUM
0 : ENDPOINT_DISABLED_
Endpoint disabled.
1 : ENDPOINT_ENABLED_
Endpoint enabled.
End of enumeration elements list.
RESERVED : Reserved
bits : 24 - 55 (32 bit)
Endpoint control
address_offset : 0x1CC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXS : Rx endpoint stall
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : ENDPOINT_OK_THIS_BI
Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared.
1 : ENDPOINT_STALLED_SOF
Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]
End of enumeration elements list.
RXT : Endpoint type
bits : 2 - 5 (4 bit)
Enumeration: ENUM
0x0 : CONTROL
Control
0x1 : ISOCHRONOUS
Isochronous
0x2 : BULK
Bulk
0x3 : RESERVED
Reserved
End of enumeration elements list.
RESERVED : Reserved
bits : 4 - 8 (5 bit)
RXI : Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : DISABLED
Disabled
1 : ENABLED
Enabled
End of enumeration elements list.
RXR : Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device.
bits : 6 - 12 (7 bit)
RXE : Rx endpoint enable An endpoint should be enabled only after it has been configured.
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : ENDPOINT_DISABLED_
Endpoint disabled.
1 : ENDPOINT_ENABLED_
Endpoint enabled.
End of enumeration elements list.
RESERVED : Reserved
bits : 8 - 23 (16 bit)
TXS : Tx endpoint stall
bits : 16 - 32 (17 bit)
Enumeration: ENUM
0 : ENDPOINT_OK_THIS_BI
Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared.
1 : ENDPOINT_STALLED_SOF
Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]
End of enumeration elements list.
RESERVED : Reserved
bits : 17 - 34 (18 bit)
TXT : Tx endpoint type
bits : 18 - 37 (20 bit)
Enumeration: ENUM
0x0 : CONTROL
Control
0x1 : ISOCHRONOUS
Isochronous
0x2 : BULK
Bulk
0x3 : INTERRUPT
Interrupt
End of enumeration elements list.
RESERVED : Reserved
bits : 20 - 40 (21 bit)
RESERVED : Reserved
bits : 20 - 40 (21 bit)
TXI : Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.
bits : 21 - 42 (22 bit)
Enumeration: ENUM
0 : ENABLED
Enabled
1 : DISABLED
Disabled
End of enumeration elements list.
TXR : Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device.
bits : 22 - 44 (23 bit)
TXE : Tx endpoint enable An endpoint should be enabled only after it has been configured
bits : 23 - 46 (24 bit)
Enumeration: ENUM
0 : ENDPOINT_DISABLED_
Endpoint disabled.
1 : ENDPOINT_ENABLED_
Endpoint enabled.
End of enumeration elements list.
RESERVED : Reserved
bits : 24 - 55 (32 bit)
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