Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x300 byte (0x0)
mem_usage : registers
protection : not protected
Receiver Buffer Register. Contains the next received character to be read (DLAB = 0).
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RBR : Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO.
bits : 0 - 7 (8 bit)
RESERVED : Reserved
bits : 8 - 39 (32 bit)
Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0).
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
alternate_register : RBR
reset_Mask : 0x0
THR : Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available.
bits : 0 - 7 (8 bit)
RESERVED : Reserved
bits : 8 - 39 (32 bit)
Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1).
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : RBR
reset_Mask : 0x0
DLLSB : Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART.
bits : 0 - 7 (8 bit)
RESERVED : Reserved
bits : 8 - 39 (32 bit)
Line Status Register. Contains flags for transmit and receive status, including line errors.
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : EMPTY
Empty. RBR is empty.
1 : DATA
Data. RBR contains valid data.
End of enumeration elements list.
OE : Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : INACTIVE
Inactive. Overrun error status is inactive.
1 : ACTIVE
Active. Overrun error status is active.
End of enumeration elements list.
PE : Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : INACTIVE
Inactive. Parity error status is inactive.
1 : ACTIVE
Active. Parity error status is active.
End of enumeration elements list.
FE : Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : INACTIVE
Inactive. Framing error status is inactive.
1 : ACTIVE
Active. Framing error status is active.
End of enumeration elements list.
BI : Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : INACTIVE
Inactive. Break interrupt status is inactive.
1 : ACTIVE
Active. Break interrupt status is active.
End of enumeration elements list.
THRE : Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NOT_EMPTY
Not empty. THR contains valid data.
1 : EMPTY
Empty. THR is empty.
End of enumeration elements list.
TEMT : Transmitter Empty. TEMT is set when both THR and TSR are empty TEMT is cleared when either the TSR or the THR contain valid data.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : NOT_EMPTY
Not empty. THR and/or the TSR contains valid data.
1 : EMPTY
Empty. THR and the TSR are empty.
End of enumeration elements list.
RXFE : Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : NO_ERROR
No error. RBR contains no USART RX errors or FCR[0]=0.
1 : ERROR
Error. USART RBR contains at least one USART RX error.
End of enumeration elements list.
TXERR : Error in transmitted character. A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.
bits : 8 - 16 (9 bit)
Enumeration: ENUM
0 : NO_ERROR
No error. No error (normal default condition).
1 : NACK
NACK. A NACK response is received during Smart card T=0 operation.
End of enumeration elements list.
RESERVED : Reserved
bits : 9 - 40 (32 bit)
Scratch Pad Register. Eight-bit temporary storage for software.
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAD : Scratch pad. A readable, writable byte.
bits : 0 - 7 (8 bit)
RESERVED : Reserved
bits : 8 - 39 (32 bit)
Auto-baud Control Register. Contains controls for the auto-baud feature.
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Start bit. This bit is automatically cleared after auto-baud completion.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : STOP
Stop. Auto-baud stop (auto-baud is not running).
1 : START
Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.
End of enumeration elements list.
MODE : Auto-baud mode select bit.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : MODE_0
Mode 0.
1 : MODE_1
Mode 1.
End of enumeration elements list.
AUTORESTART : Restart bit.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NO_RESTART
No restart.
1 : RESTART
Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)
End of enumeration elements list.
ABEOINTCLR : End of auto-baud interrupt clear bit (write-only).
bits : 8 - 16 (9 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect. Writing a 0 has no impact.
1 : CLEAR
Clear. Writing a 1 will clear the corresponding interrupt in the IIR.
End of enumeration elements list.
ABTOINTCLR : Auto-baud time-out interrupt clear bit (write-only).
bits : 9 - 18 (10 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect. Writing a 0 has no impact.
1 : CLEAR
Clear. Writing a 1 will clear the corresponding interrupt in the IIR.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 10 - 41 (32 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 10 - 41 (32 bit)
IrDA control register (USART3 only)
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRDAEN : IrDA mode enable.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART.
1 : ENABLED
Enabled. IrDA mode on USART3 is enabled.
End of enumeration elements list.
IRDAINV : Serial input direction.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : NOT_INVERTED
Not inverted. The serial input is not inverted.
1 : INVERTED
Inverted. The serial input is inverted. This has no effect on the serial output.
End of enumeration elements list.
FIXPULSEEN : IrDA fixed pulse width mode.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. IrDA fixed pulse width mode disabled.
1 : ENABLED
Enabled. IrDA fixed pulse width mode enabled.
End of enumeration elements list.
PULSEDIV : Configures the pulse when FixPulseEn = 1. See Table 885 for details.
bits : 3 - 8 (6 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 6 - 37 (32 bit)
Fractional Divider Register. Generates a clock input for the baud rate divider.
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVADDVAL : Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate.
bits : 0 - 3 (4 bit)
MULVAL : Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not.
bits : 4 - 11 (8 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)
Oversampling Register. Controls the degree of oversampling during each bit time.
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSFRAC : Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)
bits : 1 - 4 (4 bit)
OSINT : Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time.
bits : 4 - 11 (8 bit)
FDINT : In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372.
bits : 8 - 22 (15 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 15 - 46 (32 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 15 - 46 (32 bit)
Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1).
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLMSB : Divisor latch MSB. The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART.
bits : 0 - 7 (8 bit)
RESERVED : Reserved
bits : 8 - 39 (32 bit)
Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0).
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : DLM
reset_Mask : 0x0
RBRIE : RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLE
Disable. Disable the RDA interrupt.
1 : ENABLE
Enable. Enable the RDA interrupt.
End of enumeration elements list.
THREIE : THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLE
Disable. Disable the THRE interrupt.
1 : ENABLE
Enable. Enable the THRE interrupt.
End of enumeration elements list.
RXIE : RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : DISABLE
Disable. Disable the RX line status interrupts.
1 : ENABLE
Enable. Enable the RX line status interrupts.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 4 - 10 (7 bit)
RESERVED : Reserved
bits : 7 - 14 (8 bit)
ABEOINTEN : Enables the end of auto-baud interrupt.
bits : 8 - 16 (9 bit)
Enumeration: ENUM
0 : DISABLE
Disable. Disable end of auto-baud Interrupt.
1 : ENABLE
Enable. Enable end of auto-baud Interrupt.
End of enumeration elements list.
ABTOINTEN : Enables the auto-baud time-out interrupt.
bits : 9 - 18 (10 bit)
Enumeration: ENUM
0 : DISABLE
Disable. Disable auto-baud time-out Interrupt.
1 : ENABLE
Enable. Enable auto-baud time-out Interrupt.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 10 - 41 (32 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 10 - 41 (32 bit)
Half-duplex enable Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HDEN : Half-duplex mode enable
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Disable half-duplex mode.
1 : ENABLED
Enabled. Enable half-duplex mode.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 1 - 32 (32 bit)
Smart card interface control register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCIEN : Smart Card Interface Enable.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Smart card interface disabled.
1 : ENABLED
Enabled. synchronous half duplex smart card interface is enabled.
End of enumeration elements list.
NACKDIS : NACK response disable. Only applicable in T=0.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : ENABLED
Enabled. A NACK response is enabled.
1 : DISABLED
Disabled. A NACK response is inhibited.
End of enumeration elements list.
PROTSEL : Protocol selection as defined in the ISO7816-3 standard.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : T_EQ_0
T = 0
1 : T_EQ_1
T = 1
End of enumeration elements list.
TXRETRY : Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled.
bits : 5 - 12 (8 bit)
GUARDTIME : Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol.
bits : 8 - 23 (16 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 16 - 47 (32 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 16 - 47 (32 bit)
RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMMEN : NMM enable.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.
1 : ENABLED
Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt.
End of enumeration elements list.
RXDIS : Receiver enable.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : ENABLED
Enabled. The receiver is enabled.
1 : DISABLED
Disabled.The receiver is disabled.
End of enumeration elements list.
AADEN : AAD enable
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Auto Address Detect (AAD) is disabled.
1 : ENABLED
Enabled. Auto Address Detect (AAD) is enabled.
End of enumeration elements list.
DCTRL : Direction control for DIR pin.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Disable Auto Direction Control.
1 : ENABLED
Enabled. Enable Auto Direction Control.
End of enumeration elements list.
OINV : Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : LOW
Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.
1 : HIGH
High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 6 - 37 (32 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 6 - 37 (32 bit)
RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADRMATCH : Contains the address match value.
bits : 0 - 7 (8 bit)
RESERVED : Reserved
bits : 8 - 39 (32 bit)
RS-485/EIA-485 direction control delay.
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : Contains the direction control delay value. This register works in conjunction with an 8-bit counter.
bits : 0 - 7 (8 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)
Synchronous mode control register.
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNC : Enables synchronous mode.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled.
1 : ENABLED
Enabled.
End of enumeration elements list.
CSRC : Clock source select.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : SLAVE_MODE
Slave mode. Synchronous slave mode (SCLK in)
1 : MASTER_MODE
Master mode. Synchronous master mode (SCLK out)
End of enumeration elements list.
FES : Edge sampling.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : RISING
Rising. RxD is sampled on the rising edge of SCLK.
1 : FALLING
Falling. RxD is sampled on the falling edge of SCLK.
End of enumeration elements list.
TSBYPASS : Transmit synchronization bypass in synchronous slave mode.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : SYNCHRONIZED
Synchronized. The input clock is synchronized prior to being used in clock edge detection logic.
1 : NOT_SYNCHRONIZED
Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability.
End of enumeration elements list.
CSCEN : Continuous master clock enable (used only when CSRC is 1)
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ON_CHARACTER
On character. SCLK cycles only when characters are being sent on TxD.
1 : CONTINUOUSLY
Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD).
End of enumeration elements list.
SSSDIS : Start/stop bits
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : SEND
Send. Send start and stop bits as in other modes.
1 : DO_NOT_SEND
Do not send. Do not send start/stop bits.
End of enumeration elements list.
CCCLR : Continuous clock clear
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SOFTWARE
Software. CSCEN is under software control.
1 : HARDWARE
Hardware. Hardware clears CSCEN after each character is received.
End of enumeration elements list.
RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 7 - 38 (32 bit)
Transmit Enable Register. Turns off USART transmitter for use with software flow control.
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXEN : Transmit enable. After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR.
bits : 0 - 0 (1 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 1 - 32 (32 bit)
Interrupt ID Register. Identifies which interrupt(s) are pending.
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTSTATUS : Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : INTERRUPT_PENDING
Interrupt pending. At least one interrupt is pending.
1 : NOT_PENDING
Not pending. No interrupt is pending.
End of enumeration elements list.
INTID : Interrupt identification. IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).
bits : 1 - 4 (4 bit)
Enumeration: ENUM
0x3 : RLS
RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS).
0x2 : RDA
RDA. Priority 2 - Receive Data Available (RDA).
0x6 : CTI
CTI. Priority 2 - Character Time-out Indicator (CTI).
0x1 : THRE
THRE. Priority 3 - THRE Interrupt.
0x0 : RESERVED
Reserved. Priority 4 (lowest) - Reserved.
End of enumeration elements list.
FIFOENABLE : Copies of FCR[0].
bits : 6 - 13 (8 bit)
ABEOINT : End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.
bits : 8 - 16 (9 bit)
ABTOINT : Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.
bits : 9 - 18 (10 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 10 - 41 (32 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 10 - 41 (32 bit)
FIFO Control Register. Controls USART FIFO usage and modes.
address_offset : 0x8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FIFOEN : FIFO Enable.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. USART FIFOs are disabled. Must not be used in the application.
1 : ENABLED
Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs.
End of enumeration elements list.
RXFIFORES : RX FIFO Reset.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect. No impact on either of USART FIFOs.
1 : CLEAR
Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing.
End of enumeration elements list.
TXFIFORES : TX FIFO Reset.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect. No impact on either of USART FIFOs.
1 : CLEAR
Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing.
End of enumeration elements list.
DMAMODE : DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode.
bits : 3 - 6 (4 bit)
RXTRIGLVL : RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.
bits : 6 - 13 (8 bit)
Enumeration: ENUM
0x0 : LEVEL_0
Level 0. Trigger level 0 (1 character or 0x01).
0x1 : LEVEL_1
Level 1. Trigger level 1 (4 characters or 0x04).
0x2 : LEVEL_2
Level 2. Trigger level 2 (8 characters or 0x08).
0x3 : LEVEL_3
Level 3. Trigger level 3 (14 characters or 0x0E).
End of enumeration elements list.
RESERVED : Reserved
bits : 8 - 39 (32 bit)
RESERVED : Reserved
bits : 8 - 39 (32 bit)
Line Control Register. Contains controls for frame formatting and break generation.
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WLS : Word Length Select.
bits : 0 - 1 (2 bit)
Enumeration: ENUM
0x0 : 5_BIT_CHARACTER_LENG
5-bit character length.
0x1 : 6_BIT_CHARACTER_LENG
6-bit character length.
0x2 : 7_BIT_CHARACTER_LENG
7-bit character length.
0x3 : 8_BIT_CHARACTER_LENG
8-bit character length.
End of enumeration elements list.
SBS : Stop Bit Select.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : 1_STOP_BIT
1 stop bit.
1 : 2_STOP_BITS_1
2 stop bits (1.5 if LCR[1:0]=00).
End of enumeration elements list.
PE : Parity Enable
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : DISABLE_PARITY_GENER
Disable parity generation and checking.
1 : ENABLE_PARITY_GENERA
Enable parity generation and checking.
End of enumeration elements list.
PS : Parity Select.
bits : 4 - 9 (6 bit)
Enumeration: ENUM
0x0 : ODD_PARITY
Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.
0x1 : EVEN_PARITY
Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.
0x2 : FORCE_HIGH
Force HIGH. Forced 1 stick parity.
0x3 : FORCE_LOW
Force LOW. Forced 0 stick parity.
End of enumeration elements list.
BC : Break Control.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Disable break transmission.
1 : ENABLED
Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high.
End of enumeration elements list.
DLAB : Divisor Latch Access Bit.
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Disable access to Divisor Latches.
1 : ENABLED
Enabled. Enable access to Divisor Latches.
End of enumeration elements list.
RESERVED : Reserved
bits : 8 - 39 (32 bit)
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