\n
address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected
PWM Control read address
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUN0 : Stops/starts timer channel 0.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : STOP_
Stop.
1 : RUN_
Run.
End of enumeration elements list.
CENTER0 : Edge/center aligned operation for channel 0.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : EDGE_ALIGNED_
Edge-aligned.
1 : CENTER_ALIGNED_
Center-aligned.
End of enumeration elements list.
POLA0 : Selects polarity of the MCOA0 and MCOB0 pins.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : PASSIVE_STATE_IS_LOW
Passive state is LOW, active state is HIGH.
1 : PASSIVE_STATE_IS_HIG
Passive state is HIGH, active state is LOW.
End of enumeration elements list.
DTE0 : Controls the dead-time feature for channel 0.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : DEAD_TIME_DISABLED_
Dead-time disabled.
1 : DEAD_TIME_ENABLED_
Dead-time enabled.
End of enumeration elements list.
DISUP0 : Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : UPDATE
Functional registers are updated from the write registers at the end of each PWM cycle.
1 : NOUPDATE
Functional registers remain the same as long as the timer is running.
End of enumeration elements list.
RUN1 : Stops/starts timer channel 1.
bits : 8 - 16 (9 bit)
Enumeration: ENUM
0 : STOP_
Stop.
1 : RUN_
Run.
End of enumeration elements list.
CENTER1 : Edge/center aligned operation for channel 1.
bits : 9 - 18 (10 bit)
Enumeration: ENUM
0 : EDGE_ALIGNED_
Edge-aligned.
1 : CENTER_ALIGNED_
Center-aligned.
End of enumeration elements list.
POLA1 : Selects polarity of the MCOA1 and MCOB1 pins.
bits : 10 - 20 (11 bit)
Enumeration: ENUM
0 : PASSIVE_STATE_IS_LOW
Passive state is LOW, active state is HIGH.
1 : PASSIVE_STATE_IS_HIG
Passive state is HIGH, active state is LOW.
End of enumeration elements list.
DTE1 : Controls the dead-time feature for channel 1.
bits : 11 - 22 (12 bit)
Enumeration: ENUM
0 : DEAD_TIME_DISABLED_
Dead-time disabled.
1 : DEAD_TIME_ENABLED_
Dead-time enabled.
End of enumeration elements list.
DISUP1 : Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).
bits : 12 - 24 (13 bit)
Enumeration: ENUM
0 : UPDATE
Functional registers are updated from the write registers at the end of each PWM cycle.
1 : NOUPDATE
Functional registers remain the same as long as the timer is running.
End of enumeration elements list.
RESERVED : Reserved.
bits : 13 - 28 (16 bit)
RUN2 : Stops/starts timer channel 2.
bits : 16 - 32 (17 bit)
Enumeration: ENUM
0 : STOP_
Stop.
1 : RUN_
Run.
End of enumeration elements list.
CENTER2 : Edge/center aligned operation for channel 2.
bits : 17 - 34 (18 bit)
Enumeration: ENUM
0 : EDGE_ALIGNED_
Edge-aligned.
1 : CENTER_ALIGNED_
Center-aligned.
End of enumeration elements list.
POLA2 : Selects polarity of the MCOA2 and MCOB2 pins.
bits : 18 - 36 (19 bit)
Enumeration: ENUM
0 : PASSIVE_STATE_IS_LOW
Passive state is LOW, active state is HIGH.
1 : PASSIVE_STATE_IS_HIG
Passive state is HIGH, active state is LOW.
End of enumeration elements list.
DTE2 : Controls the dead-time feature for channel 1.
bits : 19 - 38 (20 bit)
Enumeration: ENUM
0 : DEAD_TIME_DISABLED_
Dead-time disabled.
1 : DEAD_TIME_ENABLED_
Dead-time enabled.
End of enumeration elements list.
DISUP2 : Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).
bits : 20 - 40 (21 bit)
Enumeration: ENUM
0 : UPDATE
Functional registers are updated from the write registers at the end of each PWM cycle.
1 : NOUPDATE
Functional registers remain the same as long as the timer is running.
End of enumeration elements list.
RESERVED : Reserved.
bits : 21 - 49 (29 bit)
RESERVED : Reserved.
bits : 21 - 49 (29 bit)
INVBDC : Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.
bits : 29 - 58 (30 bit)
Enumeration: ENUM
0 : OPPOSITE
The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time).
1 : SAME
The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)
End of enumeration elements list.
ACMODE : 3-phase AC mode select (see Section 24.8.7).
bits : 30 - 60 (31 bit)
Enumeration: ENUM
0 : 3_PHASE_AC_MODE_OFF
3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register.
1 : 3_PHASE_AC_MODE_ON_
3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0.
End of enumeration elements list.
DCMODE : 3-phase DC mode select (see Section 24.8.6).
bits : 31 - 62 (32 bit)
Enumeration: ENUM
0 : 3_PHASE_DC_MODE_OFF
3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)
1 : 3_PHASE_DC_MODE_ON_
3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs.
End of enumeration elements list.
Capture Control set address
address_offset : 0x10 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CAP0MCI0_RE_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 0 - 0 (1 bit)
CAP0MCI0_FE_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 1 - 2 (2 bit)
CAP0MCI1_RE_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 2 - 4 (3 bit)
CAP0MCI1_FE_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 3 - 6 (4 bit)
CAP0MCI2_RE_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 4 - 8 (5 bit)
CAP0MCI2_FE_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 5 - 10 (6 bit)
CAP1MCI0_RE_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 6 - 12 (7 bit)
CAP1MCI0_FE_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 7 - 14 (8 bit)
CAP1MCI1_RE_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 8 - 16 (9 bit)
CAP1MCI1_FE_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 9 - 18 (10 bit)
CAP1MCI2_RE_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 10 - 20 (11 bit)
CAP1MCI2_FE_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 11 - 22 (12 bit)
CAP2MCI0_RE_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 12 - 24 (13 bit)
CAP2MCI0_FE_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 13 - 26 (14 bit)
CAP2MCI1_RE_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 14 - 28 (15 bit)
CAP2MCI1_FE_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 15 - 30 (16 bit)
CAP2MCI2_RE_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 16 - 32 (17 bit)
CAP2MCI2_FE_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 17 - 34 (18 bit)
RT0_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 18 - 36 (19 bit)
RT1_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 19 - 38 (20 bit)
RT2_SET : Writing a one sets the corresponding bits in the CAPCON register.
bits : 20 - 40 (21 bit)
RESERVED : Reserved.
bits : 21 - 52 (32 bit)
Event Control clear address
address_offset : 0x14 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CAP0MCI0_RE_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 0 - 0 (1 bit)
CAP0MCI0_FE_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 1 - 2 (2 bit)
CAP0MCI1_RE_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 2 - 4 (3 bit)
CAP0MCI1_FE_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 3 - 6 (4 bit)
CAP0MCI2_RE_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 4 - 8 (5 bit)
CAP0MCI2_FE_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 5 - 10 (6 bit)
CAP1MCI0_RE_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 6 - 12 (7 bit)
CAP1MCI0_FE_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 7 - 14 (8 bit)
CAP1MCI1_RE_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 8 - 16 (9 bit)
CAP1MCI1_FE_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 9 - 18 (10 bit)
CAP1MCI2_RE_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 10 - 20 (11 bit)
CAP1MCI2_FE_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 11 - 22 (12 bit)
CAP2MCI0_RE_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 12 - 24 (13 bit)
CAP2MCI0_FE_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 13 - 26 (14 bit)
CAP2MCI1_RE_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 14 - 28 (15 bit)
CAP2MCI1_FE_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 15 - 30 (16 bit)
CAP2MCI2_RE_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 16 - 32 (17 bit)
CAP2MCI2_FE_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 17 - 34 (18 bit)
RT0_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 18 - 36 (19 bit)
RT1_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 19 - 38 (20 bit)
RT2_CLR : Writing a one clears the corresponding bits in the CAPCON register.
bits : 20 - 40 (21 bit)
RESERVED : Reserved.
bits : 21 - 52 (32 bit)
Timer Counter register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCTC : Timer/Counter value.
bits : 0 - 31 (32 bit)
Timer Counter register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCTC : Timer/Counter value.
bits : 0 - 31 (32 bit)
Timer Counter register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCTC : Timer/Counter value.
bits : 0 - 31 (32 bit)
Limit register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCLIM : Limit value.
bits : 0 - 31 (32 bit)
Limit register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCLIM : Limit value.
bits : 0 - 31 (32 bit)
Limit register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCLIM : Limit value.
bits : 0 - 31 (32 bit)
Match register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCMAT : Match value.
bits : 0 - 31 (32 bit)
Match register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCMAT : Match value.
bits : 0 - 31 (32 bit)
Match register
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCMAT : Match value.
bits : 0 - 31 (32 bit)
Dead time register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DT0 : Dead time for channel 0.[1]
bits : 0 - 9 (10 bit)
DT1 : Dead time for channel 1.[2]
bits : 10 - 29 (20 bit)
DT2 : Dead time for channel 2.[2]
bits : 20 - 49 (30 bit)
RESERVED : reserved
bits : 30 - 61 (32 bit)
PWM Control set address
address_offset : 0x4 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RUN0_SET : Writing a one sets the corresponding bit in the CON register.
bits : 0 - 0 (1 bit)
CENTER0_SET : Writing a one sets the corresponding bit in the CON register.
bits : 1 - 2 (2 bit)
POLA0_SET : Writing a one sets the corresponding bit in the CON register.
bits : 2 - 4 (3 bit)
DTE0_SET : Writing a one sets the corresponding bit in the CON register.
bits : 3 - 6 (4 bit)
DISUP0_SET : Writing a one sets the corresponding bit in the CON register.
bits : 4 - 8 (5 bit)
RUN1_SET : Writing a one sets the corresponding bit in the CON register.
bits : 8 - 16 (9 bit)
CENTER1_SET : Writing a one sets the corresponding bit in the CON register.
bits : 9 - 18 (10 bit)
POLA1_SET : Writing a one sets the corresponding bit in the CON register.
bits : 10 - 20 (11 bit)
DTE1_SET : Writing a one sets the corresponding bit in the CON register.
bits : 11 - 22 (12 bit)
DISUP1_SET : Writing a one sets the corresponding bit in the CON register.
bits : 12 - 24 (13 bit)
RESERVED : Writing a one sets the corresponding bit in the CON register.
bits : 13 - 28 (16 bit)
RUN2_SET : Writing a one sets the corresponding bit in the CON register.
bits : 16 - 32 (17 bit)
CENTER2_SET : Writing a one sets the corresponding bit in the CON register.
bits : 17 - 34 (18 bit)
POLA2_SET : Writing a one sets the corresponding bit in the CON register.
bits : 18 - 36 (19 bit)
DTE2_SET : Writing a one sets the corresponding bit in the CON register.
bits : 19 - 38 (20 bit)
DISUP2_SET : Writing a one sets the corresponding bit in the CON register.
bits : 20 - 40 (21 bit)
RESERVED : Writing a one sets the corresponding bit in the CON register.
bits : 21 - 49 (29 bit)
RESERVED : Writing a one sets the corresponding bit in the CON register.
bits : 21 - 49 (29 bit)
INVBDC_SET : Writing a one sets the corresponding bit in the CON register.
bits : 29 - 58 (30 bit)
ACMODE_SET : Writing a one sets the corresponding bit in the CON register.
bits : 30 - 60 (31 bit)
DCMODE_SET : Writing a one sets the corresponding bit in the CON register.
bits : 31 - 62 (32 bit)
Communication Pattern register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCPA0 : Communication pattern output A, channel 0.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : MCOA0_PASSIVE_
MCOA0 passive.
1 : INTERNAL_MCOA0_
internal MCOA0.
End of enumeration elements list.
CCPB0 : Communication pattern output B, channel 0.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : MCOB0_PASSIVE_
MCOB0 passive.
1 : MCOB0_TRACKS_INTERNA
MCOB0 tracks internal MCOA0.
End of enumeration elements list.
CCPA1 : Communication pattern output A, channel 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : MCOA1_PASSIVE_
MCOA1 passive.
1 : MCOA1_TRACKS_INTERNA
MCOA1 tracks internal MCOA0.
End of enumeration elements list.
CCPB1 : Communication pattern output B, channel 1.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : MCOB1_PASSIVE_
MCOB1 passive.
1 : MCOB1_TRACKS_INTERNA
MCOB1 tracks internal MCOA0.
End of enumeration elements list.
CCPA2 : Communication pattern output A, channel 2.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : MCOA2_PASSIVE_
MCOA2 passive.
1 : MCOA2_TRACKS_INTERNA
MCOA2 tracks internal MCOA0.
End of enumeration elements list.
CCPB2 : Communication pattern output B, channel 2.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : MCOB2_PASSIVE_
MCOB2 passive.
1 : MCOB2_TRACKS_INTERNA
MCOB2 tracks internal MCOA0.
End of enumeration elements list.
RESERVED : Reserved.
bits : 6 - 37 (32 bit)
Capture register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP : Current TC value at a capture event.
bits : 0 - 31 (32 bit)
Capture register
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP : Current TC value at a capture event.
bits : 0 - 31 (32 bit)
Capture register
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP : Current TC value at a capture event.
bits : 0 - 31 (32 bit)
Interrupt Enable read address
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ILIM0 : Limit interrupt for channel 0.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : INTERRUPT_DISABLED_
Interrupt disabled.
1 : INTERRUPT_ENABLED_
Interrupt enabled.
End of enumeration elements list.
IMAT0 : Match interrupt for channel 0.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : INTERRUPT_DISABLED_
Interrupt disabled.
1 : INTERRUPT_ENABLED_
Interrupt enabled.
End of enumeration elements list.
ICAP0 : Capture interrupt for channel 0.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : INTERRUPT_DISABLED_
Interrupt disabled.
1 : INTERRUPT_ENABLED_
Interrupt enabled.
End of enumeration elements list.
ILIM1 : Limit interrupt for channel 1.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : INTERRUPT_DISABLED_
Interrupt disabled.
1 : INTERRUPT_ENABLED_
Interrupt enabled.
End of enumeration elements list.
IMAT1 : Match interrupt for channel 1.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : INTERRUPT_DISABLED_
Interrupt disabled.
1 : INTERRUPT_ENABLED_
Interrupt enabled.
End of enumeration elements list.
ICAP1 : Capture interrupt for channel 1.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : INTERRUPT_DISABLED_
Interrupt disabled.
1 : INTERRUPT_ENABLED_
Interrupt enabled.
End of enumeration elements list.
RESERVED : Reserved.
bits : 7 - 14 (8 bit)
ILIM2 : Limit interrupt for channel 2.
bits : 8 - 16 (9 bit)
Enumeration: ENUM
0 : INTERRUPT_DISABLED_
Interrupt disabled.
1 : INTERRUPT_ENABLED_
Interrupt enabled.
End of enumeration elements list.
IMAT2 : Match interrupt for channel 2.
bits : 9 - 18 (10 bit)
Enumeration: ENUM
0 : INTERRUPT_DISABLED_
Interrupt disabled.
1 : INTERRUPT_ENABLED_
Interrupt enabled.
End of enumeration elements list.
ICAP2 : Capture interrupt for channel 2.
bits : 10 - 20 (11 bit)
Enumeration: ENUM
0 : INTERRUPT_DISABLED_
Interrupt disabled.
1 : INTERRUPT_ENABLED_
Interrupt enabled.
End of enumeration elements list.
RESERVED : Reserved.
bits : 11 - 25 (15 bit)
ABORT : Fast abort interrupt.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : INTERRUPT_DISABLED_
Interrupt disabled.
1 : INTERRUPT_ENABLED_
Interrupt enabled.
End of enumeration elements list.
RESERVED : Reserved.
bits : 16 - 47 (32 bit)
RESERVED : Reserved.
bits : 16 - 47 (32 bit)
Interrupt Enable set address
address_offset : 0x54 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ILIM0_SET : Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
bits : 0 - 0 (1 bit)
IMAT0_SET : Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
bits : 1 - 2 (2 bit)
ICAP0_SET : Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
bits : 2 - 4 (3 bit)
ILIM1_SET : Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
bits : 4 - 8 (5 bit)
IMAT1_SET : Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
bits : 5 - 10 (6 bit)
ICAP1_SET : Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
bits : 6 - 12 (7 bit)
RESERVED : Reserved.
bits : 7 - 14 (8 bit)
ILIM2_SET : Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
bits : 9 - 18 (10 bit)
IMAT2_SET : Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
bits : 10 - 20 (11 bit)
ICAP2_SET : Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
bits : 11 - 22 (12 bit)
RESERVED : Reserved.
bits : 12 - 26 (15 bit)
ABORT_SET : Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
bits : 15 - 30 (16 bit)
RESERVED : Reserved.
bits : 16 - 47 (32 bit)
RESERVED : Reserved.
bits : 16 - 47 (32 bit)
Interrupt Enable clear address
address_offset : 0x58 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ILIM0_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 0 - 0 (1 bit)
IMAT0_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 1 - 2 (2 bit)
ICAP0_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 2 - 4 (3 bit)
ILIM1_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 4 - 8 (5 bit)
IMAT1_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 5 - 10 (6 bit)
ICAP1_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 6 - 12 (7 bit)
RESERVED : Reserved.
bits : 7 - 14 (8 bit)
ILIM2_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 8 - 16 (9 bit)
IMAT2_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 9 - 18 (10 bit)
ICAP2_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 10 - 20 (11 bit)
RESERVED : Reserved.
bits : 11 - 25 (15 bit)
ABORT_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 15 - 30 (16 bit)
RESERVED : Reserved.
bits : 16 - 47 (32 bit)
RESERVED : Reserved.
bits : 16 - 47 (32 bit)
Count Control read address
address_offset : 0x5C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC0MCI0_RE : Counter 0 rising edge mode, channel 0.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOEFFECT
A rising edge on MCI0 does not affect counter 0.
1 : RISING
If MODE0 is 1, counter 0 advances on a rising edge on MCI0.
End of enumeration elements list.
TC0MCI0_FE : Counter 0 falling edge mode, channel 0.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : NOEFECT
A falling edge on MCI0 does not affect counter 0.
1 : FALLING
If MODE0 is 1, counter 0 advances on a falling edge on MCI0.
End of enumeration elements list.
TC0MCI1_RE : Counter 0 rising edge mode, channel 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOEFFECT
A rising edge on MCI1 does not affect counter 0.
1 : RISING
If MODE0 is 1, counter 0 advances on a rising edge on MCI1.
End of enumeration elements list.
TC0MCI1_FE : Counter 0 falling edge mode, channel 1.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOEFFECT
A falling edge on MCI1 does not affect counter 0.
1 : FALLING
If MODE0 is 1, counter 0 advances on a falling edge on MCI1.
End of enumeration elements list.
TC0MCI2_RE : Counter 0 rising edge mode, channel 2.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NOEFFECT
A rising edge on MCI0 does not affect counter 0.
1 : RISING
If MODE0 is 1, counter 0 advances on a rising edge on MCI2.
End of enumeration elements list.
TC0MCI2_FE : Counter 0 falling edge mode, channel 2.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NOEFFECT
A falling edge on MCI0 does not affect counter 0.
1 : FALLING
If MODE0 is 1, counter 0 advances on a falling edge on MCI2.
End of enumeration elements list.
TC1MCI0_RE : Counter 1 rising edge mode, channel 0.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : NOEFFECT
A rising edge on MCI0 does not affect counter 1.
1 : RISING
If MODE1 is 1, counter 1 advances on a rising edge on MCI0.
End of enumeration elements list.
TC1MCI0_FE : Counter 1 falling edge mode, channel 0.
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : RISING
A falling edge on MCI0 does not affect counter 1.
1 : FALLING
If MODE1 is 1, counter 1 advances on a falling edge on MCI0.
End of enumeration elements list.
TC1MCI1_RE : Counter 1 rising edge mode, channel 1.
bits : 8 - 16 (9 bit)
Enumeration: ENUM
0 : NOEFFECT
A rising edge on MCI1 does not affect counter 1.
1 : RISING
If MODE1 is 1, counter 1 advances on a rising edge on MCI1.
End of enumeration elements list.
TC1MCI1_FE : Counter 1 falling edge mode, channel 1.
bits : 9 - 18 (10 bit)
Enumeration: ENUM
0 : NOEFFECT
A falling edge on MCI0 does not affect counter 1.
1 : FALLING
If MODE1 is 1, counter 1 advances on a falling edge on MCI1.
End of enumeration elements list.
TC1MCI2_RE : Counter 1 rising edge mode, channel 2.
bits : 10 - 20 (11 bit)
Enumeration: ENUM
0 : NOEFFECT
A rising edge on MCI2 does not affect counter 1.
1 : RISING
If MODE1 is 1, counter 1 advances on a rising edge on MCI2.
End of enumeration elements list.
TC1MCI2_FE : Counter 1 falling edge mode, channel 2.
bits : 11 - 22 (12 bit)
Enumeration: ENUM
0 : NOEFFECT
A falling edge on MCI2 does not affect counter 1.
1 : RISING
If MODE1 is 1, counter 1 advances on a falling edge on MCI2.
End of enumeration elements list.
TC2MCI0_RE : Counter 2 rising edge mode, channel 0.
bits : 12 - 24 (13 bit)
Enumeration: ENUM
0 : NOEFFECT
A rising edge on MCI0 does not affect counter 2.
1 : FALLING
If MODE2 is 1, counter 2 advances on a rising edge on MCI0.
End of enumeration elements list.
TC2MCI0_FE : Counter 2 falling edge mode, channel 0.
bits : 13 - 26 (14 bit)
Enumeration: ENUM
0 : NOEFFECT
A falling edge on MCI0 does not affect counter 2.
1 : FALLING
If MODE2 is 1, counter 2 advances on a falling edge on MCI0.
End of enumeration elements list.
TC2MCI1_RE : Counter 2 rising edge mode, channel 1.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : NOEFFECT
A rising edge on MCI1 does not affect counter 2.
1 : FALLING
If MODE2 is 1, counter 2 advances on a rising edge on MCI1.
End of enumeration elements list.
TC2MCI1_FE : Counter 2 falling edge mode, channel 1.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : NOEFFECT
A falling edge on MCI1 does not affect counter 2.
1 : FALLING
If MODE2 is 1, counter 2 advances on a falling edge on MCI1.
End of enumeration elements list.
TC2MCI2_RE : Counter 2 rising edge mode, channel 2.
bits : 16 - 32 (17 bit)
Enumeration: ENUM
0 : NOEFFECT
A rising edge on MCI2 does not affect counter 2.
1 : FALLING
If MODE2 is 1, counter 2 advances on a rising edge on MCI2.
End of enumeration elements list.
TC2MCI2_FE : Counter 2 falling edge mode, channel 2.
bits : 17 - 34 (18 bit)
Enumeration: ENUM
0 : NOEFFECT
A falling edge on MCI2 does not affect counter 2.
1 : FALLING
If MODE2 is 1, counter 2 advances on a falling edge on MCI2.
End of enumeration elements list.
RESERVED : Reserved.
bits : 18 - 46 (29 bit)
CNTR0 : Channel 0 counter/timer mode.
bits : 29 - 58 (30 bit)
Enumeration: ENUM
0 : CHANNEL_0_IS_IN_TIME
Channel 0 is in timer mode.
1 : CHANNEL_0_IS_IN_COUN
Channel 0 is in counter mode.
End of enumeration elements list.
CNTR1 : Channel 1 counter/timer mode.
bits : 30 - 60 (31 bit)
Enumeration: ENUM
0 : CHANNEL_1_IS_IN_TIME
Channel 1 is in timer mode.
1 : CHANNEL_1_IS_IN_COUN
Channel 1 is in counter mode.
End of enumeration elements list.
CNTR2 : Channel 2 counter/timer mode.
bits : 31 - 62 (32 bit)
Enumeration: ENUM
0 : CHANNEL_2_IS_IN_TIME
Channel 2 is in timer mode.
1 : CHANNEL_2_IS_IN_COUN
Channel 2 is in counter mode.
End of enumeration elements list.
Count Control set address
address_offset : 0x60 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TC0MCI0_RE_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 0 - 0 (1 bit)
TC0MCI0_FE_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 1 - 2 (2 bit)
TC0MCI1_RE_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 2 - 4 (3 bit)
TC0MCI1_FE_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 3 - 6 (4 bit)
TC0MCI2_RE_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 4 - 8 (5 bit)
TC0MCI2_FE_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 5 - 10 (6 bit)
TC1MCI0_RE_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 6 - 12 (7 bit)
TC1MCI0_FE_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 7 - 14 (8 bit)
TC1MCI1_RE_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 8 - 16 (9 bit)
TC1MCI1_FE_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 9 - 18 (10 bit)
TC1MCI2_RE_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 10 - 20 (11 bit)
TC1MCI2_FE_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 11 - 22 (12 bit)
TC2MCI0_RE_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 12 - 24 (13 bit)
TC2MCI0_FE_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 13 - 26 (14 bit)
TC2MCI1_RE_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 14 - 28 (15 bit)
TC2MCI1_FE_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 15 - 30 (16 bit)
TC2MCI2_RE_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 16 - 32 (17 bit)
TC2MCI2_FE_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 17 - 34 (18 bit)
RESERVED : Reserved.
bits : 18 - 46 (29 bit)
CNTR0_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 29 - 58 (30 bit)
CNTR1_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 30 - 60 (31 bit)
CNTR2_SET : Writing a one sets the corresponding bit in the CNTCON register.
bits : 31 - 62 (32 bit)
Count Control clear address
address_offset : 0x64 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TC0MCI0_RE_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 0 - 0 (1 bit)
TC0MCI0_FE_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 1 - 2 (2 bit)
TC0MCI1_RE_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 2 - 4 (3 bit)
TC0MCI1_FE_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 3 - 6 (4 bit)
TC0MCI2_RE : Writing a one clears the corresponding bit in the CNTCON register.
bits : 4 - 8 (5 bit)
TC0MCI2_FE_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 5 - 10 (6 bit)
TC1MCI0_RE_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 6 - 12 (7 bit)
TC1MCI0_FE_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 7 - 14 (8 bit)
TC1MCI1_RE_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 8 - 16 (9 bit)
TC1MCI1_FE_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 9 - 18 (10 bit)
TC1MCI2_RE_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 10 - 20 (11 bit)
TC1MCI2_FE_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 11 - 22 (12 bit)
TC2MCI0_RE_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 12 - 24 (13 bit)
TC2MCI0_FE_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 13 - 26 (14 bit)
TC2MCI1_RE_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 14 - 28 (15 bit)
TC2MCI1_FE_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 15 - 30 (16 bit)
TC2MCI2_RE_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 16 - 32 (17 bit)
TC2MCI2_FE_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 17 - 34 (18 bit)
RESERVED : Reserved.
bits : 18 - 46 (29 bit)
CNTR0_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 29 - 58 (30 bit)
CNTR1_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 30 - 60 (31 bit)
CNTR2_CLR : Writing a one clears the corresponding bit in the CNTCON register.
bits : 31 - 62 (32 bit)
Interrupt flags read address
address_offset : 0x68 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ILIM0_F : Limit interrupt flag for channel 0.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : THIS_INTERRUPT_SOURC
This interrupt source is not contributing to the MCPWM interrupt request.
1 : IF_THE_CORRESPONDING
If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
End of enumeration elements list.
IMAT0_F : Match interrupt flag for channel 0.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : THIS_INTERRUPT_SOURC
This interrupt source is not contributing to the MCPWM interrupt request.
1 : IF_THE_CORRESPONDING
If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
End of enumeration elements list.
ICAP0_F : Capture interrupt flag for channel 0.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : THIS_INTERRUPT_SOURC
This interrupt source is not contributing to the MCPWM interrupt request.
1 : IF_THE_CORRESPONDING
If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
End of enumeration elements list.
ILIM1_F : Limit interrupt flag for channel 1.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : THIS_INTERRUPT_SOURC
This interrupt source is not contributing to the MCPWM interrupt request.
1 : IF_THE_CORRESPONDING
If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
End of enumeration elements list.
IMAT1_F : Match interrupt flag for channel 1.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : THIS_INTERRUPT_SOURC
This interrupt source is not contributing to the MCPWM interrupt request.
1 : IF_THE_CORRESPONDING
If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
End of enumeration elements list.
ICAP1_F : Capture interrupt flag for channel 1.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : THIS_INTERRUPT_SOURC
This interrupt source is not contributing to the MCPWM interrupt request.
1 : IF_THE_CORRESPONDING
If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
End of enumeration elements list.
RESERVED : Reserved.
bits : 7 - 14 (8 bit)
ILIM2_F : Limit interrupt flag for channel 2.
bits : 8 - 16 (9 bit)
Enumeration: ENUM
0 : THIS_INTERRUPT_SOURC
This interrupt source is not contributing to the MCPWM interrupt request.
1 : IF_THE_CORRESPONDING
If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
End of enumeration elements list.
IMAT2_F : Match interrupt flag for channel 2.
bits : 9 - 18 (10 bit)
Enumeration: ENUM
0 : THIS_INTERRUPT_SOURC
This interrupt source is not contributing to the MCPWM interrupt request.
1 : IF_THE_CORRESPONDING
If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
End of enumeration elements list.
ICAP2_F : Capture interrupt flag for channel 2.
bits : 10 - 20 (11 bit)
Enumeration: ENUM
0 : THIS_INTERRUPT_SOURC
This interrupt source is not contributing to the MCPWM interrupt request.
1 : IF_THE_CORRESPONDING
If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
End of enumeration elements list.
RESERVED : Reserved.
bits : 11 - 25 (15 bit)
ABORT_F : Fast abort interrupt flag.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : THIS_INTERRUPT_SOURC
This interrupt source is not contributing to the MCPWM interrupt request.
1 : IF_THE_CORRESPONDING
If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
End of enumeration elements list.
RESERVED : Reserved.
bits : 16 - 47 (32 bit)
RESERVED : Reserved.
bits : 16 - 47 (32 bit)
Interrupt flags set address
address_offset : 0x6C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ILIM0_F_SET : Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
bits : 0 - 0 (1 bit)
IMAT0_F_SET : Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
bits : 1 - 2 (2 bit)
ICAP0_F_SET : Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
bits : 2 - 4 (3 bit)
ILIM1_F_SET : Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
bits : 4 - 8 (5 bit)
IMAT1_F_SET : Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
bits : 5 - 10 (6 bit)
ICAP1_F_SET : Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
bits : 6 - 12 (7 bit)
RESERVED : Reserved.
bits : 7 - 14 (8 bit)
ILIM2_F_SET : Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
bits : 8 - 16 (9 bit)
IMAT2_F_SET : Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
bits : 9 - 18 (10 bit)
ICAP2_F_SET : Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
bits : 10 - 20 (11 bit)
RESERVED : Reserved.
bits : 11 - 25 (15 bit)
ABORT_F_SET : Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
bits : 15 - 30 (16 bit)
RESERVED : Reserved.
bits : 16 - 47 (32 bit)
RESERVED : Reserved.
bits : 16 - 47 (32 bit)
Interrupt flags clear address
address_offset : 0x70 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ILIM0_F_CLR : Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request.
bits : 0 - 0 (1 bit)
IMAT0_F_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 1 - 2 (2 bit)
ICAP0_F_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 2 - 4 (3 bit)
ILIM1_F_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 4 - 8 (5 bit)
IMAT1_F_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 5 - 10 (6 bit)
ICAP1_F_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 6 - 12 (7 bit)
RESERVED : Reserved.
bits : 7 - 14 (8 bit)
ILIM2_F_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 8 - 16 (9 bit)
IMAT2_F_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 9 - 18 (10 bit)
ICAP2_F_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 10 - 20 (11 bit)
RESERVED : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 11 - 25 (15 bit)
ABORT_F_CLR : Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
bits : 15 - 30 (16 bit)
RESERVED : Reserved.
bits : 16 - 47 (32 bit)
RESERVED : Reserved.
bits : 16 - 47 (32 bit)
Capture clear address
address_offset : 0x74 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CAP_CLR0 : Writing a 1 to this bit clears the CAP0 register.
bits : 0 - 0 (1 bit)
CAP_CLR1 : Writing a 1 to this bit clears the CAP1 register.
bits : 1 - 2 (2 bit)
CAP_CLR2 : Writing a 1 to this bit clears the CAP2 register.
bits : 2 - 4 (3 bit)
RESERVED : Reserved
bits : 3 - 34 (32 bit)
PWM Control clear address
address_offset : 0x8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RUN0_CLR : Writing a one clears the corresponding bit in the CON register.
bits : 0 - 0 (1 bit)
CENTER0_CLR : Writing a one clears the corresponding bit in the CON register.
bits : 1 - 2 (2 bit)
POLA0_CLR : Writing a one clears the corresponding bit in the CON register.
bits : 2 - 4 (3 bit)
DTE0_CLR : Writing a one clears the corresponding bit in the CON register.
bits : 3 - 6 (4 bit)
DISUP0_CLR : Writing a one clears the corresponding bit in the CON register.
bits : 4 - 8 (5 bit)
RUN1_CLR : Writing a one clears the corresponding bit in the CON register.
bits : 8 - 16 (9 bit)
CENTER1_CLR : Writing a one clears the corresponding bit in the CON register.
bits : 9 - 18 (10 bit)
POLA1_CLR : Writing a one clears the corresponding bit in the CON register.
bits : 10 - 20 (11 bit)
DTE1_CLR : Writing a one clears the corresponding bit in the CON register.
bits : 11 - 22 (12 bit)
DISUP1_CLR : Writing a one clears the corresponding bit in the CON register.
bits : 12 - 24 (13 bit)
RESERVED : Writing a one clears the corresponding bit in the CON register.
bits : 13 - 28 (16 bit)
RUN2_CLR : Writing a one clears the corresponding bit in the CON register.
bits : 16 - 32 (17 bit)
CENTER2_CLR : Writing a one clears the corresponding bit in the CON register.
bits : 17 - 34 (18 bit)
POLA2_CLR : Writing a one clears the corresponding bit in the CON register.
bits : 18 - 36 (19 bit)
DTE2_CLR : Writing a one clears the corresponding bit in the CON register.
bits : 19 - 38 (20 bit)
DISUP2_CLR : Writing a one clears the corresponding bit in the CON register.
bits : 20 - 40 (21 bit)
RESERVED : Writing a one clears the corresponding bit in the CON register.
bits : 21 - 49 (29 bit)
RESERVED : Writing a one clears the corresponding bit in the CON register.
bits : 21 - 49 (29 bit)
INVBDC_CLR : Writing a one clears the corresponding bit in the CON register.
bits : 29 - 58 (30 bit)
ACMOD_CLR : Writing a one clears the corresponding bit in the CON register.
bits : 30 - 60 (31 bit)
DCMODE_CLR : Writing a one clears the corresponding bit in the CON register.
bits : 31 - 62 (32 bit)
Capture Control read address
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP0MCI0_RE : A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0.
bits : 0 - 0 (1 bit)
CAP0MCI0_FE : A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0.
bits : 1 - 2 (2 bit)
CAP0MCI1_RE : A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1.
bits : 2 - 4 (3 bit)
CAP0MCI1_FE : A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1.
bits : 3 - 6 (4 bit)
CAP0MCI2_RE : A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2.
bits : 4 - 8 (5 bit)
CAP0MCI2_FE : A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2.
bits : 5 - 10 (6 bit)
CAP1MCI0_RE : A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0.
bits : 6 - 12 (7 bit)
CAP1MCI0_FE : A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0.
bits : 7 - 14 (8 bit)
CAP1MCI1_RE : A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1.
bits : 8 - 16 (9 bit)
CAP1MCI1_FE : A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1.
bits : 9 - 18 (10 bit)
CAP1MCI2_RE : A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2.
bits : 10 - 20 (11 bit)
CAP1MCI2_FE : A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2.
bits : 11 - 22 (12 bit)
CAP2MCI0_RE : A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0.
bits : 12 - 24 (13 bit)
CAP2MCI0_FE : A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0.
bits : 13 - 26 (14 bit)
CAP2MCI1_RE : A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1.
bits : 14 - 28 (15 bit)
CAP2MCI1_FE : A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1.
bits : 15 - 30 (16 bit)
CAP2MCI2_RE : A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2.
bits : 16 - 32 (17 bit)
CAP2MCI2_FE : A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2.
bits : 17 - 34 (18 bit)
RT0 : If this bit is 1, TC0 is reset by a channel 0 capture event.
bits : 18 - 36 (19 bit)
RT1 : If this bit is 1, TC1 is reset by a channel 1 capture event.
bits : 19 - 38 (20 bit)
RT2 : If this bit is 1, TC2 is reset by a channel 2 capture event.
bits : 20 - 40 (21 bit)
RESERVED : Reserved.
bits : 21 - 52 (32 bit)
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