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DMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected

Registers

STATUS

CHSTATUS

CHSWRCN

CHREQMSET

CHREQMCLR

CHENSET

CHENCLR

CHALTSET

CHALTCLR

CHHPSET

CHHPCLR

CONFIG

BERRCLR

BASEPTR

ABASEPTR


STATUS

Controller Status
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAENSTS STATE NUMCHAN

DMAENSTS : DMA Enable Status.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

DMA controller is disabled

1 : SET

DMA controller is enabled.

End of enumeration elements list.

STATE : State Machine State.
bits : 4 - 7 (4 bit)
access : read-only

Enumeration:

0 : IDLE

Idle.

1 : READING_CHANNEL_CONFIG

Reading channel controller data.

2 : READING_SOURCE_POINTER

Reading source data end pointer.

3 : READING_DEST_POINTER

Reading destination data end pointer.

4 : READING_SOURCE_DATA

Reading source data.

5 : WRITING_DEST_DATA

Writing destination data.

6 : WAITING_DMA_REQ_CLEAR

Waiting for a DMA request to clear.

7 : WRITING_CHANNEL_CONFIG

Writing channel controller data.

8 : STALLED

Stalled.

9 : DONE

Done.

10 : SCATTER_GATHER_TRANSITION

Peripheral scatter-gather transition.

End of enumeration elements list.

NUMCHAN : Number of Supported DMA Channels.
bits : 16 - 20 (5 bit)
access : read-only


CHSTATUS

Channel Status
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS CHSTATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15

CH0 : Channel 0 Status.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : NOT_WAITING

DMA Channel 0 is not waiting for a data request.

1 : WAITING

DMA Channel 0 is waiting for a data request.

End of enumeration elements list.

CH1 : Channel 1 Status.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : NOT_WAITING

DMA Channel 1 is not waiting for a data request.

1 : WAITING

DMA Channel 1 is waiting for a data request.

End of enumeration elements list.

CH2 : Channel 2 Status.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

0 : NOT_WAITING

DMA Channel 2 is not waiting for a data request.

1 : WAITING

DMA Channel 2 is waiting for a data request.

End of enumeration elements list.

CH3 : Channel 3 Status.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

0 : NOT_WAITING

DMA Channel 3 is not waiting for a data request.

1 : WAITING

DMA Channel 3 is waiting for a data request.

End of enumeration elements list.

CH4 : Channel 4 Status.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

0 : NOT_WAITING

DMA Channel 4 is not waiting for a data request.

1 : WAITING

DMA Channel 4 is waiting for a data request.

End of enumeration elements list.

CH5 : Channel 5 Status.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

0 : NOT_WAITING

DMA Channel 5 is not waiting for a data request.

1 : WAITING

DMA Channel 5 is waiting for a data request.

End of enumeration elements list.

CH6 : Channel 6 Status.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

0 : NOT_WAITING

DMA Channel 6 is not waiting for a data request.

1 : WAITING

DMA Channel 6 is waiting for a data request.

End of enumeration elements list.

CH7 : Channel 7 Status.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

0 : NOT_WAITING

DMA Channel 7 is not waiting for a data request.

1 : WAITING

DMA Channel 7 is waiting for a data request.

End of enumeration elements list.

CH8 : Channel 8 Status.
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

0 : NOT_WAITING

DMA Channel 8 is not waiting for a data request.

1 : WAITING

DMA Channel 8 is waiting for a data request.

End of enumeration elements list.

CH9 : Channel 9 Status.
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

0 : NOT_WAITING

DMA Channel 9 is not waiting for a data request.

1 : WAITING

DMA Channel 9 is waiting for a data request.

End of enumeration elements list.

CH10 : Channel 10 Status.
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0 : NOT_WAITING

DMA Channel 10 is not waiting for a data request.

1 : WAITING

DMA Channel 10 is waiting for a data request.

End of enumeration elements list.

CH11 : Channel 11 Status.
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

0 : NOT_WAITING

DMA Channel 11 is not waiting for a data request.

1 : WAITING

DMA Channel 11 is waiting for a data request.

End of enumeration elements list.

CH12 : Channel 12 Status.
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

0 : NOT_WAITING

DMA Channel 12 is not waiting for a data request.

1 : WAITING

DMA Channel 12 is waiting for a data request.

End of enumeration elements list.

CH13 : Channel 13 Status.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0 : NOT_WAITING

DMA Channel 13 is not waiting for a data request.

1 : WAITING

DMA Channel 13 is waiting for a data request.

End of enumeration elements list.

CH14 : Channel 14 Status.
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0 : NOT_WAITING

DMA Channel 14 is not waiting for a data request.

1 : WAITING

DMA Channel 14 is waiting for a data request.

End of enumeration elements list.

CH15 : Channel 15 Status.
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

0 : NOT_WAITING

DMA Channel 15 is not waiting for a data request.

1 : WAITING

DMA Channel 15 is waiting for a data request.

End of enumeration elements list.


CHSWRCN

Channel Software Request Control
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSWRCN CHSWRCN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15

CH0 : Channel 0 Software Request.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

0 : DO_NOT_GENERATE_SW_REQ

DMA Channel 0 does not generate a software data request.

1 : GENERATE_SW_REQ

DMA Channel 0 generates a software data request.

End of enumeration elements list.

CH1 : Channel 1 Software Request.
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

0 : DO_NOT_GENERATE_SW_REQ

DMA Channel 1 does not generate a software data request.

1 : GENERATE_SW_REQ

DMA Channel 1 generates a software data request.

End of enumeration elements list.

CH2 : Channel 2 Software Request.
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

0 : DO_NOT_GENERATE_SW_REQ

DMA Channel 2 does not generate a software data request.

1 : GENERATE_SW_REQ

DMA Channel 2 generates a software data request.

End of enumeration elements list.

CH3 : Channel 3 Software Request.
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

0 : DO_NOT_GENERATE_SW_REQ

DMA Channel 3 does not generate a software data request.

1 : GENERATE_SW_REQ

DMA Channel 3 generates a software data request.

End of enumeration elements list.

CH4 : Channel 4 Software Request.
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

0 : DO_NOT_GENERATE_SW_REQ

DMA Channel 4 does not generate a software data request.

1 : GENERATE_SW_REQ

DMA Channel 4 generates a software data request.

End of enumeration elements list.

CH5 : Channel 5 Software Request.
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

0 : DO_NOT_GENERATE_SW_REQ

DMA Channel 5 does not generate a software data request.

1 : GENERATE_SW_REQ

DMA Channel 5 generates a software data request.

End of enumeration elements list.

CH6 : Channel 6 Software Request.
bits : 6 - 6 (1 bit)
access : write-only

Enumeration:

0 : DO_NOT_GENERATE_SW_REQ

DMA Channel 6 does not generate a software data request.

1 : GENERATE_SW_REQ

DMA Channel 6 generates a software data request.

End of enumeration elements list.

CH7 : Channel 7 Software Request.
bits : 7 - 7 (1 bit)
access : write-only

Enumeration:

0 : DO_NOT_GENERATE_SW_REQ

DMA Channel 7 does not generate a software data request.

1 : GENERATE_SW_REQ

DMA Channel 7 generates a software data request.

End of enumeration elements list.

CH8 : Channel 8 Software Request.
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0 : DO_NOT_GENERATE_SW_REQ

DMA Channel 8 does not generate a software data request.

1 : GENERATE_SW_REQ

DMA Channel 8 generates a software data request.

End of enumeration elements list.

CH9 : Channel 9 Software Request.
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0 : DO_NOT_GENERATE_SW_REQ

DMA Channel 9 does not generate a software data request.

1 : GENERATE_SW_REQ

DMA Channel 9 generates a software data request.

End of enumeration elements list.

CH10 : Channel 10 Software Request.
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0 : DO_NOT_GENERATE_SW_REQ

DMA Channel 10 does not generate a software data request.

1 : GENERATE_SW_REQ

DMA Channel 10 generates a software data request.

End of enumeration elements list.

CH11 : Channel 11 Software Request.
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0 : DO_NOT_GENERATE_SW_REQ

DMA Channel 11 does not generate a software data request.

1 : GENERATE_SW_REQ

DMA Channel 11 generates a software data request.

End of enumeration elements list.

CH12 : Channel 12 Software Request.
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0 : DO_NOT_GENERATE_SW_REQ

DMA Channel 12 does not generate a software data request.

1 : GENERATE_SW_REQ

DMA Channel 12 generates a software data request.

End of enumeration elements list.

CH13 : Channel 13 Software Request.
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0 : DO_NOT_GENERATE_SW_REQ

DMA Channel 13 does not generate a software data request.

1 : GENERATE_SW_REQ

DMA Channel 13 generates a software data request.

End of enumeration elements list.

CH14 : Channel 14 Software Request.
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0 : DO_NOT_GENERATE_SW_REQ

DMA Channel 14 does not generate a software data request.

1 : GENERATE_SW_REQ

DMA Channel 14 generates a software data request.

End of enumeration elements list.

CH15 : Channel 15 Software Request.
bits : 15 - 15 (1 bit)
access : write-only

Enumeration:

0 : DO_NOT_GENERATE_SW_REQ

DMA Channel 15 does not generate a software data request.

1 : GENERATE_SW_REQ

DMA Channel 15 generates a software data request.

End of enumeration elements list.


CHREQMSET

Channel Request Mask Set
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHREQMSET CHREQMSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15

CH0 : Channel 0 Request Mask Enable.
bits : 0 - 0 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 0 peripheral data requests enabled. 1: DMA Channel 0 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 0 peripheral data requests.

End of enumeration elements list.

CH1 : Channel 1 Request Mask Enable.
bits : 1 - 1 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 1 peripheral data requests enabled. 1: DMA Channel 1 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 1 peripheral data requests.

End of enumeration elements list.

CH2 : Channel 2 Request Mask Enable.
bits : 2 - 2 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 2 peripheral data requests enabled. 1: DMA Channel 2 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 2 peripheral data requests.

End of enumeration elements list.

CH3 : Channel 3 Request Mask Enable.
bits : 3 - 3 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 3 peripheral data requests enabled. 1: DMA Channel 3 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 3 peripheral data requests.

End of enumeration elements list.

CH4 : Channel 4 Request Mask Enable.
bits : 4 - 4 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 4 peripheral data requests enabled. 1: DMA Channel 4 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 4 peripheral data requests.

End of enumeration elements list.

CH5 : Channel 5 Request Mask Enable.
bits : 5 - 5 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 5 peripheral data requests enabled. 1: DMA Channel 5 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 5 peripheral data requests.

End of enumeration elements list.

CH6 : Channel 6 Request Mask Enable.
bits : 6 - 6 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 6 peripheral data requests enabled. 1: DMA Channel 6 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 6 peripheral data requests.

End of enumeration elements list.

CH7 : Channel 7 Request Mask Enable.
bits : 7 - 7 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 7 peripheral data requests enabled. 1: DMA Channel 7 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 7 peripheral data requests.

End of enumeration elements list.

CH8 : Channel 8 Request Mask Enable.
bits : 8 - 8 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 8 peripheral data requests enabled. 1: DMA Channel 8 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 8 peripheral data requests.

End of enumeration elements list.

CH9 : Channel 9 Request Mask Enable.
bits : 9 - 9 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 9 peripheral data requests enabled. 1: DMA Channel 9 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 9 peripheral data requests.

End of enumeration elements list.

CH10 : Channel 10 Request Mask Enable.
bits : 10 - 10 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 10 peripheral data requests enabled. 1: DMA Channel 10 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 10 peripheral data requests.

End of enumeration elements list.

CH11 : Channel 11 Request Mask Enable.
bits : 11 - 11 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 11 peripheral data requests enabled. 1: DMA Channel 11 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 11 peripheral data requests.

End of enumeration elements list.

CH12 : Channel 12 Request Mask Enable.
bits : 12 - 12 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 12 peripheral data requests enabled. 1: DMA Channel 12 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 12 peripheral data requests.

End of enumeration elements list.

CH13 : Channel 13 Request Mask Enable.
bits : 13 - 13 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 13 peripheral data requests enabled. 1: DMA Channel 13 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 13 peripheral data requests.

End of enumeration elements list.

CH14 : Channel 14 Request Mask Enable.
bits : 14 - 14 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 14 peripheral data requests enabled. 1: DMA Channel 14 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 14 peripheral data requests.

End of enumeration elements list.

CH15 : Channel 15 Request Mask Enable.
bits : 15 - 15 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 15 peripheral data requests enabled. 1: DMA Channel 15 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 15 peripheral data requests.

End of enumeration elements list.


CHREQMCLR

Channel Request Mask Clear
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHREQMCLR CHREQMCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15

CH0 : Channel 0 Request Mask Disable.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Enable DMA Channel 0 peripheral data requests.

End of enumeration elements list.

CH1 : Channel 1 Request Mask Disable.
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Enable DMA Channel 1 peripheral data requests.

End of enumeration elements list.

CH2 : Channel 2 Request Mask Disable.
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Enable DMA Channel 2 peripheral data requests.

End of enumeration elements list.

CH3 : Channel 3 Request Mask Disable.
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Enable DMA Channel 3 peripheral data requests.

End of enumeration elements list.

CH4 : Channel 4 Request Mask Disable.
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Enable DMA Channel 4 peripheral data requests.

End of enumeration elements list.

CH5 : Channel 5 Request Mask Disable.
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Enable DMA Channel 5 peripheral data requests.

End of enumeration elements list.

CH6 : Channel 6 Request Mask Disable.
bits : 6 - 6 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Enable DMA Channel 6 peripheral data requests.

End of enumeration elements list.

CH7 : Channel 7 Request Mask Disable.
bits : 7 - 7 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Enable DMA Channel 7 peripheral data requests.

End of enumeration elements list.

CH8 : Channel 8 Request Mask Disable.
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Enable DMA Channel 8 peripheral data requests.

End of enumeration elements list.

CH9 : Channel 9 Request Mask Disable.
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Enable DMA Channel 9 peripheral data requests.

End of enumeration elements list.

CH10 : Channel 10 Request Mask Disable.
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Enable DMA Channel 10 peripheral data requests.

End of enumeration elements list.

CH11 : Channel 11 Request Mask Disable.
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Enable DMA Channel 11 peripheral data requests.

End of enumeration elements list.

CH12 : Channel 12 Request Mask Disable.
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Enable DMA Channel 12 peripheral data requests.

End of enumeration elements list.

CH13 : Channel 13 Request Mask Disable.
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Enable DMA Channel 13 peripheral data requests.

End of enumeration elements list.

CH14 : Channel 14 Request Mask Disable.
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Enable DMA Channel 14 peripheral data requests.

End of enumeration elements list.

CH15 : Channel 15 Request Mask Disable.
bits : 15 - 15 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Enable DMA Channel 15 peripheral data requests.

End of enumeration elements list.


CHENSET

Channel Enable Set
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHENSET CHENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15

CH0 : Channel 0 Enable.
bits : 0 - 0 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 0 disabled. 1: DMA Channel 0 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 0.

End of enumeration elements list.

CH1 : Channel 1 Enable.
bits : 1 - 1 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 1 disabled. 1: DMA Channel 1 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 1.

End of enumeration elements list.

CH2 : Channel 2 Enable.
bits : 2 - 2 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 2 disabled. 1: DMA Channel 2 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 2.

End of enumeration elements list.

CH3 : Channel 3 Enable.
bits : 3 - 3 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 3 disabled. 1: DMA Channel 3 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 3.

End of enumeration elements list.

CH4 : Channel 4 Enable.
bits : 4 - 4 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 4 disabled. 1: DMA Channel 4 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 4.

End of enumeration elements list.

CH5 : Channel 5 Enable.
bits : 5 - 5 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 5 disabled. 1: DMA Channel 5 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 5.

End of enumeration elements list.

CH6 : Channel 6 Enable.
bits : 6 - 6 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 6 disabled. 1: DMA Channel 6 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 6.

End of enumeration elements list.

CH7 : Channel 7 Enable.
bits : 7 - 7 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 7 disabled. 1: DMA Channel 7 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 7.

End of enumeration elements list.

CH8 : Channel 8 Enable.
bits : 8 - 8 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 8 disabled. 1: DMA Channel 8 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 8.

End of enumeration elements list.

CH9 : Channel 9 Enable.
bits : 9 - 9 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 9 disabled. 1: DMA Channel 9 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 9.

End of enumeration elements list.

CH10 : Channel 10 Enable.
bits : 10 - 10 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 10 disabled. 1: DMA Channel 10 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 10.

End of enumeration elements list.

CH11 : Channel 11 Enable.
bits : 11 - 11 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 11 disabled. 1: DMA Channel 11 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 11.

End of enumeration elements list.

CH12 : Channel 12 Enable.
bits : 12 - 12 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 12 disabled. 1: DMA Channel 12 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 12.

End of enumeration elements list.

CH13 : Channel 13 Enable.
bits : 13 - 13 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 13 disabled. 1: DMA Channel 13 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 13.

End of enumeration elements list.

CH14 : Channel 14 Enable.
bits : 14 - 14 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 14 disabled. 1: DMA Channel 14 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 14.

End of enumeration elements list.

CH15 : Channel 15 Enable.
bits : 15 - 15 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 15 disabled. 1: DMA Channel 15 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 15.

End of enumeration elements list.


CHENCLR

Channel Enable Clear
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHENCLR CHENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15

CH0 : Channel 0 Disable.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Disable DMA Channel 0.

End of enumeration elements list.

CH1 : Channel 1 Disable.
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Disable DMA Channel 1.

End of enumeration elements list.

CH2 : Channel 2 Disable.
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Disable DMA Channel 2.

End of enumeration elements list.

CH3 : Channel 3 Disable.
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Disable DMA Channel 3.

End of enumeration elements list.

CH4 : Channel 4 Disable.
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Disable DMA Channel 4.

End of enumeration elements list.

CH5 : Channel 5 Disable.
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Disable DMA Channel 5.

End of enumeration elements list.

CH6 : Channel 6 Disable.
bits : 6 - 6 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Disable DMA Channel 6.

End of enumeration elements list.

CH7 : Channel 7 Disable.
bits : 7 - 7 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Disable DMA Channel 7.

End of enumeration elements list.

CH8 : Channel 8 Disable.
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Disable DMA Channel 8.

End of enumeration elements list.

CH9 : Channel 9 Disable.
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Disable DMA Channel 9.

End of enumeration elements list.

CH10 : Channel 10 Disable.
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Disable DMA Channel 10.

End of enumeration elements list.

CH11 : Channel 11 Disable.
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Disable DMA Channel 11.

End of enumeration elements list.

CH12 : Channel 12 Disable.
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Disable DMA Channel 12.

End of enumeration elements list.

CH13 : Channel 13 Disable.
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Disable DMA Channel 13.

End of enumeration elements list.

CH14 : Channel 14 Disable.
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Disable DMA Channel 14.

End of enumeration elements list.

CH15 : Channel 15 Disable.
bits : 15 - 15 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Disable DMA Channel 15.

End of enumeration elements list.


CHALTSET

Channel Alternate Select Set
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHALTSET CHALTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15

CH0 : Channel 0 Alternate Enable.
bits : 0 - 0 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 0 is using primary data structure. 1: DMA Channel 0 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 0.

End of enumeration elements list.

CH1 : Channel 1 Alternate Enable.
bits : 1 - 1 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 1 is using primary data structure. 1: DMA Channel 1 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 1.

End of enumeration elements list.

CH2 : Channel 2 Alternate Enable.
bits : 2 - 2 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 2 is using primary data structure. 1: DMA Channel 2 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 2.

End of enumeration elements list.

CH3 : Channel 3 Alternate Enable.
bits : 3 - 3 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 3 is using primary data structure. 1: DMA Channel 3 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 3.

End of enumeration elements list.

CH4 : Channel 4 Alternate Enable.
bits : 4 - 4 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 4 is using primary data structure. 1: DMA Channel 4 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 4.

End of enumeration elements list.

CH5 : Channel 5 Alternate Enable.
bits : 5 - 5 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 5 is using primary data structure. 1: DMA Channel 5 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 5.

End of enumeration elements list.

CH6 : Channel 6 Alternate Enable.
bits : 6 - 6 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 6 is using primary data structure. 1: DMA Channel 6 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 6.

End of enumeration elements list.

CH7 : Channel 7 Alternate Enable.
bits : 7 - 7 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 7 is using primary data structure. 1: DMA Channel 7 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 7.

End of enumeration elements list.

CH8 : Channel 8 Alternate Enable.
bits : 8 - 8 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 8 is using primary data structure. 1: DMA Channel 8 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 8.

End of enumeration elements list.

CH9 : Channel 9 Alternate Enable.
bits : 9 - 9 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 9 is using primary data structure. 1: DMA Channel 9 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 9.

End of enumeration elements list.

CH10 : Channel 10 Alternate Enable.
bits : 10 - 10 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 10 is using primary data structure. 1: DMA Channel 10 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 10.

End of enumeration elements list.

CH11 : Channel 11 Alternate Enable.
bits : 11 - 11 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 11 is using primary data structure. 1: DMA Channel 11 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 11.

End of enumeration elements list.

CH12 : Channel 12 Alternate Enable.
bits : 12 - 12 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 12 is using primary data structure. 1: DMA Channel 12 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 12.

End of enumeration elements list.

CH13 : Channel 13 Alternate Enable.
bits : 13 - 13 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 13 is using primary data structure. 1: DMA Channel 13 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 13.

End of enumeration elements list.

CH14 : Channel 14 Alternate Enable.
bits : 14 - 14 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 14 is using primary data structure. 1: DMA Channel 14 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 14.

End of enumeration elements list.

CH15 : Channel 15 Alternate Enable.
bits : 15 - 15 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 15 is using primary data structure. 1: DMA Channel 15 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 15.

End of enumeration elements list.


CHALTCLR

Channel Alternate Select Clear
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHALTCLR CHALTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15

CH0 : Channel 0 Alternate Disable.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the primary data structure for DMA Channel 0.

End of enumeration elements list.

CH1 : Channel 1 Alternate Disable.
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the primary data structure for DMA Channel 1.

End of enumeration elements list.

CH2 : Channel 2 Alternate Disable.
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the primary data structure for DMA Channel 2.

End of enumeration elements list.

CH3 : Channel 3 Alternate Disable.
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the primary data structure for DMA Channel 3.

End of enumeration elements list.

CH4 : Channel 4 Alternate Disable.
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the primary data structure for DMA Channel 4.

End of enumeration elements list.

CH5 : Channel 5 Alternate Disable.
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the primary data structure for DMA Channel 5.

End of enumeration elements list.

CH6 : Channel 6 Alternate Disable.
bits : 6 - 6 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the primary data structure for DMA Channel 6.

End of enumeration elements list.

CH7 : Channel 7 Alternate Disable.
bits : 7 - 7 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the primary data structure for DMA Channel 7.

End of enumeration elements list.

CH8 : Channel 8 Alternate Disable.
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the primary data structure for DMA Channel 8.

End of enumeration elements list.

CH9 : Channel 9 Alternate Disable.
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the primary data structure for DMA Channel 9.

End of enumeration elements list.

CH10 : Channel 10 Alternate Disable.
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the primary data structure for DMA Channel 10.

End of enumeration elements list.

CH11 : Channel 11 Alternate Disable.
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the primary data structure for DMA Channel 11.

End of enumeration elements list.

CH12 : Channel 12 Alternate Disable.
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the primary data structure for DMA Channel 12.

End of enumeration elements list.

CH13 : Channel 13 Alternate Disable.
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the primary data structure for DMA Channel 13.

End of enumeration elements list.

CH14 : Channel 14 Alternate Disable.
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the primary data structure for DMA Channel 14.

End of enumeration elements list.

CH15 : Channel 15 Alternate Disable.
bits : 15 - 15 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the primary data structure for DMA Channel 15.

End of enumeration elements list.


CHHPSET

Channel High Priority Set
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHHPSET CHHPSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15

CH0 : Channel 0 High Priority Enable.
bits : 0 - 0 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 0 is using the default priority level. 1: DMA Channel 0 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 0.

End of enumeration elements list.

CH1 : Channel 1 High Priority Enable.
bits : 1 - 1 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 1 is using the default priority level. 1: DMA Channel 1 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 1.

End of enumeration elements list.

CH2 : Channel 2 High Priority Enable.
bits : 2 - 2 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 2 is using the default priority level. 1: DMA Channel 2 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 2.

End of enumeration elements list.

CH3 : Channel 3 High Priority Enable.
bits : 3 - 3 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 3 is using the default priority level. 1: DMA Channel 3 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 3.

End of enumeration elements list.

CH4 : Channel 4 High Priority Enable.
bits : 4 - 4 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 4 is using the default priority level. 1: DMA Channel 4 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 4.

End of enumeration elements list.

CH5 : Channel 5 High Priority Enable.
bits : 5 - 5 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 5 is using the default priority level. 1: DMA Channel 5 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 5.

End of enumeration elements list.

CH6 : Channel 6 High Priority Enable.
bits : 6 - 6 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 6 is using the default priority level. 1: DMA Channel 6 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 6.

End of enumeration elements list.

CH7 : Channel 7 High Priority Enable.
bits : 7 - 7 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 7 is using the default priority level. 1: DMA Channel 7 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 7.

End of enumeration elements list.

CH8 : Channel 8 High Priority Enable.
bits : 8 - 8 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 8 is using the default priority level. 1: DMA Channel 8 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 8.

End of enumeration elements list.

CH9 : Channel 9 High Priority Enable.
bits : 9 - 9 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 9 is using the default priority level. 1: DMA Channel 9 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 9.

End of enumeration elements list.

CH10 : Channel 10 High Priority Enable.
bits : 10 - 10 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 10 is using the default priority level. 1: DMA Channel 10 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 10.

End of enumeration elements list.

CH11 : Channel 11 High Priority Enable.
bits : 11 - 11 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 11 is using the default priority level. 1: DMA Channel 11 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 11.

End of enumeration elements list.

CH12 : Channel 12 High Priority Enable.
bits : 12 - 12 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 12 is using the default priority level. 1: DMA Channel 12 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 12.

End of enumeration elements list.

CH13 : Channel 13 High Priority Enable.
bits : 13 - 13 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 13 is using the default priority level. 1: DMA Channel 13 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 13.

End of enumeration elements list.

CH14 : Channel 14 High Priority Enable.
bits : 14 - 14 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 14 is using the default priority level. 1: DMA Channel 14 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 14.

End of enumeration elements list.

CH15 : Channel 15 High Priority Enable.
bits : 15 - 15 (1 bit)

Enumeration:

1 : ENABLED

Read: 0: DMA Channel 15 is using the default priority level. 1: DMA Channel 15 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 15.

End of enumeration elements list.


CHHPCLR

Channel High Priority Clear
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHHPCLR CHHPCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15

CH0 : Channel 0 High Priority Disable.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the high default level for DMA Channel 0.

End of enumeration elements list.

CH1 : Channel 1 High Priority Disable.
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the high default level for DMA Channel 1.

End of enumeration elements list.

CH2 : Channel 2 High Priority Disable.
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the high default level for DMA Channel 2.

End of enumeration elements list.

CH3 : Channel 3 High Priority Disable.
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the high default level for DMA Channel 3.

End of enumeration elements list.

CH4 : Channel 4 High Priority Disable.
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the high default level for DMA Channel 4.

End of enumeration elements list.

CH5 : Channel 5 High Priority Disable.
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the high default level for DMA Channel 5.

End of enumeration elements list.

CH6 : Channel 6 High Priority Disable.
bits : 6 - 6 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the high default level for DMA Channel 6.

End of enumeration elements list.

CH7 : Channel 7 High Priority Disable.
bits : 7 - 7 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the high default level for DMA Channel 7.

End of enumeration elements list.

CH8 : Channel 8 High Priority Disable.
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the high default level for DMA Channel 8.

End of enumeration elements list.

CH9 : Channel 9 High Priority Disable.
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the high default level for DMA Channel 9.

End of enumeration elements list.

CH10 : Channel 10 High Priority Disable.
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the high default level for DMA Channel 10.

End of enumeration elements list.

CH11 : Channel 11 High Priority Disable.
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the high default level for DMA Channel 11.

End of enumeration elements list.

CH12 : Channel 12 High Priority Disable.
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the high default level for DMA Channel 12.

End of enumeration elements list.

CH13 : Channel 13 High Priority Disable.
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the high default level for DMA Channel 13.

End of enumeration elements list.

CH14 : Channel 14 High Priority Disable.
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the high default level for DMA Channel 14.

End of enumeration elements list.

CH15 : Channel 15 High Priority Disable.
bits : 15 - 15 (1 bit)
access : write-only

Enumeration:

0 : RESERVED

No effect.

1 : DISABLED

Use the high default level for DMA Channel 15.

End of enumeration elements list.


CONFIG

Controller Configuration
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAEN

DMAEN : DMA Enable.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

0 : DISABLED

Disable the DMA controller.

1 : ENABLED

Enable the DMA controller.

End of enumeration elements list.


BERRCLR

Bus Error Clear
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BERRCLR BERRCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERROR

ERROR : DMA Bus Error Clear.
bits : 0 - 0 (1 bit)

Enumeration:

1 : CLEAR

Read: 0: DMA error did not occur. 1: DMA error occurred since the last time ERROR was cleared. Write: 0: No effect. 1: Clear the DMA error flag.

End of enumeration elements list.


BASEPTR

Base Pointer
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BASEPTR BASEPTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASEPTR

BASEPTR : Control Base Pointer.
bits : 5 - 31 (27 bit)


ABASEPTR

Alternate Base Pointer
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ABASEPTR ABASEPTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ABASEPTR

ABASEPTR : Alternate Control Base Pointer.
bits : 0 - 31 (32 bit)
access : read-only



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