\n
address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected
Module Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IF0EN : Interface 0 Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
Disable interface 0.
1 : ENABLED
Enable interface 0.
End of enumeration elements list.
IF1EN : Interface 1 Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable interface 1.
1 : ENABLED
Enable interface 1.
End of enumeration elements list.
OFFSTEN : OFF Output State Enable.
bits : 4 - 4 (1 bit)
Enumeration:
0 : DISABLED
EMIF will not enter the off state after 4 idle cycles.
1 : ENABLED
EMIF will enter the off state after 4 idle cycles.
End of enumeration elements list.
Interface Configuration
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSWIDTH : Interface Bus Data Width.
bits : 0 - 0 (1 bit)
Enumeration:
0 : 8BIT
The data bus is 8-bits wide.
1 : 16BIT
The data bus is 16-bits wide.
End of enumeration elements list.
MUXMD : Interface Mux Mode.
bits : 2 - 2 (1 bit)
Enumeration:
0 : NONMUXED
The interface operates in non-multiplexed mode.
1 : MUXED
The interface operates in multiplexed mode.
End of enumeration elements list.
ASEN : Interface Automatic Address Shift Enable.
bits : 3 - 3 (1 bit)
Enumeration:
0 : DISABLED
The address is not automatically shifted.
1 : ENABLED
The address is automatically shifted.
End of enumeration elements list.
ROEN : Interface Read Only Enable.
bits : 4 - 4 (1 bit)
Enumeration:
0 : DISABLED
The interface supports reads and writes.
1 : ENABLED
The interface supports only reads.
End of enumeration elements list.
WDHINH : Write Data Hold State Inhibit.
bits : 8 - 8 (1 bit)
Enumeration:
0 : INACTIVE
Enable the write data hold state.
1 : ACTIVE
Inhibit the write data hold state.
End of enumeration elements list.
DELAYOE : Output Enable Delay.
bits : 12 - 12 (1 bit)
Enumeration:
0 : DISABLED
The output enable signal (/OE) is not delayed.
1 : ENABLED
The output enable signal (/OE) is delayed.
End of enumeration elements list.
KLREN : Keep Last Read Enable.
bits : 16 - 16 (1 bit)
Enumeration:
0 : DISABLED
The bus is driven to the idle state between active requests.
1 : ENABLED
The bus drives the last value read on the interface between active requests.
End of enumeration elements list.
Interface Read Timing
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RASET : Interface Read Address Setup Delay .
bits : 0 - 3 (4 bit)
RAHOLD : Interface Read Address Hold Delay.
bits : 4 - 7 (4 bit)
RDHOLD : Interface Read Data Hold Delay.
bits : 8 - 11 (4 bit)
RDWAIT : Interface Read Data Wait Delay.
bits : 16 - 21 (6 bit)
Interface Write Timing
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WASET : Interface Write Address Setup Delay .
bits : 0 - 3 (4 bit)
WAHOLD : Interface Write Address Hold Delay.
bits : 4 - 7 (4 bit)
WDHOLD : Interface Write Data Hold Delay.
bits : 8 - 11 (4 bit)
WDWAIT : Interface Write Data Wait Delay.
bits : 16 - 21 (6 bit)
Interface Read Control States
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSRAS : Chip Select Read Address Setup State.
bits : 0 - 0 (1 bit)
Enumeration:
0 : LOW
Set chip select (CSx) to low during the read address setup state.
1 : HIGH
Set chip select (CSx) to high during the read address setup state.
End of enumeration elements list.
CSRAH : Chip Select Read Address Hold State.
bits : 1 - 1 (1 bit)
Enumeration:
0 : LOW
Set chip select (CSx) to low during the read address hold state.
1 : HIGH
Set chip select (CSx) to high during the read address hold state.
End of enumeration elements list.
CSRDW : Chip Select Read Data Wait State.
bits : 2 - 2 (1 bit)
Enumeration:
0 : LOW
Set chip select (CSx) to low during the read data wait state.
1 : HIGH
Set chip select (CSx) to high during the read data wait state.
End of enumeration elements list.
CSRDH : Chip Select Read Data Hold State.
bits : 3 - 3 (1 bit)
Enumeration:
0 : LOW
Set chip select (CSx) to low during the read data hold state.
1 : HIGH
Set chip select (CSx) to high during the read data hold state.
End of enumeration elements list.
OERAS : Output Enable Read Address Setup State.
bits : 4 - 4 (1 bit)
Enumeration:
0 : LOW
Set output enable (/OE) to low during the read address setup state.
1 : HIGH
Set output enable (/OE) to high during the read address setup state.
End of enumeration elements list.
OERAH : Output Enable Read Address Hold State.
bits : 5 - 5 (1 bit)
Enumeration:
0 : LOW
Set output enable (/OE) to low during the read address hold state.
1 : HIGH
Set output enable (/OE) to high during the read address hold state.
End of enumeration elements list.
OERDW : Output Enable Read Data Wait State.
bits : 6 - 6 (1 bit)
Enumeration:
0 : LOW
Set output enable (/OE) to low during the read data wait state.
1 : HIGH
Set output enable (/OE) to high during the read data wait state.
End of enumeration elements list.
OERDH : Output Enable Read Data Hold State.
bits : 7 - 7 (1 bit)
Enumeration:
0 : LOW
Set output enable (/OE) to low during the read data hold state.
1 : HIGH
Set output enable (/OE) to high during the read data hold state.
End of enumeration elements list.
WRRAS : Write Signal Read Address Setup State.
bits : 8 - 8 (1 bit)
Enumeration:
0 : LOW
Set write signal (/WR) to low during the read address setup state.
1 : HIGH
Set write signal (/WR) to high during the read address setup state.
End of enumeration elements list.
WRRAH : Write Signal Read Address Hold State.
bits : 9 - 9 (1 bit)
Enumeration:
0 : LOW
Set write signal (/WR) to low during the read address hold state.
1 : HIGH
Set write signal (/WR) to high during the read address hold state.
End of enumeration elements list.
WRRDW : Write Signal Read Data Wait State.
bits : 10 - 10 (1 bit)
Enumeration:
0 : LOW
Set write signal (/WR) to low during the read data wait state.
1 : HIGH
Set write signal (/WR) to high during the read data wait state.
End of enumeration elements list.
WRRDH : Write Signal Read Data Hold State.
bits : 11 - 11 (1 bit)
Enumeration:
0 : LOW
Set write signal (/WR) to low during the read data hold state.
1 : HIGH
Set write signal (/WR) to high during the read data hold state.
End of enumeration elements list.
ALERAS : Address Latch Enable Read Address Setup State.
bits : 12 - 12 (1 bit)
Enumeration:
0 : LOW
Set address latch enable (ALEm) to low during the read address setup state.
1 : HIGH
Set address latch enable (ALEm) to high during the read address setup state.
End of enumeration elements list.
ALERAH : Address Latch Enable Read Address Hold State.
bits : 13 - 13 (1 bit)
Enumeration:
0 : LOW
Set address latch enable (ALEm) to low during the read address hold state.
1 : HIGH
Set address latch enable (ALEm) to high during the read address hold state.
End of enumeration elements list.
ALERDW : Address Latch Enable Read Data Wait State.
bits : 14 - 14 (1 bit)
Enumeration:
0 : LOW
Set address latch enable (ALEm) to low during the read data wait state.
1 : HIGH
Set address latch enable (ALEm) to high during the read data wait state.
End of enumeration elements list.
ALERDH : Address Latch Enable Read Data Hold State.
bits : 15 - 15 (1 bit)
Enumeration:
0 : LOW
Set address latch enable (ALEm) to low during the read data hold state.
1 : HIGH
Set address latch enable (ALEm) to high during the read data hold state.
End of enumeration elements list.
Interface Write Control States
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSWAS : Chip Select Write Address Setup State.
bits : 0 - 0 (1 bit)
Enumeration:
0 : LOW
Set chip select (CSx) to low during the write address setup state.
1 : HIGH
Set chip select (CSx) to high during the write address setup state.
End of enumeration elements list.
CSWAH : Chip Select Write Address Hold State.
bits : 1 - 1 (1 bit)
Enumeration:
0 : LOW
Set chip select (CSx) to low during the write address hold state.
1 : HIGH
Set chip select (CSx) to high during the write address hold state.
End of enumeration elements list.
CSWDW : Chip Select Write Data Wait State.
bits : 2 - 2 (1 bit)
Enumeration:
0 : LOW
Set chip select (CSx) to low during the write data wait state.
1 : HIGH
Set chip select (CSx) to high during the write data wait state.
End of enumeration elements list.
CSWDH : Chip Select Write Data Hold State.
bits : 3 - 3 (1 bit)
Enumeration:
0 : LOW
Set chip select (CSx) to low during the write data hold state.
1 : HIGH
Set chip select (CSx) to high during the write data hold state.
End of enumeration elements list.
OEWAS : Output Enable Write Address Setup State.
bits : 4 - 4 (1 bit)
Enumeration:
0 : LOW
Set output enable (/OE) to low during the write address setup state.
1 : HIGH
Set output enable (/OE) to high during the write address setup state.
End of enumeration elements list.
OEWAH : Output Enable Write Address Hold State.
bits : 5 - 5 (1 bit)
Enumeration:
0 : LOW
Set output enable (/OE) to low during the write address hold state.
1 : HIGH
Set output enable (/OE) to high during the write address hold state.
End of enumeration elements list.
OEWDW : Output Enable Write Data Wait State.
bits : 6 - 6 (1 bit)
Enumeration:
0 : LOW
Set output enable (/OE) to low during the write data wait state.
1 : HIGH
Set output enable (/OE) to high during the write data wait state.
End of enumeration elements list.
OEWDH : Output Enable Write Data Hold State.
bits : 7 - 7 (1 bit)
Enumeration:
0 : LOW
Set output enable (/OE) to low during the write data hold state.
1 : HIGH
Set output enable (/OE) to high during the write data hold state.
End of enumeration elements list.
WRWAS : Write Signal Write Address Setup State.
bits : 8 - 8 (1 bit)
Enumeration:
0 : LOW
Set write signal (/WR) to low during the write address setup state.
1 : HIGH
Set write signal (/WR) to high during the write address setup state.
End of enumeration elements list.
WRWAH : Write Signal Write Address Hold State.
bits : 9 - 9 (1 bit)
Enumeration:
0 : LOW
Set write signal (/WR) to low during the write address hold state.
1 : HIGH
Set write signal (/WR) to high during the write address hold state.
End of enumeration elements list.
WRWDW : Write Signal Write Data Wait State.
bits : 10 - 10 (1 bit)
Enumeration:
0 : LOW
Set write signal (/WR) to low during the write data wait state.
1 : HIGH
Set write signal (/WR) to high during the write data wait state.
End of enumeration elements list.
WRWDH : Write Signal Write Data Hold State.
bits : 11 - 11 (1 bit)
Enumeration:
0 : LOW
Set write signal (/WR) to low during the write data hold state.
1 : HIGH
Set write signal (/WR) to high during the write data hold state.
End of enumeration elements list.
ALEWAS : Address Latch Enable Write Address Setup State.
bits : 12 - 12 (1 bit)
Enumeration:
0 : LOW
Set address latch enable (ALEm) to low during the write address setup state.
1 : HIGH
Set address latch enable (ALEm) to high during the write address setup state.
End of enumeration elements list.
ALEWAH : Address Latch Enable Write Address Hold State.
bits : 13 - 13 (1 bit)
Enumeration:
0 : LOW
Set address latch enable (ALEm) to low during the write address hold state.
1 : HIGH
Set address latch enable (ALEm) to high during the write address hold state.
End of enumeration elements list.
ALEWDW : Address Latch Enable Write Data Wait State.
bits : 14 - 14 (1 bit)
Enumeration:
0 : LOW
Set address latch enable (ALEm) to low during the write data wait state.
1 : HIGH
Set address latch enable (ALEm) to high during the write data wait state.
End of enumeration elements list.
ALEWDH : Address Latch Enable Write Data Hold State.
bits : 15 - 15 (1 bit)
Enumeration:
0 : LOW
Set address latch enable (ALEm) to low during the write data hold state.
1 : HIGH
Set address latch enable (ALEm) to high during the write data hold state.
End of enumeration elements list.
Module Status
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSTS : EMIF OFF Status.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : ON
The EMIF bus is active.
1 : OFF
The EMIF is in the off bus state.
End of enumeration elements list.
IDLESTS : EMIF IDLE Status.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : NOT_IDLE
The EMIF has not been idle for four cycles.
1 : IDLE
The EMIF has been idle for four four cycles.
End of enumeration elements list.
Interface Configuration
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSWIDTH : Interface Bus Data Width.
bits : 0 - 0 (1 bit)
Enumeration:
0 : 8BIT
The data bus is 8-bits wide.
1 : 16BIT
The data bus is 16-bits wide.
End of enumeration elements list.
MUXMD : Interface Mux Mode.
bits : 2 - 2 (1 bit)
Enumeration:
0 : NONMUXED
The interface operates in non-multiplexed mode.
1 : MUXED
The interface operates in multiplexed mode.
End of enumeration elements list.
ASEN : Interface Automatic Address Shift Enable.
bits : 3 - 3 (1 bit)
Enumeration:
0 : DISABLED
The address is not automatically shifted.
1 : ENABLED
The address is automatically shifted.
End of enumeration elements list.
ROEN : Interface Read Only Enable.
bits : 4 - 4 (1 bit)
Enumeration:
0 : DISABLED
The interface supports reads and writes.
1 : ENABLED
The interface supports only reads.
End of enumeration elements list.
WDHINH : Write Data Hold State Inhibit.
bits : 8 - 8 (1 bit)
Enumeration:
0 : INACTIVE
Enable the write data hold state.
1 : ACTIVE
Inhibit the write data hold state.
End of enumeration elements list.
DELAYOE : Output Enable Delay.
bits : 12 - 12 (1 bit)
Enumeration:
0 : DISABLED
The output enable signal (/OE) is not delayed.
1 : ENABLED
The output enable signal (/OE) is delayed.
End of enumeration elements list.
KLREN : Keep Last Read Enable.
bits : 16 - 16 (1 bit)
Enumeration:
0 : DISABLED
The bus is driven to the idle state between active requests.
1 : ENABLED
The bus drives the last value read on the interface between active requests.
End of enumeration elements list.
Interface Read Timing
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RASET : Interface Read Address Setup Delay .
bits : 0 - 3 (4 bit)
RAHOLD : Interface Read Address Hold Delay.
bits : 4 - 7 (4 bit)
RDHOLD : Interface Read Data Hold Delay.
bits : 8 - 11 (4 bit)
RDWAIT : Interface Read Data Wait Delay.
bits : 16 - 21 (6 bit)
Interface Write Timing
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WASET : Interface Write Address Setup Delay .
bits : 0 - 3 (4 bit)
WAHOLD : Interface Write Address Hold Delay.
bits : 4 - 7 (4 bit)
WDHOLD : Interface Write Data Hold Delay.
bits : 8 - 11 (4 bit)
WDWAIT : Interface Write Data Wait Delay.
bits : 16 - 21 (6 bit)
Interface Read Control States
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSRAS : Chip Select Read Address Setup State.
bits : 0 - 0 (1 bit)
Enumeration:
0 : LOW
Set chip select (CSx) to low during the read address setup state.
1 : HIGH
Set chip select (CSx) to high during the read address setup state.
End of enumeration elements list.
CSRAH : Chip Select Read Address Hold State.
bits : 1 - 1 (1 bit)
Enumeration:
0 : LOW
Set chip select (CSx) to low during the read address hold state.
1 : HIGH
Set chip select (CSx) to high during the read address hold state.
End of enumeration elements list.
CSRDW : Chip Select Read Data Wait State.
bits : 2 - 2 (1 bit)
Enumeration:
0 : LOW
Set chip select (CSx) to low during the read data wait state.
1 : HIGH
Set chip select (CSx) to high during the read data wait state.
End of enumeration elements list.
CSRDH : Chip Select Read Data Hold State.
bits : 3 - 3 (1 bit)
Enumeration:
0 : LOW
Set chip select (CSx) to low during the read data hold state.
1 : HIGH
Set chip select (CSx) to high during the read data hold state.
End of enumeration elements list.
OERAS : Output Enable Read Address Setup State.
bits : 4 - 4 (1 bit)
Enumeration:
0 : LOW
Set output enable (/OE) to low during the read address setup state.
1 : HIGH
Set output enable (/OE) to high during the read address setup state.
End of enumeration elements list.
OERAH : Output Enable Read Address Hold State.
bits : 5 - 5 (1 bit)
Enumeration:
0 : LOW
Set output enable (/OE) to low during the read address hold state.
1 : HIGH
Set output enable (/OE) to high during the read address hold state.
End of enumeration elements list.
OERDW : Output Enable Read Data Wait State.
bits : 6 - 6 (1 bit)
Enumeration:
0 : LOW
Set output enable (/OE) to low during the read data wait state.
1 : HIGH
Set output enable (/OE) to high during the read data wait state.
End of enumeration elements list.
OERDH : Output Enable Read Data Hold State.
bits : 7 - 7 (1 bit)
Enumeration:
0 : LOW
Set output enable (/OE) to low during the read data hold state.
1 : HIGH
Set output enable (/OE) to high during the read data hold state.
End of enumeration elements list.
WRRAS : Write Signal Read Address Setup State.
bits : 8 - 8 (1 bit)
Enumeration:
0 : LOW
Set write signal (/WR) to low during the read address setup state.
1 : HIGH
Set write signal (/WR) to high during the read address setup state.
End of enumeration elements list.
WRRAH : Write Signal Read Address Hold State.
bits : 9 - 9 (1 bit)
Enumeration:
0 : LOW
Set write signal (/WR) to low during the read address hold state.
1 : HIGH
Set write signal (/WR) to high during the read address hold state.
End of enumeration elements list.
WRRDW : Write Signal Read Data Wait State.
bits : 10 - 10 (1 bit)
Enumeration:
0 : LOW
Set write signal (/WR) to low during the read data wait state.
1 : HIGH
Set write signal (/WR) to high during the read data wait state.
End of enumeration elements list.
WRRDH : Write Signal Read Data Hold State.
bits : 11 - 11 (1 bit)
Enumeration:
0 : LOW
Set write signal (/WR) to low during the read data hold state.
1 : HIGH
Set write signal (/WR) to high during the read data hold state.
End of enumeration elements list.
ALERAS : Address Latch Enable Read Address Setup State.
bits : 12 - 12 (1 bit)
Enumeration:
0 : LOW
Set address latch enable (ALEm) to low during the read address setup state.
1 : HIGH
Set address latch enable (ALEm) to high during the read address setup state.
End of enumeration elements list.
ALERAH : Address Latch Enable Read Address Hold State.
bits : 13 - 13 (1 bit)
Enumeration:
0 : LOW
Set address latch enable (ALEm) to low during the read address hold state.
1 : HIGH
Set address latch enable (ALEm) to high during the read address hold state.
End of enumeration elements list.
ALERDW : Address Latch Enable Read Data Wait State.
bits : 14 - 14 (1 bit)
Enumeration:
0 : LOW
Set address latch enable (ALEm) to low during the read data wait state.
1 : HIGH
Set address latch enable (ALEm) to high during the read data wait state.
End of enumeration elements list.
ALERDH : Address Latch Enable Read Data Hold State.
bits : 15 - 15 (1 bit)
Enumeration:
0 : LOW
Set address latch enable (ALEm) to low during the read data hold state.
1 : HIGH
Set address latch enable (ALEm) to high during the read data hold state.
End of enumeration elements list.
Interface Write Control States
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSWAS : Chip Select Write Address Setup State.
bits : 0 - 0 (1 bit)
Enumeration:
0 : LOW
Set chip select (CSx) to low during the write address setup state.
1 : HIGH
Set chip select (CSx) to high during the write address setup state.
End of enumeration elements list.
CSWAH : Chip Select Write Address Hold State.
bits : 1 - 1 (1 bit)
Enumeration:
0 : LOW
Set chip select (CSx) to low during the write address hold state.
1 : HIGH
Set chip select (CSx) to high during the write address hold state.
End of enumeration elements list.
CSWDW : Chip Select Write Data Wait State.
bits : 2 - 2 (1 bit)
Enumeration:
0 : LOW
Set chip select (CSx) to low during the write data wait state.
1 : HIGH
Set chip select (CSx) to high during the write data wait state.
End of enumeration elements list.
CSWDH : Chip Select Write Data Hold State.
bits : 3 - 3 (1 bit)
Enumeration:
0 : LOW
Set chip select (CSx) to low during the write data hold state.
1 : HIGH
Set chip select (CSx) to high during the write data hold state.
End of enumeration elements list.
OEWAS : Output Enable Write Address Setup State.
bits : 4 - 4 (1 bit)
Enumeration:
0 : LOW
Set output enable (/OE) to low during the write address setup state.
1 : HIGH
Set output enable (/OE) to high during the write address setup state.
End of enumeration elements list.
OEWAH : Output Enable Write Address Hold State.
bits : 5 - 5 (1 bit)
Enumeration:
0 : LOW
Set output enable (/OE) to low during the write address hold state.
1 : HIGH
Set output enable (/OE) to high during the write address hold state.
End of enumeration elements list.
OEWDW : Output Enable Write Data Wait State.
bits : 6 - 6 (1 bit)
Enumeration:
0 : LOW
Set output enable (/OE) to low during the write data wait state.
1 : HIGH
Set output enable (/OE) to high during the write data wait state.
End of enumeration elements list.
OEWDH : Output Enable Write Data Hold State.
bits : 7 - 7 (1 bit)
Enumeration:
0 : LOW
Set output enable (/OE) to low during the write data hold state.
1 : HIGH
Set output enable (/OE) to high during the write data hold state.
End of enumeration elements list.
WRWAS : Write Signal Write Address Setup State.
bits : 8 - 8 (1 bit)
Enumeration:
0 : LOW
Set write signal (/WR) to low during the write address setup state.
1 : HIGH
Set write signal (/WR) to high during the write address setup state.
End of enumeration elements list.
WRWAH : Write Signal Write Address Hold State.
bits : 9 - 9 (1 bit)
Enumeration:
0 : LOW
Set write signal (/WR) to low during the write address hold state.
1 : HIGH
Set write signal (/WR) to high during the write address hold state.
End of enumeration elements list.
WRWDW : Write Signal Write Data Wait State.
bits : 10 - 10 (1 bit)
Enumeration:
0 : LOW
Set write signal (/WR) to low during the write data wait state.
1 : HIGH
Set write signal (/WR) to high during the write data wait state.
End of enumeration elements list.
WRWDH : Write Signal Write Data Hold State.
bits : 11 - 11 (1 bit)
Enumeration:
0 : LOW
Set write signal (/WR) to low during the write data hold state.
1 : HIGH
Set write signal (/WR) to high during the write data hold state.
End of enumeration elements list.
ALEWAS : Address Latch Enable Write Address Setup State.
bits : 12 - 12 (1 bit)
Enumeration:
0 : LOW
Set address latch enable (ALEm) to low during the write address setup state.
1 : HIGH
Set address latch enable (ALEm) to high during the write address setup state.
End of enumeration elements list.
ALEWAH : Address Latch Enable Write Address Hold State.
bits : 13 - 13 (1 bit)
Enumeration:
0 : LOW
Set address latch enable (ALEm) to low during the write address hold state.
1 : HIGH
Set address latch enable (ALEm) to high during the write address hold state.
End of enumeration elements list.
ALEWDW : Address Latch Enable Write Data Wait State.
bits : 14 - 14 (1 bit)
Enumeration:
0 : LOW
Set address latch enable (ALEm) to low during the write data wait state.
1 : HIGH
Set address latch enable (ALEm) to high during the write data wait state.
End of enumeration elements list.
ALEWDH : Address Latch Enable Write Data Hold State.
bits : 15 - 15 (1 bit)
Enumeration:
0 : LOW
Set address latch enable (ALEm) to low during the write data hold state.
1 : HIGH
Set address latch enable (ALEm) to high during the write data hold state.
End of enumeration elements list.
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