Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected
Channel Capture/Compare Mode
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COSEL : Channel Output Function Select.
bits : 0 - 1 (2 bit)
Enumeration:
0 : TOGGLE_OUTPUT
Toggle the channel output at the next capture/compare, overflow, or intermediate event.
1 : SET_OUTPUT
Set the channel output at the next capture/compare, overflow, or intermediate event.
2 : CLEAR_OUTPUT
Clear the output at the next capture/compare, overflow, or intermediate event.
3 : NO_CHANGE
Capture/Compare, overflow, or intermediate events do not control the output state.
End of enumeration elements list.
PWMMD : PWM N-Bit Mode.
bits : 2 - 5 (4 bit)
DIFGEN : Differential Signal Generator Enable.
bits : 6 - 6 (1 bit)
Enumeration:
0 : DISABLED
Disable the differential signal generator. The channel will output a single non-differential output.
1 : ENABLED
Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH).
End of enumeration elements list.
CMD : Channel Operating Mode.
bits : 8 - 10 (3 bit)
Enumeration:
0 : EDGE_PWM
Configure the channel for edge-aligned PWM mode.
1 : CENTER_ALIGNED_PWM
Configure the channel for center-aligned PWM mode.
2 : HF_SQUARE_WAVE
Configure the channel for high-frequency/square-wave mode.
3 : TIMER_CAPTURE
Configure the channel for timer/capture mode.
4 : N_BIT_PWM
Configure the channel for n-bit edge-aligned PWM mode.
End of enumeration elements list.
Channel Capture/Compare Control
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUTST : Channel Output State.
bits : 0 - 0 (1 bit)
Enumeration:
0 : LOW
The channel output state is low.
1 : HIGH
The channel output state is high.
End of enumeration elements list.
CPCAPEN : Positive Edge Input Capture Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable positive-edge input capture.
1 : ENABLED
Enable positive-edge input capture.
End of enumeration elements list.
CNCAPEN : Negative Edge Input Capture Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
Disable negative-edge input capture.
1 : ENABLED
Enable negative-edge input capture.
End of enumeration elements list.
CUPDCF : Channel Register Update Complete Flag.
bits : 3 - 3 (1 bit)
Enumeration:
0 : NOT_SET
A EPCA channel register update completed or is not pending.
1 : SET
A EPCA channel register update has not completed and is still pending.
End of enumeration elements list.
YPHST : Differential Y Phase State.
bits : 5 - 5 (1 bit)
Enumeration:
0 : LOW
Set the Y Phase output state to low.
1 : HIGH
Set the Y Phase output state to high.
End of enumeration elements list.
ACTIVEPH : Active Channel Select.
bits : 6 - 6 (1 bit)
Enumeration:
0 : YACTIVE
The Y Phase is active and X Phase is inactive.
1 : XACTIVE
The X Phase is active and Y Phase is inactive.
End of enumeration elements list.
XPHST : Differential X Phase State.
bits : 7 - 7 (1 bit)
Enumeration:
0 : LOW
Set the X Phase output state to low.
1 : HIGH
Set the X Phase output state to high.
End of enumeration elements list.
CCIEN : Capture/Compare Interrupt Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : DISABLED
Disable the channel capture/compare interrupt.
1 : ENABLED
Enable the channel capture/compare interrupt.
End of enumeration elements list.
CCDEN : Capture/Compare DMA Request Enable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : DISABLED
Do not request DMA data when a channel capture/compare event occurs.
1 : ENABLED
Request DMA data when a channel capture/compare event occurs.
End of enumeration elements list.
CCSEN : Capture/Compare Synchronization Signal Enable.
bits : 10 - 10 (1 bit)
Enumeration:
0 : DISABLED
Do not send a synchronization signal when a channel capture/compare event occurs.
1 : ENABLED
Send a synchronization signal when a channel capture/compare event occurs.
End of enumeration elements list.
CIOVFIEN : Intermediate Overflow Interrupt Enable.
bits : 11 - 11 (1 bit)
Enumeration:
0 : DISABLED
Disable the channel intermediate overflow interrupt.
1 : ENABLED
Enable the channel intermediate overflow interrupt.
End of enumeration elements list.
CIOVFDEN : Intermediate Overflow DMA Request Enable.
bits : 12 - 12 (1 bit)
Enumeration:
0 : DISABLED
Do not request DMA data when a channel intermediate overflow event occurs.
1 : ENABLED
Request DMA data when a channel intermediate overflow event occurs.
End of enumeration elements list.
CIOVFSEN : Intermediate Overflow Synchronization Signal Enable.
bits : 13 - 13 (1 bit)
Enumeration:
0 : DISABLED
Do not send a synchronization signal when a channel intermediate overflow event occurs.
1 : ENABLED
Send a synchronization signal when a channel intermediate overflow occurs.
End of enumeration elements list.
Channel Capture/Compare Mode
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COSEL : Channel Output Function Select.
bits : 0 - 1 (2 bit)
Enumeration:
0 : TOGGLE_OUTPUT
Toggle the channel output at the next capture/compare, overflow, or intermediate event.
1 : SET_OUTPUT
Set the channel output at the next capture/compare, overflow, or intermediate event.
2 : CLEAR_OUTPUT
Clear the output at the next capture/compare, overflow, or intermediate event.
3 : NO_CHANGE
Capture/Compare, overflow, or intermediate events do not control the output state.
End of enumeration elements list.
PWMMD : PWM N-Bit Mode.
bits : 2 - 5 (4 bit)
DIFGEN : Differential Signal Generator Enable.
bits : 6 - 6 (1 bit)
Enumeration:
0 : DISABLED
Disable the differential signal generator. The channel will output a single non-differential output.
1 : ENABLED
Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH).
End of enumeration elements list.
CMD : Channel Operating Mode.
bits : 8 - 10 (3 bit)
Enumeration:
0 : EDGE_PWM
Configure the channel for edge-aligned PWM mode.
1 : CENTER_ALIGNED_PWM
Configure the channel for center-aligned PWM mode.
2 : HF_SQUARE_WAVE
Configure the channel for high-frequency/square-wave mode.
3 : TIMER_CAPTURE
Configure the channel for timer/capture mode.
4 : N_BIT_PWM
Configure the channel for n-bit edge-aligned PWM mode.
End of enumeration elements list.
Channel Capture/Compare Control
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUTST : Channel Output State.
bits : 0 - 0 (1 bit)
Enumeration:
0 : LOW
The channel output state is low.
1 : HIGH
The channel output state is high.
End of enumeration elements list.
CPCAPEN : Positive Edge Input Capture Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable positive-edge input capture.
1 : ENABLED
Enable positive-edge input capture.
End of enumeration elements list.
CNCAPEN : Negative Edge Input Capture Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
Disable negative-edge input capture.
1 : ENABLED
Enable negative-edge input capture.
End of enumeration elements list.
CUPDCF : Channel Register Update Complete Flag.
bits : 3 - 3 (1 bit)
Enumeration:
0 : NOT_SET
A EPCA channel register update completed or is not pending.
1 : SET
A EPCA channel register update has not completed and is still pending.
End of enumeration elements list.
YPHST : Differential Y Phase State.
bits : 5 - 5 (1 bit)
Enumeration:
0 : LOW
Set the Y Phase output state to low.
1 : HIGH
Set the Y Phase output state to high.
End of enumeration elements list.
ACTIVEPH : Active Channel Select.
bits : 6 - 6 (1 bit)
Enumeration:
0 : YACTIVE
The Y Phase is active and X Phase is inactive.
1 : XACTIVE
The X Phase is active and Y Phase is inactive.
End of enumeration elements list.
XPHST : Differential X Phase State.
bits : 7 - 7 (1 bit)
Enumeration:
0 : LOW
Set the X Phase output state to low.
1 : HIGH
Set the X Phase output state to high.
End of enumeration elements list.
CCIEN : Capture/Compare Interrupt Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : DISABLED
Disable the channel capture/compare interrupt.
1 : ENABLED
Enable the channel capture/compare interrupt.
End of enumeration elements list.
CCDEN : Capture/Compare DMA Request Enable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : DISABLED
Do not request DMA data when a channel capture/compare event occurs.
1 : ENABLED
Request DMA data when a channel capture/compare event occurs.
End of enumeration elements list.
CCSEN : Capture/Compare Synchronization Signal Enable.
bits : 10 - 10 (1 bit)
Enumeration:
0 : DISABLED
Do not send a synchronization signal when a channel capture/compare event occurs.
1 : ENABLED
Send a synchronization signal when a channel capture/compare event occurs.
End of enumeration elements list.
CIOVFIEN : Intermediate Overflow Interrupt Enable.
bits : 11 - 11 (1 bit)
Enumeration:
0 : DISABLED
Disable the channel intermediate overflow interrupt.
1 : ENABLED
Enable the channel intermediate overflow interrupt.
End of enumeration elements list.
CIOVFDEN : Intermediate Overflow DMA Request Enable.
bits : 12 - 12 (1 bit)
Enumeration:
0 : DISABLED
Do not request DMA data when a channel intermediate overflow event occurs.
1 : ENABLED
Request DMA data when a channel intermediate overflow event occurs.
End of enumeration elements list.
CIOVFSEN : Intermediate Overflow Synchronization Signal Enable.
bits : 13 - 13 (1 bit)
Enumeration:
0 : DISABLED
Do not send a synchronization signal when a channel intermediate overflow event occurs.
1 : ENABLED
Send a synchronization signal when a channel intermediate overflow occurs.
End of enumeration elements list.
Channel Compare Value
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCAPV : Channel Compare Value.
bits : 0 - 17 (18 bit)
Channel Compare Update Value
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCAPVUPD : Channel Compare Update Value.
bits : 0 - 17 (18 bit)
Channel Capture/Compare Mode
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COSEL : Channel Output Function Select.
bits : 0 - 1 (2 bit)
Enumeration:
0 : TOGGLE_OUTPUT
Toggle the channel output at the next capture/compare, overflow, or intermediate event.
1 : SET_OUTPUT
Set the channel output at the next capture/compare, overflow, or intermediate event.
2 : CLEAR_OUTPUT
Clear the output at the next capture/compare, overflow, or intermediate event.
3 : NO_CHANGE
Capture/Compare, overflow, or intermediate events do not control the output state.
End of enumeration elements list.
PWMMD : PWM N-Bit Mode.
bits : 2 - 5 (4 bit)
DIFGEN : Differential Signal Generator Enable.
bits : 6 - 6 (1 bit)
Enumeration:
0 : DISABLED
Disable the differential signal generator. The channel will output a single non-differential output.
1 : ENABLED
Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH).
End of enumeration elements list.
CMD : Channel Operating Mode.
bits : 8 - 10 (3 bit)
Enumeration:
0 : EDGE_PWM
Configure the channel for edge-aligned PWM mode.
1 : CENTER_ALIGNED_PWM
Configure the channel for center-aligned PWM mode.
2 : HF_SQUARE_WAVE
Configure the channel for high-frequency/square-wave mode.
3 : TIMER_CAPTURE
Configure the channel for timer/capture mode.
4 : N_BIT_PWM
Configure the channel for n-bit edge-aligned PWM mode.
End of enumeration elements list.
Channel Capture/Compare Control
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUTST : Channel Output State.
bits : 0 - 0 (1 bit)
Enumeration:
0 : LOW
The channel output state is low.
1 : HIGH
The channel output state is high.
End of enumeration elements list.
CPCAPEN : Positive Edge Input Capture Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable positive-edge input capture.
1 : ENABLED
Enable positive-edge input capture.
End of enumeration elements list.
CNCAPEN : Negative Edge Input Capture Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
Disable negative-edge input capture.
1 : ENABLED
Enable negative-edge input capture.
End of enumeration elements list.
CUPDCF : Channel Register Update Complete Flag.
bits : 3 - 3 (1 bit)
Enumeration:
0 : NOT_SET
A EPCA channel register update completed or is not pending.
1 : SET
A EPCA channel register update has not completed and is still pending.
End of enumeration elements list.
YPHST : Differential Y Phase State.
bits : 5 - 5 (1 bit)
Enumeration:
0 : LOW
Set the Y Phase output state to low.
1 : HIGH
Set the Y Phase output state to high.
End of enumeration elements list.
ACTIVEPH : Active Channel Select.
bits : 6 - 6 (1 bit)
Enumeration:
0 : YACTIVE
The Y Phase is active and X Phase is inactive.
1 : XACTIVE
The X Phase is active and Y Phase is inactive.
End of enumeration elements list.
XPHST : Differential X Phase State.
bits : 7 - 7 (1 bit)
Enumeration:
0 : LOW
Set the X Phase output state to low.
1 : HIGH
Set the X Phase output state to high.
End of enumeration elements list.
CCIEN : Capture/Compare Interrupt Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : DISABLED
Disable the channel capture/compare interrupt.
1 : ENABLED
Enable the channel capture/compare interrupt.
End of enumeration elements list.
CCDEN : Capture/Compare DMA Request Enable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : DISABLED
Do not request DMA data when a channel capture/compare event occurs.
1 : ENABLED
Request DMA data when a channel capture/compare event occurs.
End of enumeration elements list.
CCSEN : Capture/Compare Synchronization Signal Enable.
bits : 10 - 10 (1 bit)
Enumeration:
0 : DISABLED
Do not send a synchronization signal when a channel capture/compare event occurs.
1 : ENABLED
Send a synchronization signal when a channel capture/compare event occurs.
End of enumeration elements list.
CIOVFIEN : Intermediate Overflow Interrupt Enable.
bits : 11 - 11 (1 bit)
Enumeration:
0 : DISABLED
Disable the channel intermediate overflow interrupt.
1 : ENABLED
Enable the channel intermediate overflow interrupt.
End of enumeration elements list.
CIOVFDEN : Intermediate Overflow DMA Request Enable.
bits : 12 - 12 (1 bit)
Enumeration:
0 : DISABLED
Do not request DMA data when a channel intermediate overflow event occurs.
1 : ENABLED
Request DMA data when a channel intermediate overflow event occurs.
End of enumeration elements list.
CIOVFSEN : Intermediate Overflow Synchronization Signal Enable.
bits : 13 - 13 (1 bit)
Enumeration:
0 : DISABLED
Do not send a synchronization signal when a channel intermediate overflow event occurs.
1 : ENABLED
Send a synchronization signal when a channel intermediate overflow occurs.
End of enumeration elements list.
Channel Compare Value
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCAPV : Channel Compare Value.
bits : 0 - 17 (18 bit)
Channel Compare Update Value
address_offset : 0x170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCAPVUPD : Channel Compare Update Value.
bits : 0 - 17 (18 bit)
Module Operating Mode
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIV : Input Clock Divider.
bits : 0 - 9 (10 bit)
CLKSEL : Input Clock (F
bits : 10 - 12 (3 bit)
Enumeration:
0 : APB
Set the APB as the input clock (FCLKIN).
1 : TIMER0
Set Timer 0 low overflows divided by 2 as the input clock (FCLKIN).
2 : HL_ECI
Set high-to-low transitions on ECI divided by 2 as the input clock (FCLKIN).
3 : EXTOSCN
Set the external oscillator module output (EXTOSCn) divided by 2 as the input clock (FCLKIN).
4 : ECI
Set ECI transitions divided by 2 as the input clock (FCLKIN).
End of enumeration elements list.
HDOSEL : High Drive Port Bank Output Select.
bits : 14 - 15 (2 bit)
Enumeration:
0 : THREE_DIFF
Select three differential outputs from Channels 3, 4, and 5 for the High Drive pins.
1 : TWO_DIFF
Select the differential outputs from Channels 4 and 5 and non-differential outputs from Channels 2 and 3 for the High Drive pins.
2 : ONE_DIFF
Select the differential output from Channel 5 and non-differential outputs from Channels 1-4 for the High Drive pins.
3 : NO_DIFF
Select the non-differential channel outputs (Channels 0-5) for the High Drive pins.
End of enumeration elements list.
DEND : DMA Write End Index.
bits : 16 - 18 (3 bit)
Enumeration:
0 : LIMIT
Set the last register in a DMA write transfer to LIMITUPD.
1 : CH0
Set the last register in a DMA write transfer to Channel 0 CCAPVUPD.
2 : CH1
Set the last register in a DMA write transfer to Channel 1 CCAPVUPD.
3 : CH2
Set the last register in a DMA write transfer to Channel 2 CCAPVUPD.
4 : CH3
Set the last register in a DMA write transfer to Channel 3 CCAPVUPD.
5 : CH4
Set the last register in a DMA write transfer to Channel 4 CCAPVUPD.
6 : CH5
Set the last register in a DMA write transfer to Channel 5 CCAPVUPD.
7 : EMPTY
Empty slot.
End of enumeration elements list.
DPTR : DMA Write Transfer Pointer.
bits : 19 - 21 (3 bit)
Enumeration:
0 : LIMIT
The DMA channel will write to LIMITUPD next.
1 : CH0
The DMA channel will write to Channel 0 CCAPVUPD next.
2 : CH1
The DMA channel will write to Channel 1 CCAPVUPD next.
3 : CH2
The DMA channel will write to Channel 2 CCAPVUPD next.
4 : CH3
The DMA channel will write to Channel 3 CCAPVUPD next.
5 : CH4
The DMA channel will write to Channel 4 CCAPVUPD next.
6 : CH5
The DMA channel will write to Channel 5 CCAPVUPD next.
7 : EMPTY
Empty slot.
End of enumeration elements list.
DSTART : DMA Target Start Index.
bits : 22 - 24 (3 bit)
Enumeration:
0 : LIMIT
Set the first register in a DMA write transfer to LIMITUPD.
1 : CH0
Set the first register in a DMA write transfer to Channel 0 CCAPVUPD.
2 : CH1
Set the first register in a DMA write transfer to Channel 1 CCAPVUPD.
3 : CH2
Set the first register in a DMA write transfer to Channel 2 CCAPVUPD.
4 : CH3
Set the first register in a DMA write transfer to Channel 3 CCAPVUPD.
5 : CH4
Set the first register in a DMA write transfer to Channel 4 CCAPVUPD.
6 : CH5
Set the first register in a DMA write transfer to Channel 5 CCAPVUPD.
7 : EMPTY
Empty slot.
End of enumeration elements list.
DBUSYF : DMA Busy Flag.
bits : 25 - 25 (1 bit)
Enumeration:
0 : IDLE
The DMA channel is not servicing an EPCA control transfer.
1 : BUSY
The DMA channel is busy servicing an EPCA control transfer.
End of enumeration elements list.
STDOSEL : Standard Port Bank Output Select.
bits : 27 - 28 (2 bit)
Enumeration:
0 : NO_DIFF
Select the non-differential channel outputs (Channels 0-5) for the standard PB pins.
1 : ONE_DIFF
Select the differential output from Channel 2 and non-differential outputs from Channels 0, 1, 3, and 4 for the standard PB pins.
2 : TWO_DIFF
Select the differential outputs from Channels 1 and 2 and non-differential outputs from Channels 0 and 3 for the standard PB pins.
3 : THREE_DIFF
Select three differential outputs from Channels 0, 1, and 2 for the standard PB pins.
End of enumeration elements list.
Module Control
address_offset : 0x190 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVFIEN : EPCA Counter Overflow/Limit Interrupt Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
Disable the EPCA counter overflow/limit event interrupt.
1 : ENABLED
Enable the EPCA counter overflow/limit event interrupt.
End of enumeration elements list.
OVFDEN : EPCA Counter Overflow/Limit DMA Request Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Do not request DMA data when a EPCA counter overflow/limit event occurs.
1 : ENABLED
Request DMA data when a EPCA counter overflow/limit event occurs.
End of enumeration elements list.
OVFSEN : EPCA Counter Overflow/Limit Synchronization Signal Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
Do not send a synchronization signal when a EPCA counter overflow/limit event occurs.
1 : ENABLED
Send a synchronization signal when a EPCA counter overflow/limit event occurs.
End of enumeration elements list.
HALTIEN : EPCA Halt Input Interrupt Enable.
bits : 3 - 3 (1 bit)
Enumeration:
0 : DISABLED
Do not generate an interrupt if the EPCA halt input is high.
1 : ENABLED
Generate an interrupt if the EPCA halt input is high.
End of enumeration elements list.
NOUPD : Internal Register Update Inhibit.
bits : 4 - 4 (1 bit)
Enumeration:
0 : INACTIVE
The EPCA registers will automatically load any new update values after an overflow/limit event occurs.
1 : ACTIVE
The EPCA registers will not load any new update values after an overflow/limit event occurs.
End of enumeration elements list.
IDLEBEN : Idle Bypass Enable.
bits : 5 - 5 (1 bit)
Enumeration:
0 : DISABLED
The EPCA module will stop running when the core halts (idle).
1 : ENABLED
The EPCA module will continue normal operation when the core halts (idle).
End of enumeration elements list.
DBGMD : EPCA Debug Mode.
bits : 6 - 6 (1 bit)
Enumeration:
0 : HALT
A debug breakpoint will stop the EPCA counter/timer.
1 : RUN
The EPCA will continue to operate while the core is halted in debug mode.
End of enumeration elements list.
HALTEN : Halt Input Enable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : DISABLED
The Halt input (PB_HDKill) does not affect the EPCA counter/timer.
1 : ENABLED
An assertion of the Halt input (PB_HDKill) will stop the EPCA counter/timer.
End of enumeration elements list.
STSEL : Synchronous Input Trigger Select.
bits : 11 - 12 (2 bit)
Enumeration:
0 : EPCANT0
Select input trigger 0, EPCAnT0 (Comparator 0 Output).
1 : EPCANT1
Select input trigger 1, EPCAnT1 (Comparator 1 Output).
2 : EPCANT2
Select input trigger 2, EPCAnT2 (Timer 0 High Overflow ).
3 : EPCANT3
Select input trigger 3, EPCAnT3 (Timer 1 High Overflow).
End of enumeration elements list.
STESEL : Synchronous Input Trigger Edge Select.
bits : 13 - 13 (1 bit)
Enumeration:
0 : FALLING
A high-to-low transition (falling edge) on EPCAnTx will start the counter/timer.
1 : RISING
A low-to-high transition (rising edge) on EPCAnTx will start the counter/timer.
End of enumeration elements list.
STEN : Synchronous Input Trigger Enable.
bits : 14 - 14 (1 bit)
Enumeration:
0 : DISABLED
Disable the input trigger (EPCAnTx). The EPCA counter/timer will continue to run if the RUN bit is set regardless of the value on the input trigger.
1 : ENABLED
Enable the input trigger (EPCAnTx). If RUN is set to 1, the EPCA counter/timer will start running when the selected input trigger (STSEL) meets the criteria set by STESEL. It will not stop running if the criteria is no longer met.
End of enumeration elements list.
DIVST : Clock Divider Output State.
bits : 21 - 21 (1 bit)
Enumeration:
0 : OUTPUT_HIGH
The clock divider is currently in the first half-cycle.
1 : OUTPUT_LOW
The clock divider is currently in the second half-cycle.
End of enumeration elements list.
DIV : Current Clock Divider Count.
bits : 22 - 31 (10 bit)
Module Status
address_offset : 0x1A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C0CCI : Channel 0 Capture/Compare Interrupt Flag.
bits : 0 - 0 (1 bit)
Enumeration:
0 : NOT_SET
A Channel 0 match or capture event did not occur.
1 : SET
A Channel 0 match or capture event occurred.
End of enumeration elements list.
C1CCI : Channel 1 Capture/Compare Interrupt Flag.
bits : 1 - 1 (1 bit)
Enumeration:
0 : NOT_SET
A Channel 1 match or capture event did not occur.
1 : SET
A Channel 1 match or capture event occurred.
End of enumeration elements list.
C2CCI : Channel 2 Capture/Compare Interrupt Flag.
bits : 2 - 2 (1 bit)
Enumeration:
0 : NOT_SET
A Channel 2 match or capture event did not occur.
1 : SET
A Channel 2 match or capture event occurred.
End of enumeration elements list.
C3CCI : Channel 3 Capture/Compare Interrupt Flag.
bits : 3 - 3 (1 bit)
Enumeration:
0 : NOT_SET
A Channel 3 match or capture event did not occur.
1 : SET
A Channel 3 match or capture event occurred.
End of enumeration elements list.
C4CCI : Channel 4 Capture/Compare Interrupt Flag.
bits : 4 - 4 (1 bit)
Enumeration:
0 : NOT_SET
A Channel 4 match or capture event did not occur.
1 : SET
A Channel 4 match or capture event occurred.
End of enumeration elements list.
C5CCI : Channel 5 Capture/Compare Interrupt Flag.
bits : 5 - 5 (1 bit)
Enumeration:
0 : NOT_SET
A Channel 5 match or capture event did not occur.
1 : SET
A Channel 5 match or capture event occurred.
End of enumeration elements list.
RUN : Counter/Timer Run.
bits : 6 - 6 (1 bit)
Enumeration:
0 : STOP
Stop the EPCA Counter/Timer.
1 : START
Start the EPCA Counter/Timer.
End of enumeration elements list.
OVFI : Counter/Timer Overflow/Limit Interrupt Flag.
bits : 7 - 7 (1 bit)
Enumeration:
0 : NOT_SET
An EPCA Counter/Timer overflow/limit event did not occur.
1 : SET
An EPCA Counter/Timer overflow/limit event occurred.
End of enumeration elements list.
UPDCF : Register Update Complete Flag.
bits : 8 - 8 (1 bit)
Enumeration:
0 : EMPTY
An EPCA register update completed or is not pending.
1 : FULL
An EPCA register update has not completed and is still pending.
End of enumeration elements list.
HALTI : Halt Input Interrupt Flag.
bits : 9 - 9 (1 bit)
Enumeration:
0 : NOT_SET
The Halt input (PB_HDKill) was not asserted.
1 : SET
The Halt input (PB_HDKill) was asserted.
End of enumeration elements list.
C0IOVFI : Channel 0 Intermediate Overflow Interrupt Flag.
bits : 10 - 10 (1 bit)
Enumeration:
0 : NOT_SET
Channel 0 did not count past the channel n-bit mode limit.
1 : SET
Channel 0 counted past the channel n-bit mode limit.
End of enumeration elements list.
C1IOVFI : Channel 1 Intermediate Overflow Interrupt Flag.
bits : 11 - 11 (1 bit)
Enumeration:
0 : NOT_SET
Channel 1 did not count past the channel n-bit mode limit.
1 : SET
Channel 1 counted past the channel n-bit mode limit.
End of enumeration elements list.
C2IOVFI : Channel 2 Intermediate Overflow Interrupt Flag.
bits : 12 - 12 (1 bit)
Enumeration:
0 : NOT_SET
Channel 2 did not count past the channel n-bit mode limit.
1 : SET
Channel 2 counted past the channel n-bit mode limit.
End of enumeration elements list.
C3IOVFI : Channel 3 Intermediate Overflow Interrupt Flag.
bits : 13 - 13 (1 bit)
Enumeration:
0 : NOT_SET
Channel 3 did not count past the channel n-bit mode limit.
1 : SET
Channel 3 counted past the channel n-bit mode limit.
End of enumeration elements list.
C4IOVFI : Channel 4 Intermediate Overflow Interrupt Flag.
bits : 14 - 14 (1 bit)
Enumeration:
0 : NOT_SET
Channel 4 did not count past the channel n-bit mode limit.
1 : SET
Channel 4 counted past the channel n-bit mode limit.
End of enumeration elements list.
C5IOVFI : Channel 5 Intermediate Overflow Interrupt Flag.
bits : 15 - 15 (1 bit)
Enumeration:
0 : NOT_SET
Channel 5 did not count past the channel n-bit mode limit.
1 : SET
Channel 5 counted past the channel n-bit mode limit.
End of enumeration elements list.
Module Counter/Timer
address_offset : 0x1B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : Counter/Timer.
bits : 0 - 15 (16 bit)
Module Upper Limit
address_offset : 0x1C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LIMIT : Upper Limit.
bits : 0 - 15 (16 bit)
Module Upper Limit Update Value
address_offset : 0x1D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LIMITUPD : Module Upper Limit Update Value.
bits : 0 - 15 (16 bit)
Phase Delay Time
address_offset : 0x1E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTIMEX : X Phase Delay Time.
bits : 0 - 7 (8 bit)
DTIMEY : Y Phase Delay Time.
bits : 8 - 15 (8 bit)
Channel Compare Value
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCAPV : Channel Compare Value.
bits : 0 - 17 (18 bit)
DMA Transfer Target
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTARGET : DMA Transfer Target.
bits : 0 - 31 (32 bit)
access : write-only
Channel Compare Update Value
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCAPVUPD : Channel Compare Update Value.
bits : 0 - 17 (18 bit)
Channel Capture/Compare Mode
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COSEL : Channel Output Function Select.
bits : 0 - 1 (2 bit)
Enumeration:
0 : TOGGLE_OUTPUT
Toggle the channel output at the next capture/compare, overflow, or intermediate event.
1 : SET_OUTPUT
Set the channel output at the next capture/compare, overflow, or intermediate event.
2 : CLEAR_OUTPUT
Clear the output at the next capture/compare, overflow, or intermediate event.
3 : NO_CHANGE
Capture/Compare, overflow, or intermediate events do not control the output state.
End of enumeration elements list.
PWMMD : PWM N-Bit Mode.
bits : 2 - 5 (4 bit)
DIFGEN : Differential Signal Generator Enable.
bits : 6 - 6 (1 bit)
Enumeration:
0 : DISABLED
Disable the differential signal generator. The channel will output a single non-differential output.
1 : ENABLED
Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH).
End of enumeration elements list.
CMD : Channel Operating Mode.
bits : 8 - 10 (3 bit)
Enumeration:
0 : EDGE_PWM
Configure the channel for edge-aligned PWM mode.
1 : CENTER_ALIGNED_PWM
Configure the channel for center-aligned PWM mode.
2 : HF_SQUARE_WAVE
Configure the channel for high-frequency/square-wave mode.
3 : TIMER_CAPTURE
Configure the channel for timer/capture mode.
4 : N_BIT_PWM
Configure the channel for n-bit edge-aligned PWM mode.
End of enumeration elements list.
Channel Capture/Compare Control
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUTST : Channel Output State.
bits : 0 - 0 (1 bit)
Enumeration:
0 : LOW
The channel output state is low.
1 : HIGH
The channel output state is high.
End of enumeration elements list.
CPCAPEN : Positive Edge Input Capture Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable positive-edge input capture.
1 : ENABLED
Enable positive-edge input capture.
End of enumeration elements list.
CNCAPEN : Negative Edge Input Capture Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
Disable negative-edge input capture.
1 : ENABLED
Enable negative-edge input capture.
End of enumeration elements list.
CUPDCF : Channel Register Update Complete Flag.
bits : 3 - 3 (1 bit)
Enumeration:
0 : NOT_SET
A EPCA channel register update completed or is not pending.
1 : SET
A EPCA channel register update has not completed and is still pending.
End of enumeration elements list.
YPHST : Differential Y Phase State.
bits : 5 - 5 (1 bit)
Enumeration:
0 : LOW
Set the Y Phase output state to low.
1 : HIGH
Set the Y Phase output state to high.
End of enumeration elements list.
ACTIVEPH : Active Channel Select.
bits : 6 - 6 (1 bit)
Enumeration:
0 : YACTIVE
The Y Phase is active and X Phase is inactive.
1 : XACTIVE
The X Phase is active and Y Phase is inactive.
End of enumeration elements list.
XPHST : Differential X Phase State.
bits : 7 - 7 (1 bit)
Enumeration:
0 : LOW
Set the X Phase output state to low.
1 : HIGH
Set the X Phase output state to high.
End of enumeration elements list.
CCIEN : Capture/Compare Interrupt Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : DISABLED
Disable the channel capture/compare interrupt.
1 : ENABLED
Enable the channel capture/compare interrupt.
End of enumeration elements list.
CCDEN : Capture/Compare DMA Request Enable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : DISABLED
Do not request DMA data when a channel capture/compare event occurs.
1 : ENABLED
Request DMA data when a channel capture/compare event occurs.
End of enumeration elements list.
CCSEN : Capture/Compare Synchronization Signal Enable.
bits : 10 - 10 (1 bit)
Enumeration:
0 : DISABLED
Do not send a synchronization signal when a channel capture/compare event occurs.
1 : ENABLED
Send a synchronization signal when a channel capture/compare event occurs.
End of enumeration elements list.
CIOVFIEN : Intermediate Overflow Interrupt Enable.
bits : 11 - 11 (1 bit)
Enumeration:
0 : DISABLED
Disable the channel intermediate overflow interrupt.
1 : ENABLED
Enable the channel intermediate overflow interrupt.
End of enumeration elements list.
CIOVFDEN : Intermediate Overflow DMA Request Enable.
bits : 12 - 12 (1 bit)
Enumeration:
0 : DISABLED
Do not request DMA data when a channel intermediate overflow event occurs.
1 : ENABLED
Request DMA data when a channel intermediate overflow event occurs.
End of enumeration elements list.
CIOVFSEN : Intermediate Overflow Synchronization Signal Enable.
bits : 13 - 13 (1 bit)
Enumeration:
0 : DISABLED
Do not send a synchronization signal when a channel intermediate overflow event occurs.
1 : ENABLED
Send a synchronization signal when a channel intermediate overflow occurs.
End of enumeration elements list.
Channel Compare Value
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCAPV : Channel Compare Value.
bits : 0 - 17 (18 bit)
Channel Compare Update Value
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCAPVUPD : Channel Compare Update Value.
bits : 0 - 17 (18 bit)
Channel Capture/Compare Mode
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COSEL : Channel Output Function Select.
bits : 0 - 1 (2 bit)
Enumeration:
0 : TOGGLE_OUTPUT
Toggle the channel output at the next capture/compare, overflow, or intermediate event.
1 : SET_OUTPUT
Set the channel output at the next capture/compare, overflow, or intermediate event.
2 : CLEAR_OUTPUT
Clear the output at the next capture/compare, overflow, or intermediate event.
3 : NO_CHANGE
Capture/Compare, overflow, or intermediate events do not control the output state.
End of enumeration elements list.
PWMMD : PWM N-Bit Mode.
bits : 2 - 5 (4 bit)
DIFGEN : Differential Signal Generator Enable.
bits : 6 - 6 (1 bit)
Enumeration:
0 : DISABLED
Disable the differential signal generator. The channel will output a single non-differential output.
1 : ENABLED
Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH).
End of enumeration elements list.
CMD : Channel Operating Mode.
bits : 8 - 10 (3 bit)
Enumeration:
0 : EDGE_PWM
Configure the channel for edge-aligned PWM mode.
1 : CENTER_ALIGNED_PWM
Configure the channel for center-aligned PWM mode.
2 : HF_SQUARE_WAVE
Configure the channel for high-frequency/square-wave mode.
3 : TIMER_CAPTURE
Configure the channel for timer/capture mode.
4 : N_BIT_PWM
Configure the channel for n-bit edge-aligned PWM mode.
End of enumeration elements list.
Channel Capture/Compare Control
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUTST : Channel Output State.
bits : 0 - 0 (1 bit)
Enumeration:
0 : LOW
The channel output state is low.
1 : HIGH
The channel output state is high.
End of enumeration elements list.
CPCAPEN : Positive Edge Input Capture Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable positive-edge input capture.
1 : ENABLED
Enable positive-edge input capture.
End of enumeration elements list.
CNCAPEN : Negative Edge Input Capture Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
Disable negative-edge input capture.
1 : ENABLED
Enable negative-edge input capture.
End of enumeration elements list.
CUPDCF : Channel Register Update Complete Flag.
bits : 3 - 3 (1 bit)
Enumeration:
0 : NOT_SET
A EPCA channel register update completed or is not pending.
1 : SET
A EPCA channel register update has not completed and is still pending.
End of enumeration elements list.
YPHST : Differential Y Phase State.
bits : 5 - 5 (1 bit)
Enumeration:
0 : LOW
Set the Y Phase output state to low.
1 : HIGH
Set the Y Phase output state to high.
End of enumeration elements list.
ACTIVEPH : Active Channel Select.
bits : 6 - 6 (1 bit)
Enumeration:
0 : YACTIVE
The Y Phase is active and X Phase is inactive.
1 : XACTIVE
The X Phase is active and Y Phase is inactive.
End of enumeration elements list.
XPHST : Differential X Phase State.
bits : 7 - 7 (1 bit)
Enumeration:
0 : LOW
Set the X Phase output state to low.
1 : HIGH
Set the X Phase output state to high.
End of enumeration elements list.
CCIEN : Capture/Compare Interrupt Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : DISABLED
Disable the channel capture/compare interrupt.
1 : ENABLED
Enable the channel capture/compare interrupt.
End of enumeration elements list.
CCDEN : Capture/Compare DMA Request Enable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : DISABLED
Do not request DMA data when a channel capture/compare event occurs.
1 : ENABLED
Request DMA data when a channel capture/compare event occurs.
End of enumeration elements list.
CCSEN : Capture/Compare Synchronization Signal Enable.
bits : 10 - 10 (1 bit)
Enumeration:
0 : DISABLED
Do not send a synchronization signal when a channel capture/compare event occurs.
1 : ENABLED
Send a synchronization signal when a channel capture/compare event occurs.
End of enumeration elements list.
CIOVFIEN : Intermediate Overflow Interrupt Enable.
bits : 11 - 11 (1 bit)
Enumeration:
0 : DISABLED
Disable the channel intermediate overflow interrupt.
1 : ENABLED
Enable the channel intermediate overflow interrupt.
End of enumeration elements list.
CIOVFDEN : Intermediate Overflow DMA Request Enable.
bits : 12 - 12 (1 bit)
Enumeration:
0 : DISABLED
Do not request DMA data when a channel intermediate overflow event occurs.
1 : ENABLED
Request DMA data when a channel intermediate overflow event occurs.
End of enumeration elements list.
CIOVFSEN : Intermediate Overflow Synchronization Signal Enable.
bits : 13 - 13 (1 bit)
Enumeration:
0 : DISABLED
Do not send a synchronization signal when a channel intermediate overflow event occurs.
1 : ENABLED
Send a synchronization signal when a channel intermediate overflow occurs.
End of enumeration elements list.
Channel Compare Value
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCAPV : Channel Compare Value.
bits : 0 - 17 (18 bit)
Channel Compare Update Value
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCAPVUPD : Channel Compare Update Value.
bits : 0 - 17 (18 bit)
Channel Capture/Compare Mode
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COSEL : Channel Output Function Select.
bits : 0 - 1 (2 bit)
Enumeration:
0 : TOGGLE_OUTPUT
Toggle the channel output at the next capture/compare, overflow, or intermediate event.
1 : SET_OUTPUT
Set the channel output at the next capture/compare, overflow, or intermediate event.
2 : CLEAR_OUTPUT
Clear the output at the next capture/compare, overflow, or intermediate event.
3 : NO_CHANGE
Capture/Compare, overflow, or intermediate events do not control the output state.
End of enumeration elements list.
PWMMD : PWM N-Bit Mode.
bits : 2 - 5 (4 bit)
DIFGEN : Differential Signal Generator Enable.
bits : 6 - 6 (1 bit)
Enumeration:
0 : DISABLED
Disable the differential signal generator. The channel will output a single non-differential output.
1 : ENABLED
Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH).
End of enumeration elements list.
CMD : Channel Operating Mode.
bits : 8 - 10 (3 bit)
Enumeration:
0 : EDGE_PWM
Configure the channel for edge-aligned PWM mode.
1 : CENTER_ALIGNED_PWM
Configure the channel for center-aligned PWM mode.
2 : HF_SQUARE_WAVE
Configure the channel for high-frequency/square-wave mode.
3 : TIMER_CAPTURE
Configure the channel for timer/capture mode.
4 : N_BIT_PWM
Configure the channel for n-bit edge-aligned PWM mode.
End of enumeration elements list.
Channel Capture/Compare Control
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUTST : Channel Output State.
bits : 0 - 0 (1 bit)
Enumeration:
0 : LOW
The channel output state is low.
1 : HIGH
The channel output state is high.
End of enumeration elements list.
CPCAPEN : Positive Edge Input Capture Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable positive-edge input capture.
1 : ENABLED
Enable positive-edge input capture.
End of enumeration elements list.
CNCAPEN : Negative Edge Input Capture Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
Disable negative-edge input capture.
1 : ENABLED
Enable negative-edge input capture.
End of enumeration elements list.
CUPDCF : Channel Register Update Complete Flag.
bits : 3 - 3 (1 bit)
Enumeration:
0 : NOT_SET
A EPCA channel register update completed or is not pending.
1 : SET
A EPCA channel register update has not completed and is still pending.
End of enumeration elements list.
YPHST : Differential Y Phase State.
bits : 5 - 5 (1 bit)
Enumeration:
0 : LOW
Set the Y Phase output state to low.
1 : HIGH
Set the Y Phase output state to high.
End of enumeration elements list.
ACTIVEPH : Active Channel Select.
bits : 6 - 6 (1 bit)
Enumeration:
0 : YACTIVE
The Y Phase is active and X Phase is inactive.
1 : XACTIVE
The X Phase is active and Y Phase is inactive.
End of enumeration elements list.
XPHST : Differential X Phase State.
bits : 7 - 7 (1 bit)
Enumeration:
0 : LOW
Set the X Phase output state to low.
1 : HIGH
Set the X Phase output state to high.
End of enumeration elements list.
CCIEN : Capture/Compare Interrupt Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : DISABLED
Disable the channel capture/compare interrupt.
1 : ENABLED
Enable the channel capture/compare interrupt.
End of enumeration elements list.
CCDEN : Capture/Compare DMA Request Enable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : DISABLED
Do not request DMA data when a channel capture/compare event occurs.
1 : ENABLED
Request DMA data when a channel capture/compare event occurs.
End of enumeration elements list.
CCSEN : Capture/Compare Synchronization Signal Enable.
bits : 10 - 10 (1 bit)
Enumeration:
0 : DISABLED
Do not send a synchronization signal when a channel capture/compare event occurs.
1 : ENABLED
Send a synchronization signal when a channel capture/compare event occurs.
End of enumeration elements list.
CIOVFIEN : Intermediate Overflow Interrupt Enable.
bits : 11 - 11 (1 bit)
Enumeration:
0 : DISABLED
Disable the channel intermediate overflow interrupt.
1 : ENABLED
Enable the channel intermediate overflow interrupt.
End of enumeration elements list.
CIOVFDEN : Intermediate Overflow DMA Request Enable.
bits : 12 - 12 (1 bit)
Enumeration:
0 : DISABLED
Do not request DMA data when a channel intermediate overflow event occurs.
1 : ENABLED
Request DMA data when a channel intermediate overflow event occurs.
End of enumeration elements list.
CIOVFSEN : Intermediate Overflow Synchronization Signal Enable.
bits : 13 - 13 (1 bit)
Enumeration:
0 : DISABLED
Do not send a synchronization signal when a channel intermediate overflow event occurs.
1 : ENABLED
Send a synchronization signal when a channel intermediate overflow occurs.
End of enumeration elements list.
Channel Compare Value
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCAPV : Channel Compare Value.
bits : 0 - 17 (18 bit)
Channel Compare Update Value
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCAPVUPD : Channel Compare Update Value.
bits : 0 - 17 (18 bit)
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