Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected
Transmit Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSGEN : DFS Generator Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
Disable the internal DFS generator.
1 : ENABLED
Enable the internal DFS generator.
End of enumeration elements list.
FSSEN : DFS Synchronize Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
The internal DFS generator starts immediately when FSGEN is set to 1.
1 : ENABLED
Synchronize the rising edge of the internally generated WS signal from the DFS generator to the rising edge of the external WS input signal.
End of enumeration elements list.
DDIS : Transmit Delay Disable.
bits : 5 - 5 (1 bit)
Enumeration:
0 : INACTIVE
The first data bit is sent on the second or later rising edge of SCK after WS changes.
1 : ACTIVE
The first data bit is sent on the first rising edge of SCK after WS changes.
End of enumeration elements list.
FSDEL : Transmit Initial Phase Delay.
bits : 6 - 13 (8 bit)
FSSRCSEL : Transmit Frame Sync Source Select.
bits : 14 - 14 (1 bit)
Enumeration:
0 : FSIN_EXT
The word select or frame sync is input from the WS pin.
1 : FSIN_INT
The word select or frame sync is input from the internal DFS generator.
End of enumeration elements list.
FILLSEL : Transmit Data Fill Select.
bits : 15 - 16 (2 bit)
Enumeration:
0 : ZEROS
Send zeros during unused bit cycles.
1 : ONES
Send ones during unused bit cycles.
2 : SIGN
Send the sign bit of the current sample (MSB-first format) or last sample (LSB-first format) during unused bit cycles.
3 : RANDOM
Send pseudo-random data generated by an 8-bit LFSR during unused bit cycles.
End of enumeration elements list.
JSEL : Transmit Data Justification Select.
bits : 17 - 17 (1 bit)
Enumeration:
0 : LEFT
Use left-justified or I2S-style formats.
1 : RIGHT
Use right-justified format.
End of enumeration elements list.
FSINVEN : Transmit WS Inversion Enable.
bits : 20 - 20 (1 bit)
Enumeration:
0 : DISABLED
Don't invert the WS signal. Use this setting for I2S format.
1 : ENABLED
Invert the WS signal.
End of enumeration elements list.
SCLKINVEN : Transmit SCK Inversion Enable.
bits : 21 - 21 (1 bit)
Enumeration:
0 : DISABLED
Do not invert the transmitter bit clock.
1 : ENABLED
Invert the transmitter bit clock.
End of enumeration elements list.
ORDER : Transmit Order.
bits : 22 - 22 (1 bit)
Enumeration:
0 : LEFT_RIGHT
Left sample transmitted first, right sample transmitted second. Use this setting for I2S format.
1 : RIGHT_LEFT
Right sample transmitted first, left sample transmitted second.
End of enumeration elements list.
MBSEL : Transmit Mono Bit-Width Select.
bits : 24 - 26 (3 bit)
Enumeration:
0 : 8BITS
8 bits are sent per mono sample.
1 : 9BITS
9 bits are sent per mono sample.
2 : 16BITS
16 bits are sent per mono sample.
3 : 24BITS
24 bits are sent per mono sample.
4 : 32BITS
32 bits are sent per mono sample.
End of enumeration elements list.
TXEN : Transmitter Enable.
bits : 29 - 29 (1 bit)
Enumeration:
0 : DISABLED
Disable the I2S transmitter.
1 : ENABLED
Enable the I2S transmitter.
End of enumeration elements list.
Transmit Mode
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CYCLE : Transmit Clock Cycle Select.
bits : 0 - 11 (12 bit)
START : Transmit Start Control.
bits : 12 - 19 (8 bit)
SLOTS : Transmit Drive Select.
bits : 20 - 24 (5 bit)
DEDIS : Transmit Drive Early Disable.
bits : 25 - 25 (1 bit)
Enumeration:
0 : INACTIVE
Drive the output during every cycle of the transmitter's assigned slot(s), including the last clock cycle.
1 : ACTIVE
Drive the output for every cycle of the transmitter's assigned slot(s), except for the last clock cycle of the last slot.
End of enumeration elements list.
DIMD : Transmit Drive Inactive Mode.
bits : 26 - 26 (1 bit)
Enumeration:
0 : ZERO
Drive zero on the data output pin during non-active slots.
1 : HIGH_Z
Don't drive the data output pin. The data output pin is tristated.
End of enumeration elements list.
TDMEN : Transmit Time Division Multiplexing Enable.
bits : 27 - 27 (1 bit)
Enumeration:
0 : DISABLED
Disable the time division multiplexing (TDM) feature.
1 : ENABLED
Enable the time division multiplexing (TDM) feature.
End of enumeration elements list.
Frame Sync Duty Cycle
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSLOW : Frame Sync Low Time.
bits : 0 - 15 (16 bit)
FSHIGH : Frame Sync High Time.
bits : 16 - 31 (16 bit)
Receive Control
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSDEL : Receive Initial Phase Delay.
bits : 0 - 7 (8 bit)
JSEL : Receive Data Justification.
bits : 8 - 8 (1 bit)
Enumeration:
0 : LEFT
Use left-justified or I2S-style formats.
1 : RIGHT
Use right-justified format.
End of enumeration elements list.
DDIS : Receive Delay Disable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : INACTIVE
The first data bit is captured on the second or later rising edge of SCK after WS changes.
1 : ACTIVE
The first data bit is captured by the receiver on the first rising edge of SCK after WS changes.
End of enumeration elements list.
FSINVEN : Receive WS Inversion Enable.
bits : 11 - 11 (1 bit)
Enumeration:
0 : DISABLED
Don't invert the WS signal. Use this setting for I2S format.
1 : ENABLED
Invert the WS signal.
End of enumeration elements list.
SCLKINVEN : Receive SCK Inversion Enable.
bits : 12 - 12 (1 bit)
Enumeration:
0 : DISABLED
Do not invert the receiver bit clock.
1 : ENABLED
Invert the receiver bit clock.
End of enumeration elements list.
ORDER : Receive Order.
bits : 13 - 13 (1 bit)
Enumeration:
0 : LEFT_RIGHT
Left sample received first, right sample received second. Use this setting for I2S format.
1 : RIGHT_LEFT
Right sample received first, left sample received second.
End of enumeration elements list.
MBSEL : Receive Mono Bit-Width Select.
bits : 15 - 17 (3 bit)
Enumeration:
0 : 8BITS
8 bits are received per mono sample.
1 : 9BITS
9 bits are received per mono sample.
2 : 16BITS
16 bits are received per mono sample.
3 : 24BITS
24 bits are received per mono sample.
4 : 32BITS
32 bits are received per mono sample.
End of enumeration elements list.
FSSRCSEL : Receive Frame Sync Source Select.
bits : 20 - 20 (1 bit)
Enumeration:
0 : FSIN_EXT
The word select or frame sync is input from the WS pin.
1 : FSIN_INT
The word select or frame sync is input from the internal DFS generator.
End of enumeration elements list.
RXEN : Receive Enable.
bits : 21 - 21 (1 bit)
Enumeration:
0 : DISABLED
Disable the I2S receiver.
1 : ENABLED
Enable the I2S receiver.
End of enumeration elements list.
Receive Mode
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CYCLE : Receive Clock Cycle Select.
bits : 0 - 11 (12 bit)
START : Receive Start Control.
bits : 12 - 19 (8 bit)
SLOTS : Receive Drive Select.
bits : 20 - 25 (6 bit)
TDMEN : Receive Time Division Multiplexing Enable.
bits : 27 - 27 (1 bit)
Enumeration:
0 : DISABLED
Disable the time division multiplexing (TDM) feature.
1 : ENABLED
Enable the time division multiplexing (TDM) feature.
End of enumeration elements list.
Clock Control
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTDIV : Clock Divider Integer Value.
bits : 0 - 9 (10 bit)
FRACDIV : Clock Divider Fractional Value.
bits : 10 - 17 (8 bit)
DUTYMD : Duty Cycle Adjustment Mode.
bits : 18 - 18 (1 bit)
Enumeration:
0 : MORE
When the division is fractional, the clock high time will be greater than 50% (by half of the source clock period).
1 : LESS
When the division is fractional, the clock low time will be greater than 50% (by half of the source clock period).
End of enumeration elements list.
CLKUPD : Clock Divider Update.
bits : 19 - 19 (1 bit)
access : write-only
Enumeration:
1 : UPDATE
Update the clock divider with new values of INTDIV, FRACDIV, and DIVEN.
End of enumeration elements list.
DIVEN : Clock Divider Enable.
bits : 20 - 20 (1 bit)
Enumeration:
0 : DISABLED
Disable the clock divider.
1 : ENABLED
Enable the clock divider.
End of enumeration elements list.
TXCLKSEL : Transmit Clock Select.
bits : 21 - 21 (1 bit)
Enumeration:
0 : INTERNAL
The I2S transmitter is clocked from the internal clock divider.
1 : EXTERNAL
The I2S transmitter is clocked from the SCK pin.
End of enumeration elements list.
RXCLKSEL : Receive Clock Select.
bits : 22 - 22 (1 bit)
Enumeration:
0 : INTERNAL
The I2S receiver is clocked from the internal clock divider.
1 : EXTERNAL
The I2S receiver is clocked from the SCK pin.
End of enumeration elements list.
RESET : I2S Module Reset.
bits : 23 - 23 (1 bit)
access : write-only
Enumeration:
1 : ACTIVE
Reset the I2S module.
End of enumeration elements list.
RXCLKEN : Receive Clock Enable.
bits : 24 - 24 (1 bit)
Enumeration:
0 : DISABLED
Disable the I2S receiver clock.
1 : ENABLED
Enable the I2S receiver clock.
End of enumeration elements list.
TXCLKEN : Transmit Clock Enable.
bits : 25 - 25 (1 bit)
Enumeration:
0 : DISABLED
Disable the I2S transmitter clock.
1 : ENABLED
Enable the I2S transmitter clock.
End of enumeration elements list.
RXSCLKMD : Receive SCK Mode.
bits : 26 - 26 (1 bit)
Enumeration:
0 : SCK_OUTPUT
The I2S receiver SCK signal is an output.
1 : SCK_INPUT
The I2S receiver SCK signal is an input.
End of enumeration elements list.
TXSCLKMD : Transmit SCK Mode.
bits : 27 - 27 (1 bit)
Enumeration:
0 : SCK_OUTPUT
The I2S transmitter SCK signal is an output.
1 : SCK_INPUT
The I2S transmitter SCK signal is an input.
End of enumeration elements list.
Transmit Data FIFO
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXFIFO : Transmit Data FIFO.
bits : 0 - 31 (32 bit)
access : write-only
Receive Data FIFO
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXFIFO : Receive Data FIFO.
bits : 0 - 31 (32 bit)
access : read-only
FIFO Status
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXFIFONUM : Transmit FIFO Status.
bits : 0 - 3 (4 bit)
access : read-only
RXFIFONUM : Receive FIFO Status.
bits : 16 - 19 (4 bit)
access : read-only
FIFO Control
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXFIFOWM : Transmit FIFO Low Watermark.
bits : 0 - 3 (4 bit)
RXFIFOWM : Receive FIFO High Watermark.
bits : 16 - 19 (4 bit)
TXFIFOFL : Transmit FIFO Flush.
bits : 21 - 21 (1 bit)
access : write-only
Enumeration:
1 : SET
Flush the I2S transmitter FIFO.
End of enumeration elements list.
RXFIFOFL : Receive FIFO Flush.
bits : 22 - 22 (1 bit)
access : write-only
Enumeration:
1 : SET
Flush the I2S receiver FIFO.
End of enumeration elements list.
Interrupt Control
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXUFIEN : Transmit Underflow Interrupt Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
Disable the transmit underflow interrupt.
1 : ENABLED
Enable the transmit underflow interrupt.
End of enumeration elements list.
RXOFIEN : Receive Overflow Interrupt Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable the receive overflow interrupt.
1 : ENABLED
Enable the receive overflow interrupt.
End of enumeration elements list.
TXLWMIEN : Transmit FIFO Low Watermark Interrupt Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
Disable the transmit FIFO low watermark interrupt.
1 : ENABLED
Enable the transmit FIFO low watermark interrupt.
End of enumeration elements list.
RXHWMIEN : Receive FIFO High Watermark Interrupt Enable.
bits : 3 - 3 (1 bit)
Enumeration:
0 : DISABLED
Disable the receive FIFO high watermark interrupt.
1 : ENABLED
Enable the receive FIFO high watermark interrupt.
End of enumeration elements list.
Module Status
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXUFI : Transmit Underflow Interrupt Flag.
bits : 0 - 0 (1 bit)
Enumeration:
0 : NOT_SET
A transmit underflow has not occurred.
1 : SET
A transmit underflow occurred.
End of enumeration elements list.
RXOFI : Receive Overflow Interrupt Flag.
bits : 1 - 1 (1 bit)
Enumeration:
0 : NOT_SET
A receive overflow has not occurred.
1 : SET
A receive overflow occurred.
End of enumeration elements list.
TXLWMI : Transmit FIFO Low Watermark Interrupt Flag.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
Transmit FIFO level is above the low watermark.
1 : SET
Transmit FIFO level is at or below the low watermark.
End of enumeration elements list.
RXHWMI : Receive FIFO High Watermark Interrupt Flag.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
Receive FIFO level is below the high watermark.
1 : SET
Receive FIFO level is at or above the high watermark.
End of enumeration elements list.
CDBUSYF : Clock Divider Busy Flag.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : NOT_BUSY
The divider is not busy and an update is not pending.
1 : BUSY
The divider is busy and an update is pending.
End of enumeration elements list.
CDSTS : Clock Divider Counter Status.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : RUNNING
Divided clock output is running.
1 : HALTED
Divided clock output is halted.
End of enumeration elements list.
TXCLKSELRF : Transmit Clock Select Ready Flag.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The transmit clock is not synchronized.
1 : SET
The transmit clock is synchronized and the transmitter is ready to send data.
End of enumeration elements list.
RXCLKSELRF : Receive Clock Select Ready Flag.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The receive clock is not synchronized.
1 : SET
The receive clock is synchronized and the receiver is ready to accept data.
End of enumeration elements list.
TXCLKENRF : Transmit Clock Enable Ready Flag.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The transmit clock is not synchronized.
1 : SET
The transmit clock is synchronized and the transmitter is ready to send data.
End of enumeration elements list.
RXCLKENRF : Receive Clock Enable Ready Flag.
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The receive clock is not synchronized.
1 : SET
The receive clock is synchronized and the receiver is ready to accept data.
End of enumeration elements list.
DMA Control
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDMAEN : Transmit DMA Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
Disable transmitter DMA data requests.
1 : ENABLED
Enable transmitter DMA data requests.
End of enumeration elements list.
RXDMAEN : Receive DMA Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable receiver DMA data transfer requests.
1 : ENABLED
Enable receiver DMA data transfer requests.
End of enumeration elements list.
TXDMABMD : Transmit DMA Burst Mode.
bits : 2 - 2 (1 bit)
Enumeration:
0 : ONE_WORD
The transmitter transmits one word at a time. Whenever there is any room in the transmit FIFO, a single word burst DMA data request is generated.
1 : FOUR_WORDS
The transmitter transmits four words at a time. Whenever the FIFO depth drops below five, a DMA burst request is generated for four words.
End of enumeration elements list.
RXDMABMD : Receive DMA Burst Mode.
bits : 3 - 3 (1 bit)
Enumeration:
0 : ONE_WORD
The receiver receives one word at a time. Whenever there is at least one word in the receive FIFO, a single word burst DMA request is generated.
1 : FOUR_WORDS
The receiver receives four words at a time. Whenever the FIFO depth rises above three, a DMA burst request is generated for four words.
End of enumeration elements list.
Debug Control
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDBGHEN : I2S Transmit DMA Debug Halt Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
Transmit DMA requests continue while the core is debug mode.
1 : ENABLED
Transmit DMA requests stop while the core is debug mode.
End of enumeration elements list.
RXDBGHEN : I2S Receive DMA Debug Halt Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Receive DMA requests continue while the core is debug mode.
1 : ENABLED
Receive DMA requests stop while the core is debug mode.
End of enumeration elements list.
TXDBGMD : I2S Transmit Debug Mode.
bits : 2 - 2 (1 bit)
Enumeration:
0 : RUN
The clock to the I2S transmitter is active in debug mode.
1 : HALT
The clock to the I2S transmitter is not active in debug mode. The clock divider keeps running and the clock will be disabled when two samples are ready to be sent by the transmitter.
End of enumeration elements list.
RXDBGMD : I2S Receive Debug Mode.
bits : 3 - 3 (1 bit)
Enumeration:
0 : RUN
The clock to the I2S receiver is active in debug mode.
1 : HALT
The clock to the I2S receiver is not active in debug mode. The clock divider keeps running and the clock will be disabled when two samples are captured in the receiver.
End of enumeration elements list.
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