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LOCK_0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected

Registers

KEY

PERIPHLOCK0

PERIPHLOCK1


KEY

Security Key
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEY KEY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : Peripheral Lock Mask Key.
bits : 0 - 7 (8 bit)

Enumeration:

0 : LOCKED

PERIPHLOCK registers are locked and no valid values have been written to KEY.

1 : INTERMEDIATE

PERIPHLOCK registers are locked and the first valid value (0xA5) has been written to KEY.

2 : UNLOCKED

PERIPHLOCK registers are unlocked. Any subsequent writes to KEY will lock the interface.

End of enumeration elements list.


PERIPHLOCK0

Peripheral Lock Control 0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERIPHLOCK0 PERIPHLOCK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USARTL SPIL I2CL PCAL TIMERL SARADCL SSGL CMPL CSL EMIFL AESL CRCL RTCL CLKRSTL VMONL IDACL DMACTRLL DMAXBARL LPTL VREFL I2SL PLLL EXTOSCL VREGL LPOSCL EVREGL IVCL

USARTL : USART/UART Module Lock Enable.
bits : 0 - 0 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the USART0, USART1, UART0, and UART1 Module registers.

1 : LOCKED

Lock the USART0, USART1, UART0, and UART1 Module registers (bits can still be read).

End of enumeration elements list.

SPIL : SPI Module Lock Enable.
bits : 1 - 1 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the SPI0, SPI1, and SPI2 Module registers.

1 : LOCKED

Lock the SPI0, SPI1, and SPI2 Module registers (bits can still be read).

End of enumeration elements list.

I2CL : I2C Module Lock Enable.
bits : 2 - 2 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the I2C0 and I2C1 Module registers.

1 : LOCKED

Lock the I2C0 and I2C1 Module registers (bits can still be read).

End of enumeration elements list.

PCAL : PCA Module Lock Enable.
bits : 3 - 3 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the EPCA0, PCA0, and PCA1 Module registers.

1 : LOCKED

Lock the EPCA0, PCA0, and PCA1 Module registers (bits can still be read).

End of enumeration elements list.

TIMERL : Timer Module Lock Enable.
bits : 4 - 4 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the TIMER0 and TIMER1 Module registers.

1 : LOCKED

Lock the TIMER0 and TIMER1 Module registers (bits can still be read).

End of enumeration elements list.

SARADCL : SARADC Module Lock Enable.
bits : 6 - 6 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the SARADC0 and SARADC1 Module registers.

1 : LOCKED

Lock the SARADC0 and SARADC1 Module registers (bits can still be read).

End of enumeration elements list.

SSGL : SSG Module Lock Enable.
bits : 7 - 7 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the SSG0 Module registers.

1 : LOCKED

Lock the SSG0 Module registers (bits can still be read).

End of enumeration elements list.

CMPL : Comparator Module Lock Enable.
bits : 8 - 8 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the Comparator 0 and Comparator 1 Module registers.

1 : LOCKED

Lock the Comparator 0 and Comparator 1 Module registers (bits can still be read).

End of enumeration elements list.

CSL : Capacitive Sensing Module Lock Enable.
bits : 9 - 9 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the Capacitive Sensing (CAPSENSE0) Module registers.

1 : LOCKED

Lock the Capacitive Sensing (CAPSENSE0) Module registers (bits can still be read).

End of enumeration elements list.

EMIFL : EMIF Module Lock Enable.
bits : 10 - 10 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the External Memory Interface (EMIF0) Module registers.

1 : LOCKED

Lock the External Memory Interface (EMIF0) Module registers (bits can still be read).

End of enumeration elements list.

AESL : AES Module Lock Enable.
bits : 11 - 11 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the AES0 Module registers.

1 : LOCKED

Lock the AES0 Module registers (bits can still be read).

End of enumeration elements list.

CRCL : CRC Module Lock Enable.
bits : 12 - 12 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the CRC0 Module registers.

1 : LOCKED

Lock the CRC0 Module registers (bits can still be read).

End of enumeration elements list.

RTCL : RTC Module Lock Enable.
bits : 13 - 13 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the RTC0 Module registers.

1 : LOCKED

Lock the RTC0 Module registers (bits can still be read).

End of enumeration elements list.

CLKRSTL : Clock Control and Reset Sources Lock Enable.
bits : 14 - 14 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the Clock Control (CLKCTRL) and Reset Sources (RSTSRC) Module registers.

1 : LOCKED

Lock the Clock Control (CLKCTRL) and Reset Sources (RSTSRC) Module registers (bits can still be read).

End of enumeration elements list.

VMONL : Voltage Supply Monitor Module Lock Enable.
bits : 15 - 15 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the Voltage Supply Monitor (VMON0) Module registers.

1 : LOCKED

Lock the Voltage Supply Monitor (VMON0) Module registers (bits can still be read).

End of enumeration elements list.

IDACL : IDAC Module Lock Enable.
bits : 16 - 16 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the IDAC0 and IDAC1 Module registers.

1 : LOCKED

Lock the IDAC0 and IDAC1 Module registers (bits can still be read).

End of enumeration elements list.

DMACTRLL : DMA Controller Module Lock Enable.
bits : 17 - 17 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the DMA Controller (DMACTRL0) Module registers.

1 : LOCKED

Lock the DMA Controller (DMACTRL0) Module registers (bits can still be read).

End of enumeration elements list.

DMAXBARL : DMA Crossbar Module Lock Enable.
bits : 18 - 18 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the DMA Crossbar (DMAXBAR0) Module registers.

1 : LOCKED

Lock the DMA Crossbar (DMAXBAR0) Module registers (bits can still be read).

End of enumeration elements list.

LPTL : Low Power Timer Module Lock Enable.
bits : 19 - 19 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the Low Power Timer (LPTIMER0) Module registers.

1 : LOCKED

Lock the Low Power Timer (LPTIMER0) Module registers (bits can still be read).

End of enumeration elements list.

VREFL : Voltage Reference Module Lock Enable.
bits : 20 - 20 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the Voltage Reference (VREF0) Module registers.

1 : LOCKED

Lock the Voltage Reference (VREF0) Module registers (bits can still be read).

End of enumeration elements list.

I2SL : I2S Module Lock Enable.
bits : 21 - 21 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the I2S0 Module registers.

1 : LOCKED

Lock the I2S0 Module registers (bits can still be read).

End of enumeration elements list.

PLLL : PLL Module Lock Enable.
bits : 22 - 22 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the PLL0 Module registers.

1 : LOCKED

Lock the PLL0 Module registers (bits can still be read).

End of enumeration elements list.

EXTOSCL : External Oscillator Module Lock Enable.
bits : 23 - 23 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the External Oscillator (EXTOSC0) Module registers.

1 : LOCKED

Lock the External Oscillator (EXTOSC0) Module registers (bits can still be read).

End of enumeration elements list.

VREGL : Voltage Regulator Module Lock Enable.
bits : 24 - 24 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the Voltage Regulator (VREG0) Module registers.

1 : LOCKED

Lock the Voltage Regulator (VREG0) Module registers (bits can still be read).

End of enumeration elements list.

LPOSCL : Low Power Oscillator Lock Enable.
bits : 25 - 25 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the Low Power Oscillator (LPOSC0) Module registers.

1 : LOCKED

Lock the Low Power Oscillator (LPOSC0) Module registers (bits can still be read).

End of enumeration elements list.

EVREGL : External Regulator Module Lock Enable.
bits : 26 - 26 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the External Regulator (EXTVREG0) Module registers.

1 : LOCKED

Lock the External Regulator (EXTVREG0) Module registers (bits can still be read).

End of enumeration elements list.

IVCL : IVC Module Lock Enable.
bits : 28 - 28 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the IVC0 Module registers.

1 : LOCKED

Lock the IVC0 Module registers (bits can still be read).

End of enumeration elements list.


PERIPHLOCK1

Peripheral Lock Control 1
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERIPHLOCK1 PERIPHLOCK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMUL

PMUL : PMU Module Lock Enable.
bits : 0 - 0 (1 bit)

Enumeration:

0 : UNLOCKED

Unlock the PMU Module registers.

1 : LOCKED

Lock the PMU Module registers (bits can still be read).

End of enumeration elements list.



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