Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected
Input/Output Data
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Input/Output Data.
bits : 0 - 31 (32 bit)
Module Control
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFRQI : Receive FIFO Read Request Interrupt Flag.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The RX FIFO has fewer bytes than the level defined by RFTH.
1 : SET
The RX FIFO has equal or more bytes than the level defined by RFTH.
End of enumeration elements list.
RFORI : Receive FIFO Overrun Interrupt Flag.
bits : 1 - 1 (1 bit)
Enumeration:
0 : NOT_SET
Read: A receive FIFO overrun has not occurred. Write: Clear the flag.
1 : SET
Read: A receive FIFO overrun occurred. Write: Force a receive overrun interrupt.
End of enumeration elements list.
TFRQI : Transmit FIFO Write Request Interrupt Flag.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The TX FIFO has fewer bytes than the level defined by TFTH.
1 : SET
The TX FIFO has equal or more bytes than the level defined by TFTH.
End of enumeration elements list.
TFORI : Transmit FIFO Overrun Interrupt Flag.
bits : 3 - 3 (1 bit)
Enumeration:
0 : NOT_SET
Read: A transmit FIFO overrun has not occurred. Write: Clear the flag.
1 : SET
Read: A transmit FIFO overrun occurred. Write: Force a transmit overrun interrupt.
End of enumeration elements list.
SLVSELI : Slave Selected Interrupt Flag.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The slave select signal (NSS) is not active.
1 : SET
The slave select signal (NSS) is active.
End of enumeration elements list.
MDFI : Mode Fault Interrupt Flag.
bits : 5 - 5 (1 bit)
Enumeration:
0 : NOT_SET
Read: A master mode collision is not detected. Write: Clear the flag.
1 : SET
Read: A master mode collision occurred. Write: Force a mode fault interrupt.
End of enumeration elements list.
URI : Underrun Interrupt Flag.
bits : 6 - 6 (1 bit)
Enumeration:
0 : NOT_SET
Read: A data transfer is still in progress. Write: Clear the flag.
1 : SET
Read: The transmit FIFO and shift register are empty and the data transfer has ended. Write: Force an underrun interrupt.
End of enumeration elements list.
SREI : Shift Register Empty Interrupt Flag.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
There is data still present in the transmit FIFO.
1 : SET
All data has been transferred out of the shift register and there is no data waiting in the transmit FIFO.
End of enumeration elements list.
RFILI : Illegal Receive FIFO Access Interrupt Flag.
bits : 8 - 8 (1 bit)
Enumeration:
0 : NOT_SET
Read: An illegal write or read of the receive FIFO has not occurred. Write: Clear the flag.
1 : SET
Read: An illegal write or read of the receive FIFO occurred. Write: Force an illegal receive access interrupt.
End of enumeration elements list.
TFILI : Illegal Transmit FIFO Access Interrupt Flag.
bits : 9 - 9 (1 bit)
Enumeration:
0 : NOT_SET
Read: An illegal write or read of the transmit FIFO has not occurred. Write: Clear the flag.
1 : SET
Read: An illegal write or read of the transmit FIFO occurred. Write: Force an illegal transmit access interrupt.
End of enumeration elements list.
NSSSTS : NSS Instantaneous Pin Status.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : LOW
NSS is currently a logic low.
1 : HIGH
NSS is currently a logic high.
End of enumeration elements list.
BUSYF : SPI Busy.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The SPI is not busy and a transfer is not in progress.
1 : SET
The SPI is currently busy and a transfer is in progress.
End of enumeration elements list.
RFCNT : Receive FIFO Counter.
bits : 16 - 19 (4 bit)
access : read-only
TFCNT : Transmit FIFO Counter.
bits : 20 - 23 (4 bit)
access : read-only
DBGMD : SPI Debug Mode.
bits : 24 - 24 (1 bit)
Enumeration:
0 : RUN
The SPI module will continue to operate while the core is halted in debug mode.
1 : HALT
A debug breakpoint will cause the SPI module to halt.
End of enumeration elements list.
Module Configuration
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFRQIEN : Receive FIFO Read Request Interrupt Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
Disable the receive FIFO request interrupt.
1 : ENABLED
Enable the receive FIFO request interrupt.
End of enumeration elements list.
RFORIEN : Receive FIFO Overrun Interrupt Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable the receive FIFO overrun interrupt.
1 : ENABLED
Enable the receive FIFO overrun interrupt.
End of enumeration elements list.
TFRQIEN : Transmit FIFO Write Request Interrupt Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DISABLED
Disable the transmit FIFO data request interrupt.
1 : ENABLED
Enable the transmit FIFO data request interrupt.
End of enumeration elements list.
TFORIEN : Transmit FIFO Overrun Interrupt Enable.
bits : 3 - 3 (1 bit)
Enumeration:
0 : DISABLED
Disable the transmit FIFO overrun interrupt.
1 : ENABLED
Enable the transmit FIFO overrun interrupt.
End of enumeration elements list.
SLVSELIEN : Slave Selected Interrupt Enable.
bits : 4 - 4 (1 bit)
Enumeration:
0 : DISABLED
Disable the slave select interrupt.
1 : ENABLED
Enable the slave select interrupt.
End of enumeration elements list.
MDFIEN : Mode Fault Interrupt Enable.
bits : 5 - 5 (1 bit)
Enumeration:
0 : DISABLED
Disable the mode fault interrupt.
1 : ENABLED
Enable the mode fault interrupt.
End of enumeration elements list.
URIEN : Underrun Interrupt Enable.
bits : 6 - 6 (1 bit)
Enumeration:
0 : DISABLED
Disable the underrun interrupt.
1 : ENABLED
Enable the underrun interrupt.
End of enumeration elements list.
SREIEN : Shift Register Empty Interrupt Enable.
bits : 7 - 7 (1 bit)
Enumeration:
0 : DISABLED
Disable the shift register empty interrupt.
1 : ENABLED
Enable the shift register empty interrupt.
End of enumeration elements list.
SPIEN : SPI Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : DISABLED
Disable the SPI.
1 : ENABLED
Enable the SPI.
End of enumeration elements list.
MSTEN : Master Mode Enable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : DISABLED
Operate in slave mode.
1 : ENABLED
Operate in master mode.
End of enumeration elements list.
CLKPOL : SPI Clock Polarity.
bits : 10 - 10 (1 bit)
Enumeration:
0 : LOW
The SCK line is low in the idle state.
1 : HIGH
The SCK line is high in the idle state.
End of enumeration elements list.
CLKPHA : SPI Clock Phase.
bits : 11 - 11 (1 bit)
Enumeration:
0 : CENTER
The first edge of SCK is the sample edge (center of data bit).
1 : EDGE
The first edge of SCK is the shift edge (edge of data bit).
End of enumeration elements list.
NSSPOL : Slave Select Polarity Select.
bits : 12 - 12 (1 bit)
Enumeration:
0 : LOW
NSS is active low.
1 : HIGH
NSS is active high.
End of enumeration elements list.
DDIRSEL : Data Direction Select.
bits : 13 - 13 (1 bit)
Enumeration:
0 : MSB_FIRST
Data will be shifted MSB first.
1 : LSB_FIRST
Data will be shifted LSB first.
End of enumeration elements list.
NSSMD : Slave Select Mode.
bits : 14 - 15 (2 bit)
Enumeration:
0 : 3_WIRE_MASTER_SLAVE
3-wire Slave or 3-wire Master.
1 : 4_WIRE_SLAVE
4-wire slave (NSS input). This setting can also be used for multi-master configurations.
2 : 4_WIRE_MASTER_NSS_LOW
4-wire master with NSS low (NSS output).
3 : 4_WIRE_MASTER_NSS_HIGH
4-wire master with NSS high (NSS output).
End of enumeration elements list.
RFTH : Receive FIFO Threshold.
bits : 16 - 17 (2 bit)
Enumeration:
0 : ONE
A DMA / RFRQ request asserts when >= 1 FIFO slot is filled.
1 : TWO
A DMA / RFRQ request asserts when >= 2 FIFO slots are filled.
2 : FOUR
A DMA / RFRQ request asserts when >= 4 FIFO slots are filled.
3 : FULL
A DMA / RFRQ request asserts when all FIFO slots are filled.
End of enumeration elements list.
TFTH : Transmit FIFO Threshold.
bits : 18 - 19 (2 bit)
Enumeration:
0 : ONE
A DMA / TFRQ request asserts when >= 1 FIFO slot is empty.
1 : TWO
A DMA / TFRQ request asserts when >= 2 FIFO slots are empty.
2 : FOUR
A DMA / TFRQ request asserts when >= 4 FIFO slots are empty.
3 : EMPTY
A DMA / TFRQ request asserts when all FIFO slots are empty.
End of enumeration elements list.
DSIZE : Data Size.
bits : 20 - 23 (4 bit)
DMAEN : DMA Enable.
bits : 24 - 24 (1 bit)
Enumeration:
0 : DISABLED
Disable DMA requests.
1 : ENABLED
Enable DMA requests when the transmit buffer is empty or the receive buffer is full.
End of enumeration elements list.
RFIFOFL : Receive FIFO Flush.
bits : 29 - 29 (1 bit)
Enumeration:
1 : SET
Flush the receive FIFO.
End of enumeration elements list.
TFIFOFL : Transmit FIFO Flush.
bits : 30 - 30 (1 bit)
Enumeration:
1 : SET
Flush the transmit FIFO.
End of enumeration elements list.
RESET : Module Soft Reset.
bits : 31 - 31 (1 bit)
Enumeration:
0 : INACTIVE
SPI module is not in soft reset.
1 : ACTIVE
SPI module is in soft reset and some of the module bits cannot be accessed until this bit is cleared to 0 by hardware.
End of enumeration elements list.
Module Clock Rate Control
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIV : Clock Divider.
bits : 0 - 15 (16 bit)
FIFO Status
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFRPTR : Receive FIFO Read Pointer.
bits : 0 - 3 (4 bit)
access : read-only
RFWPTR : Receive FIFO Write Pointer.
bits : 4 - 7 (4 bit)
access : read-only
TFRPTR : Transmit FIFO Read Pointer.
bits : 8 - 11 (4 bit)
access : read-only
TFWPTR : Transmit FIFO Write Pointer.
bits : 12 - 15 (4 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.