Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected
Module Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSTA : AES Transfer Start.
bits : 0 - 0 (1 bit)
Enumeration:
1 : START
Start the AES operation.
End of enumeration elements list.
KEYCPEN : Key Capture Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable key capture.
1 : ENABLED
Enable key capture.
End of enumeration elements list.
EDMD : Encryption/Decryption Mode.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DECRYPT
AES module performs a decryption operation
1 : ENCRYPT
AES module performs an encryption operation.
End of enumeration elements list.
SWMDEN : Software Mode Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : DISABLED
Disable software mode.
1 : ENABLED
Enable software mode.
End of enumeration elements list.
BEN : Bypass AES Operation Enable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : DISABLED
Do not bypass AES operations.
1 : ENABLED
Bypass AES operations.
End of enumeration elements list.
XOREN : XOR Enable.
bits : 10 - 11 (2 bit)
Enumeration:
0 : XOR_DISABLED
Disable the XOR paths.
1 : XOR_INPUT
Enable the XOR input path, disable the XOR output path.
2 : XOR_OUTPUT
Disable the XOR input path, enable the XOR output path.
End of enumeration elements list.
HCTREN : Hardware Counter Mode Enable.
bits : 12 - 12 (1 bit)
Enumeration:
0 : DISABLED
Disable hardware counter mode.
1 : ENABLED
Enable hardware counter mode.
End of enumeration elements list.
HCBCEN : Hardware Cipher-Block Chaining Mode Enable.
bits : 13 - 13 (1 bit)
Enumeration:
0 : DISABLED
Disable hardware cipher-block chaining (CBC) mode.
1 : ENABLED
Enable hardware cipher-block chaining (CBC) mode.
End of enumeration elements list.
KEYSIZE : Keystore Size Select.
bits : 16 - 17 (2 bit)
Enumeration:
0 : KEY128
Key is composed of 128 bits.
1 : KEY192
Key is composed of 192 bits.
2 : KEY256
Key is composed of 256 bits.
End of enumeration elements list.
ERRIEN : Error Interrupt Enable.
bits : 24 - 24 (1 bit)
Enumeration:
0 : DISABLED
Disable the error interrupt.
1 : ENABLED
Enable the error interrupt. An interrupt is generated when the Input/Output Data FIFO Overun (DORI), Input/Output Data FIFO Underun (DURI), or XOR Data FIFO Overrun (XORI) flags are set.
End of enumeration elements list.
OCIEN : Operation Complete Interrupt Enable.
bits : 25 - 25 (1 bit)
Enumeration:
0 : DISABLED
Disable the operation complete interrupt.
1 : ENABLED
Enable the operation complete interrupt. An interrupt is generated when the Operation Complete Interrupt (OCI) flag is set.
End of enumeration elements list.
DBGMD : AES Debug Mode.
bits : 30 - 30 (1 bit)
Enumeration:
0 : HALT
A debug breakpoint will cause the AES module to halt.
1 : RUN
The AES module will continue to operate while the core is halted in debug mode.
End of enumeration elements list.
RESET : Module Soft Reset.
bits : 31 - 31 (1 bit)
Enumeration:
0 : INACTIVE
AES module is not in soft reset.
1 : ACTIVE
AES module is in soft reset and none of the module bits can be accessed.
End of enumeration elements list.
Number of Blocks
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZE : Transfer Size.
bits : 0 - 10 (11 bit)
Module Status
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFIFOLVL : Input/Output Data FIFO Level.
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
0 : EMPTY
Input/Output data FIFO is empty.
1 : 1_BYTE
Input/Output data FIFO contains 1 byte.
2 : 2_BYTES
Input/Output data FIFO contains 2 bytes.
3 : 3_BYTES
Input/Output data FIFO contains 3 bytes.
4 : 4_BYTES
Input/Output data FIFO contains 4 bytes.
5 : 5_BYTES
Input/Output data FIFO contains 5 bytes.
6 : 6_BYTES
Input/Output data FIFO contains 6 bytes.
7 : 7_BYTES
Input/Output data FIFO contains 7 bytes.
8 : 8_BYTES
Input/Output data FIFO contains 8 bytes.
9 : 9_BYTES
Input/Output data FIFO contains 9 bytes.
10 : 10_BYTES
Input/Output data FIFO contains 10 bytes.
11 : 11_BYTES
Input/Output data FIFO contains 11 bytes.
12 : 12_BYTES
Input/Output data FIFO contains 12 bytes.
13 : 13_BYTES
Input/Output data FIFO contains 13 bytes.
14 : 14_BYTES
Input/Output data FIFO contains 14 bytes.
15 : 15_BYTES
Input/Output data FIFO contains 15 bytes.
16 : FULL
Input/Output data FIFO contains 16 bytes (full).
End of enumeration elements list.
XFIFOLVL : XOR Data FIFO Level.
bits : 8 - 12 (5 bit)
access : read-only
Enumeration:
0 : EMPTY
XOR data FIFO is empty.
1 : 1_BYTE
XOR data FIFO contains 1 byte.
2 : 2_BYTES
XOR data FIFO contains 2 bytes.
3 : 3_BYTES
XOR data FIFO contains 3 bytes.
4 : 4_BYTES
XOR data FIFO contains 4 bytes.
5 : 5_BYTES
XOR data FIFO contains 5 bytes.
6 : 6_BYTES
XOR data FIFO contains 6 bytes.
7 : 7_BYTES
XOR data FIFO contains 7 bytes.
8 : 8_BYTES
XOR data FIFO contains 8 bytes.
9 : 9_BYTES
XOR data FIFO contains 9 bytes.
10 : 10_BYTES
XOR data FIFO contains 10 bytes.
11 : 11_BYTES
XOR data FIFO contains 11 bytes.
12 : 12_BYTES
XOR data FIFO contains 12 bytes.
13 : 13_BYTES
XOR data FIFO contains 13 bytes.
14 : 14_BYTES
XOR data FIFO contains 14 bytes.
15 : 15_BYTES
XOR data FIFO contains 15 bytes.
16 : FULL
XOR data FIFO contains 16 bytes (full).
End of enumeration elements list.
BUSYF : Module Busy Flag.
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
AES module is not busy.
1 : SET
AES module is completing an operation.
End of enumeration elements list.
DURI : Input/Output Data FIFO Underrun Interrupt Flag.
bits : 28 - 28 (1 bit)
Enumeration:
0 : NOT_SET
No input/output data FIFO underrun.
1 : SET
An input/output data FIFO underrun has occurred.
End of enumeration elements list.
DORI : Input/Output Data FIFO Overrun Interrupt Flag.
bits : 29 - 29 (1 bit)
Enumeration:
0 : NOT_SET
No input/output data FIFO overrun.
1 : SET
An input/output data FIFO overrun has occurred.
End of enumeration elements list.
XORI : XOR Data FIFO Overrun Interrupt Flag.
bits : 30 - 30 (1 bit)
Enumeration:
0 : NOT_SET
No XOR data FIFO overrun.
1 : SET
An XOR data FIFO overrun has occurred.
End of enumeration elements list.
OCI : Operation Complete Interrupt Flag.
bits : 31 - 31 (1 bit)
Enumeration:
0 : NOT_SET
AES operation complete interrupt has not occurred.
1 : SET
AES operation complete interrupt occurred.
End of enumeration elements list.
Input/Output Data FIFO Access
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAFIFO : Input/Output Data FIFO Access.
bits : 0 - 31 (32 bit)
XOR Data FIFO Access
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XORFIFO : XOR Data FIFO Access.
bits : 0 - 31 (32 bit)
Hardware Key Word 0
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HWKEY0 : Hardware Key Word 0.
bits : 0 - 31 (32 bit)
Hardware Key Word 1
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HWKEY1 : Hardware Key Word 1.
bits : 0 - 31 (32 bit)
Hardware Key Word 2
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HWKEY2 : Hardware Key Word 2.
bits : 0 - 31 (32 bit)
Hardware Key Word 3
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HWKEY3 : Hardware Key Word 3.
bits : 0 - 31 (32 bit)
Hardware Key Word 4
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HWKEY4 : Hardware Key Word 4.
bits : 0 - 31 (32 bit)
Hardware Key Word 5
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HWKEY5 : Hardware Key Word 5.
bits : 0 - 31 (32 bit)
Hardware Key Word 6
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HWKEY6 : Hardware Key Word 6.
bits : 0 - 31 (32 bit)
Hardware Key Word 7
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HWKEY7 : Hardware Key Word 7.
bits : 0 - 31 (32 bit)
Hardware Counter Word 0
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HWCTR0 : Hardware Counter Word 0.
bits : 0 - 31 (32 bit)
Hardware Counter Word 1
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HWCTR1 : Hardware Counter Word 1.
bits : 0 - 31 (32 bit)
Hardware Counter Word 2
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HWCTR2 : Hardware Counter Word 2.
bits : 0 - 31 (32 bit)
Hardware Counter Word 3
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HWCTR3 : Hardware Counter Word 3.
bits : 0 - 31 (32 bit)
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