Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected
Configuration
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPDSTSF : Write Update Status Flag.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
An internal pulse counter register update is not in progress.
1 : SET
An internal pulse counter register update is in progress.
End of enumeration elements list.
DBGSEL : Debug Signal Select.
bits : 5 - 7 (3 bit)
Enumeration:
0 : NONE
No debug signals output.
1 : LCC0_LCC1
(LC Mode) DBG0 = CMP0OUT, DBG1 = CMP0OUT.
2 : LCC0_INT0
(LC Mode) DBG0 = CMP0OUT, DBG1 = INTEG0.
3 : LCC1_INT1
(LC Mode) DBG0 = CMP1OUT, DBG1 = INTEG1.
4 : INT0_INT1
(Any Mode) DBG0 = INTEG0 DBG1 = INTEG1.
5 : CMP0_CMP1
(Switch Mode) DBG0 = CMP0OUT, DBG1 = CMP0OUT.
6 : CMP0_INT0
(Switch Mode) DBG0 = CMP0OUT, DBG1 = INTEG0.
7 : CMP1_INT1
(Switch Mode) DBG0= CMP1OUT, DBG1 = INTEG1.
End of enumeration elements list.
FLQDEN : Flutter Quadrature-to-Dual Switch Enable.
bits : 24 - 24 (1 bit)
Enumeration:
0 : DISABLED
The pulse counter remains in quadrature mode during a flutter event.
1 : ENABLED
The pulse counter switches from quadrature mode to dual mode during a flutter event.
End of enumeration elements list.
FLSTPEN : Flutter Stop Enable.
bits : 25 - 25 (1 bit)
Enumeration:
0 : DISABLED
The pulse counter continues operating during a flutter event.
1 : ENABLED
The 24-bit counters stop counting during a flutter event.
End of enumeration elements list.
TOPMD : Topology Mode.
bits : 29 - 29 (1 bit)
Enumeration:
0 : SWITCH
Select the switch closure topology.
1 : LC
Select the LC resonant topology.
End of enumeration elements list.
PCMD : Pulse Counter Mode.
bits : 30 - 31 (2 bit)
Enumeration:
0 : DISABLED
Disable the pulse counter.
1 : SINGLE
Select single channel mode.
2 : DUAL
Select dual channel mode.
3 : QUADRATURE
Select quadrature mode.
End of enumeration elements list.
Control Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPLTH : Comparator Low Threshold.
bits : 15 - 16 (2 bit)
Enumeration:
0 : 32_PERCENT
Set the digital comparator low threshold to 32% of VIO.
1 : 36_PERCENT
Set the digital comparator low threshold to 36% of VIO.
2 : 40_PERCENT
Set the digital comparator low threshold to 40% of VIO.
3 : 44_PERCENT
Set the digital comparator low threshold to 44% of VIO.
End of enumeration elements list.
CMPHTH : Comparator High Threshold.
bits : 17 - 18 (2 bit)
Enumeration:
0 : 48_PERCENT
Set the digital comparator high threshold to 48% of VIO.
1 : 52_PERCENT
Set the digital comparator high threshold to 52% of VIO.
2 : 56_PERCENT
Set the digital comparator high threshold to 56% of VIO.
3 : 60_PERCENT
Set the digital comparator high threshold to 60% of VIO.
End of enumeration elements list.
CALMD : Automatic Calibration Mode.
bits : 19 - 19 (1 bit)
Enumeration:
0 : UNTIL_PASS
Continue to calibrate until a passing condition occurs.
1 : UNTIL_FAIL
Continue to calibrate until a failing condition occurs.
End of enumeration elements list.
CALPUMD : Automatic Calibration Pull-up Mode.
bits : 20 - 21 (2 bit)
Enumeration:
0 : FULL
Use full pull-up mode.
1 : SMALL
Use small pull-up mode.
2 : MEDIUM
Use medium pull-up mode.
3 : LARGE
Use large pull-up mode.
End of enumeration elements list.
FPUPEN : Force Continuous Pull-up Enable.
bits : 22 - 22 (1 bit)
Enumeration:
0 : DISABLED
Pull-ups are enabled automatically by hardware.
1 : ENABLED
Always enable the pull-ups.
End of enumeration elements list.
FPDNEN : Force Ground Input Enable.
bits : 23 - 23 (1 bit)
Enumeration:
0 : DISABLED
Disable input grounding.
1 : ENABLED
Enable input grounding. The IN0 and IN1 inputs are grounded.
End of enumeration elements list.
PUVAL : Pull-up Value.
bits : 24 - 28 (5 bit)
CALSEL : Automatic Calibration Input Select.
bits : 29 - 29 (1 bit)
Enumeration:
0 : IN0
Calibrate the IN0 input.
1 : IN1
Calibrate the IN1 input.
End of enumeration elements list.
CALRF : Calibration Result Flag.
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The automatic calibration operation did not succeed.
1 : SET
The automatic calibration operation succeeded.
End of enumeration elements list.
CALBUSYF : Calibration Busy Flag.
bits : 31 - 31 (1 bit)
Enumeration:
0 : NOT_SET
A calibration operation is not in progress.
1 : SET
A calibration operation is in progress. Hardware will clear this flag when the operation completes.
End of enumeration elements list.
LC Configuration
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEMD : LC Pulse Extension Mode.
bits : 0 - 1 (2 bit)
Enumeration:
0 : LOW
Stretch the LC comparator output low pulses by approximately 20 ns.
1 : HIGH
Stretch the LC comparator output high pulses by approximately 20 ns.
2 : NONE
No pulse extension.
End of enumeration elements list.
CMP0FTH : LC Comparator 0 Fine Threshold.
bits : 2 - 4 (3 bit)
CMP0CTH : LC Comparator 0 Coarse Threshold.
bits : 5 - 10 (6 bit)
CMP0THR : LC Comparator 0 Threshold Range.
bits : 11 - 11 (1 bit)
Enumeration:
0 : LOW
Set the comparator 0 threshold to the low range (0 V to VIO/8 in 48 steps).
1 : FULL
Set the comparator 0 threshold to a full range (0 V to VIO in 64 steps).
End of enumeration elements list.
CMP1FTH : LC Comparator 1 Fine Threshold.
bits : 12 - 14 (3 bit)
CMP1CTH : LC Comparator 1 Coarse Threshold.
bits : 15 - 20 (6 bit)
CMP1THR : LC Comparator 1 Threshold Range.
bits : 21 - 21 (1 bit)
Enumeration:
0 : LOW
Set the comparator 1 threshold to the low range (0 V to VIO/8 in 48 steps).
1 : FULL
Set the comparator 1 threshold to a full range (0 V to VIO in 64 steps).
End of enumeration elements list.
CMPLHYS : LC Comparator Low-side Hysteresis.
bits : 22 - 23 (2 bit)
Enumeration:
0 : 0_MV
Set both LC comparators to use 0 mV low-side hysteresis.
1 : 5_MV
Set both LC comparators to use 5 mV low-side hysteresis.
2 : 10_MV
Set both LC comparators to use 10 mV low-side hysteresis.
3 : 20_MV
Set both LC comparators to use 20 mV low-side hysteresis.
End of enumeration elements list.
CMPHHYS : LC Comparator High-side Hysteresis.
bits : 24 - 25 (2 bit)
Enumeration:
0 : 0_MV
Set both LC comparators to use 0 mV high-side hysteresis.
1 : 5_MV
Set both LC comparators to use 5 mV high-side hysteresis.
2 : 10_MV
Set both LC comparators to use 10 mV high-side hysteresis.
3 : 20_MV
Set both LC comparators to use 20 mV high-side hysteresis.
End of enumeration elements list.
CMPMD : LC Comparator Mode.
bits : 26 - 27 (2 bit)
Enumeration:
0 : 5_US
Mode 0 (slowest response time, lowest power consumption).
1 : 1_US
Mode 1.
2 : 400_NS
Mode 2.
3 : 200_NS
Mode 3 (fastest response time, highest power consumption).
End of enumeration elements list.
CMP0CNT1EN : LC Comparator 0 to Count 1 Enable.
bits : 28 - 28 (1 bit)
Enumeration:
0 : DISABLED
Use LC comparator 0 as an input to counter 0 and LC comparator 1 as an input to counter 1.
1 : ENABLED
Use LC comparator 0 as an input to both counter 0 and counter 1.
End of enumeration elements list.
FCMP0EN : Force LC Comparator 0 On Enable.
bits : 29 - 29 (1 bit)
Enumeration:
0 : DISABLED
Hardware automatically turns LC comparator 0 on and off.
1 : ENABLED
Force LC comparator 0 always on.
End of enumeration elements list.
FCMP1EN : Force LC Comparator 1 On Enable.
bits : 30 - 30 (1 bit)
Enumeration:
0 : DISABLED
Hardware automatically turns LC comparator 1 on and off.
1 : ENABLED
Force LC comparator 1 always on.
End of enumeration elements list.
Timing
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATE : Timing State.
bits : 0 - 2 (3 bit)
access : read-only
B0OEN : Bias 0 Offset Enable.
bits : 3 - 3 (1 bit)
Enumeration:
0 : DISABLED
The bias 0 pulse is a full width (minimum 2 RTC cycles).
1 : ENABLED
The bias 0 pulse is delayed 1/2 an RTC cycle and de-asserts 1/2 an RTC cycle early (minimum 3 RTC cycles).
End of enumeration elements list.
B1OEN : Bias 1 Offset Enable.
bits : 4 - 4 (1 bit)
Enumeration:
0 : DISABLED
The bias 1 pulse is a full width (minimum 2 RTC cycles).
1 : ENABLED
The bias 1 pulse is delayed 1/2 an RTC cycle and de-asserts 1/2 an RTC cycle early (minimum 3 RTC cycles).
End of enumeration elements list.
ZONED : Zone D Count.
bits : 9 - 11 (3 bit)
ZONEC : Zone C Count.
bits : 12 - 14 (3 bit)
ZONEB : Zone B Count.
bits : 15 - 17 (3 bit)
ZONEA : Zone A Count.
bits : 18 - 20 (3 bit)
ZONEP : Zone P Count.
bits : 21 - 23 (3 bit)
WAKEMD : LC Wake Mode.
bits : 24 - 26 (3 bit)
Enumeration:
0 : DISABLED
Disable wake up events.
1 : WZONEP
Wake or interrupt at the start of zone P.
2 : WZONEA
Wake or interrupt at the start of zone A.
3 : WZONEB
Wake or interrupt at the start of zone B.
4 : WZONEC
Wake or interrupt at the start of zone C.
5 : WZONED
Wake or interrupt at the start of zone D.
6 : WEND
Wake or interrupt at the end of the LC sequence.
7 : WKSTOP
Wake or interrupt at the end of the LC sequence and stop the sequencer when this event occurs.
End of enumeration elements list.
START : Sequencer Start.
bits : 27 - 27 (1 bit)
Enumeration:
0 : DISABLED
Do not start the sequencer.
1 : ENABLED
Start the sequencer.
End of enumeration elements list.
PERIOD : Pulse Counter Period.
bits : 28 - 31 (4 bit)
Enumeration:
0 : 4_CYCLES
Set the period to 4 RTC cycles.
1 : 8_CYCLES
Set the period to 8 RTC cycles.
2 : 16_CYCLES
Set the period to 16 RTC cycles.
3 : 32_CYCLES
Set the period to 32 RTC cycles.
4 : 64_CYCLES
Set the period to 64 RTC cycles.
5 : 128_CYCLES
Set the period to 128 RTC cycles.
6 : 256_CYCLES
Set the period to 256 RTC cycles.
7 : 512_CYCLES
Set the period to 512 RTC cycles.
8 : 1024_CYCLES
Set the period to 1024 RTC cycles.
9 : 2048_CYCLES
Set the period to 2048 RTC cycles.
10 : 4096_CYCLES
Set the period to 4096 RTC cycles.
14 : SINGLE_SAMPLE
Set the module to single sample mode and disable the period counter after the next completion of the sequencer. In this mode, firmware must start each sample by setting FLCSEN to 1.
15 : CONSECUTIVE_SAMPLE
Set the module to consecutive sample mode and disable the period counter. After completing zone D, the timing engine will jump directly to zone A, skipping both the W and P zones.
End of enumeration elements list.
LC Mode
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATRKEN : Automatic Tracking Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : DISABLED
Disable automatic tracking.
1 : ENABLED
Enable automatic tracking. A new MAX value of any size will increase both the MAX and MIN by 1, and a new MIN value of any size will decrease both the MAX and MIN by 1.
End of enumeration elements list.
ACDEN : Automatic Center Discriminator Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : DISABLED
Disable automatic center discriminator mode. Firmware must set the CD0 and CD1 fields.
1 : ENABLED
Enable automatic center discriminator mode. Hardware will keep the CD0 and CD1 fields centered between MAX and MIN.
End of enumeration elements list.
LCD0HYS : LC Discriminator 0 Digital Hysterisis.
bits : 2 - 3 (2 bit)
Enumeration:
0 : ZERO
A high-to-low transition occurs if LCCOUNT0 is less than CD0.
1 : MINUS1
A high-to-low transition occurs if LCCOUNT0 is less than CD0 - 1.
2 : MINUS2
A high-to-low transition occurs if LCCOUNT0 is less than CD0 - 2.
3 : MINUS3
A high-to-low transition occurs if LCCOUNT0 is less than CD0 - 3.
End of enumeration elements list.
LCD1HYS : LC Discriminator 1 Digital Hysterisis.
bits : 4 - 5 (2 bit)
Enumeration:
0 : ZERO
A high-to-low transition occurs if LCCOUNT1 is less than CD1.
1 : MINUS1
A high-to-low transition occurs if LCCOUNT1 is less than CD1 - 1.
2 : MINUS2
A high-to-low transition occurs if LCCOUNT1 is less than CD1 - 2.
3 : MINUS3
A high-to-low transition occurs if LCCOUNT1 is less than CD1 - 3.
End of enumeration elements list.
C0ZONE : Counter 0 Active Zone Select.
bits : 6 - 7 (2 bit)
Enumeration:
0 : ZONEA
Select zone A as the active zone for counter 0 (LCIN0 input).
1 : ZONEB
Select zone B as the active zone for counter 0 (LCIN0 input).
2 : ZONEC
Select zone C as the active zone for counter 0 (LCIN0 input).
3 : ZONED
Select zone D as the active zone for counter 0 (LCIN0 input).
End of enumeration elements list.
C1ZONE : Counter 1 Active Zone Select.
bits : 8 - 9 (2 bit)
Enumeration:
0 : ZONEA
Select zone A as the active zone for counter 1 (LCIN1 input).
1 : ZONEB
Select zone B as the active zone for counter 1 (LCIN1 input).
2 : ZONEC
Select zone C as the active zone for counter 1 (LCIN1 input).
3 : ZONED
Select zone D as the active zone for counter 1 (LCIN1 input).
End of enumeration elements list.
P0ZONE : Pulse 0 Active Zone Select.
bits : 10 - 11 (2 bit)
Enumeration:
0 : DISABLED
Disable the pulse 0 output (LCPUL0).
1 : C_ONLY
Select zone C only as the active zone for the pulse 0 output (LCPUL0).
2 : A_ONLY
Select zone A only as the active zone for the pulse 0 output (LCPUL0).
3 : A_AND_C
Select zones A and C as the active zones for the pulse 0 output (LCPUL0).
End of enumeration elements list.
P1ZONE : Pulse 1 Active Zone Select.
bits : 12 - 13 (2 bit)
Enumeration:
0 : DISABLED
Disable the pulse 1 output (LCPUL1).
1 : C_ONLY
Select zone C only as the active zone for the pulse 1 output (LCPUL1).
2 : A_ONLY
Select zone A only as the active zone for the pulse 1 output (LCPUL1).
3 : A_AND_C
Select zones A and C as the active zones for the pulse 1 output (LCPUL1).
End of enumeration elements list.
PMD : LC Pulse Mode.
bits : 14 - 15 (2 bit)
Enumeration:
0 : DISABLED
Disable pulse mode.
1 : TOGGLE
Toggle at the start of zone A or zone C.
2 : PULSE_LOW
Set the pulse mode to idle high, pulse low.
3 : PULSE_HIGH
Set the pulse mode to idle low, pulse high.
End of enumeration elements list.
B0ZONECEN : Bias 0 Zone C Enable.
bits : 16 - 16 (1 bit)
Enumeration:
0 : DISABLED
Disable bias 0 during zone C.
1 : ENABLED
Enable bias 0 during zone C.
End of enumeration elements list.
B0ZONEBEN : Bias 0 Zone B Enable.
bits : 17 - 17 (1 bit)
Enumeration:
0 : DISABLED
Disable bias 0 during zone B.
1 : ENABLED
Enable bias 0 during zone B.
End of enumeration elements list.
B0ZONEAEN : Bias 0 Zone A Enable.
bits : 18 - 18 (1 bit)
Enumeration:
0 : DISABLED
Disable bias 0 during zone A.
1 : ENABLED
Enable bias 0 during zone A.
End of enumeration elements list.
B0ZONEPEN : Bias 0 Zone P Enable.
bits : 19 - 19 (1 bit)
Enumeration:
0 : DISABLED
Disable bias 0 during zone P.
1 : ENABLED
Enable bias 0 during zone P.
End of enumeration elements list.
B0POL : Bias 0 Polarity.
bits : 20 - 20 (1 bit)
Enumeration:
0 : PULSE_LOW
Set bias 0 to idle high, pulse low.
1 : PULSE_HIGH
Set bias 0 to idle low, pulse high.
End of enumeration elements list.
B1ZONECEN : Bias 1 Zone C Enable.
bits : 21 - 21 (1 bit)
Enumeration:
0 : DISABLED
Disable bias 1 during zone C.
1 : ENABLED
Enable bias 1 during zone C.
End of enumeration elements list.
B1ZONEBEN : Bias 1 Zone B Enable.
bits : 22 - 22 (1 bit)
Enumeration:
0 : DISABLED
Disable bias 1 during zone B.
1 : ENABLED
Enable bias 1 during zone B.
End of enumeration elements list.
B1ZONEAEN : Bias 1 Zone A Enable.
bits : 23 - 23 (1 bit)
Enumeration:
0 : DISABLED
Disable bias 1 during zone A.
1 : ENABLED
Enable bias 1 during zone A.
End of enumeration elements list.
B1ZONEPEN : Bias 1 Zone P Enable.
bits : 24 - 24 (1 bit)
Enumeration:
0 : DISABLED
Disable bias 1 during zone P.
1 : ENABLED
Enable bias 1 during zone P.
End of enumeration elements list.
B1POL : Bias 1 Polarity.
bits : 25 - 25 (1 bit)
Enumeration:
0 : PULSE_LOW
Set bias 1 to idle high, pulse low.
1 : PULSE_HIGH
Set bias 1 to idle low, pulse high.
End of enumeration elements list.
BMD : Bias Mode.
bits : 26 - 27 (2 bit)
Enumeration:
0 : MODE0
Disable the bias signals.
1 : MODE1
Use the bias signals externally only (LCBIAS0 and LCBIAS1 outputs).
2 : MODE2
Use the bias signals internally only.
3 : MODE3
Use the bias signals externally (LCBIAS0 and LCBIAS1 outputs) and internally.
End of enumeration elements list.
LCMD : LC Mode.
bits : 28 - 31 (4 bit)
Enumeration:
0 : MODE0
The LC pulse asserts throughout zone A or zone C with a single-ended comparator using the counter and discriminator.
1 : MODE1
The LC pulse asserts throughout zone A or zone C with differential comparators using the counter and discriminator.
2 : MODE2
The LC pulse asserts throughout zone A or zone C with a single-ended comparator sampling and holding at the end of the LC pulse.
3 : MODE3
The LC pulse asserts throughout zone A or zone C with differential comparators sampling and holding at the end of the LC pulse.
4 : MODE4
The LC pulse starts at the beginning of zone A or C and stops with the timer with a single-ended comparator using the counter and discriminator.
5 : MODE5
The LC pulse starts at the beginning of zone A or C and stops with the timer with differential comparators using the counter and discriminator.
6 : MODE6
The LC pulse starts at the beginning of zone A or C and stops with the timer with a single-ended comparator sampling and holding at the end of the LC pulse.
7 : MODE7
The LC pulse starts at the beginning of zone A or C and stops with the timer with differential comparators sampling and holding at the end of the LC pulse.
8 : MODE8
The LC pulse starts at beginning of zone A or C and stops with the rising edge of the external stop input (STOPx) with a single-ended comparator using the counter and discriminator.
9 : MODE9
The LC pulse starts at beginning of zone A or C and stops with the falling edge of the external stop input (STOPx) with single-ended comparators using the counter and discriminator.
10 : MODE10
The LC pulse starts at beginning of zone A or C and stops with the rising edge of the external stop input (STOPx) with a single-ended comparator sampling and holding at the end of the LC pulse.
11 : MODE11
The LC pulse starts at beginning of zone A or C and stops with the falling edge of the external stop input (STOPx) with single-ended comparators sampling and holding at the end of the LC pulse.
12 : MODE12
Do not generate a pulse with a single-ended comparator using the timer and discrimintor.
13 : MODE13
Do not generate a pulse with differential comparators using the timer and discrimintor.
14 : MODE14
Do not generate a pulse with a single-ended comparator sampling and holding at the end of the zone.
15 : MODE15
Do not genreate a pulse with differential comparators sampling and holding at the end of the zone.
End of enumeration elements list.
LC Clock Control
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKCYCLES : LC Oscillator Clock Cycles.
bits : 0 - 11 (12 bit)
access : read-only
CLKCAL : LC Oscillator Calibration Start.
bits : 12 - 12 (1 bit)
Enumeration:
0 : NOT_IN_PROGRESS
A calibration operation is not in progress.
1 : START
Start an oscillator calibration or a calibration operation is in progress.
End of enumeration elements list.
RELOAD : LC Oscillator Reload Value.
bits : 16 - 27 (12 bit)
LC Counter Limits
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MIN0 : LC Counter 0 Minimum Value.
bits : 0 - 7 (8 bit)
access : read-only
MAX0 : LC Counter 0 Maximum Value.
bits : 8 - 15 (8 bit)
access : read-only
MIN1 : LC Counter 1 Minimum Value.
bits : 16 - 23 (8 bit)
access : read-only
MAX1 : LC Counter 1 Maximum Value.
bits : 24 - 31 (8 bit)
access : read-only
LC Counters
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCCOUNT0 : LC Counter 0.
bits : 0 - 7 (8 bit)
access : read-only
CD0 : LC Counter 0 Discriminator.
bits : 8 - 15 (8 bit)
LCCOUNT1 : LC Counter 1.
bits : 16 - 23 (8 bit)
access : read-only
CD1 : LC Counter 1 Discriminator.
bits : 24 - 31 (8 bit)
Pulse Counter Debounce Configuration
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDBTH : Integrator Low Debounce.
bits : 0 - 7 (8 bit)
HDBTH : Integrator High Debounce.
bits : 8 - 15 (8 bit)
INTEGDCEN : PC Integrator Disconnect Enable.
bits : 16 - 16 (1 bit)
Enumeration:
0 : DISABLED
Connect integrator to 24 bit counter state machine logic.
1 : ENABLED
Disconnect the integrators from the IN0 and IN1 inputs.
End of enumeration elements list.
INTEG0 : PC Integrator 0 Output.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : LOW
The integrator 0 output is low.
1 : HIGH
The integrator 0 output is high.
End of enumeration elements list.
INTEG1 : PC Integrator 1 Output.
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : LOW
The integrator 1 output is low.
1 : HIGH
The integrator 1 output is high.
End of enumeration elements list.
Pulse Counter 0
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT0 : Pulse Counter 0.
bits : 0 - 23 (24 bit)
access : read-only
Pulse Counter 1
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT1 : Pulse Counter 1.
bits : 0 - 23 (24 bit)
access : read-only
Comparator 0
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP0 : Pulse Counter Comparator 0 Threshold.
bits : 0 - 23 (24 bit)
Pulse Counter Comparator 1 Threshold
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP1 : Pulse Counter Comparator 1 Threshold.
bits : 0 - 23 (24 bit)
Pulse Counter Status
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIRCHGI : Direction Change Interrupt Flag.
bits : 0 - 0 (1 bit)
Enumeration:
0 : NOT_SET
A direction change did not occur.
1 : SET
A direction change occurred.
End of enumeration elements list.
OVFI : Counter Overflow Interrupt Flag.
bits : 1 - 1 (1 bit)
Enumeration:
0 : NOT_SET
Neither of the counters overflowed.
1 : SET
One of the counters overflowed.
End of enumeration elements list.
CMP0I : Digital Comparator 0 Interrupt Flag.
bits : 2 - 2 (1 bit)
Enumeration:
0 : NOT_SET
A digital comparator 0 and counter 0 match did not occur.
1 : SET
A digital comparator 0 and counter 0 match occurred.
End of enumeration elements list.
CMP1I : Digital Comparator 1 Interrupt Flag.
bits : 3 - 3 (1 bit)
Enumeration:
0 : NOT_SET
A digital comparator 1 and counter 1 match did not occur.
1 : SET
A digital comparator 1 and counter 1 match occurred.
End of enumeration elements list.
TRANSI : Integrator Transition Interrupt Flag.
bits : 4 - 4 (1 bit)
Enumeration:
0 : NOT_SET
An integrator output transition did not occur.
1 : SET
An integrator output transition occurred.
End of enumeration elements list.
QERRI : Quadrature Error Interrupt Flag.
bits : 5 - 5 (1 bit)
Enumeration:
0 : NOT_SET
A quadrature error did not occur.
1 : SET
A quadrature error occurred.
End of enumeration elements list.
FLSTOPI : Flutter Stop Interrupt Flag.
bits : 6 - 6 (1 bit)
Enumeration:
0 : NOT_SET
A flutter detection end event did not occur.
1 : SET
A flutter detection end event occurred.
End of enumeration elements list.
FLSTARTI : Flutter Start Interrupt Flag.
bits : 7 - 7 (1 bit)
Enumeration:
0 : NOT_SET
A flutter detection start event did not occur.
1 : SET
A flutter detection start event occurred.
End of enumeration elements list.
DIRCHGIEN : Direction Change Interrupt Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : DISABLED
Disable direction change as an interrupt or wake up source.
1 : ENABLED
Enable direction change as an interrupt or wake up source.
End of enumeration elements list.
OVFIEN : Counter Overflow Interrupt Enable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : DISABLED
Disable counter overflows as an interrupt or wake up source.
1 : ENABLED
Enable counter overflows as an interrupt or wake up source.
End of enumeration elements list.
CMP0IEN : Digital Comparator 0 Interrupt Enable.
bits : 10 - 10 (1 bit)
Enumeration:
0 : DISABLED
Disable comparator 0 as an interrupt or wake up source.
1 : ENABLED
Enable comparator 0 as an interrupt or wake up source.
End of enumeration elements list.
CMP1IEN : Digital Comparator 1 Interrupt Enable.
bits : 11 - 11 (1 bit)
Enumeration:
0 : DISABLED
Disable comparator 1 as an interrupt or wake up source.
1 : ENABLED
Enable comparator 1 as an interrupt or wake up source.
End of enumeration elements list.
TRANSIEN : Integrator Transition Interrupt Enable.
bits : 12 - 12 (1 bit)
Enumeration:
0 : DISABLED
Disable integrator transitions as an interrupt or wake up source.
1 : ENABLED
Enable integrator transitions as an interrupt or wake up source.
End of enumeration elements list.
QERRIEN : Quadrature Error Interrupt Enable.
bits : 13 - 13 (1 bit)
Enumeration:
0 : DISABLED
Disable quadrature error as an interrupt or wake up source.
1 : ENABLED
Enable quadrature error as an interrupt or wake up source.
End of enumeration elements list.
FLSTOPIEN : Flutter Stop Interrupt Enable.
bits : 14 - 14 (1 bit)
Enumeration:
0 : DISABLED
Disable flutter detection end events as an interrupt or wake up source.
1 : ENABLED
Enable flutter detection end events as an interrupt or wake up source.
End of enumeration elements list.
FLSTARTIEN : Flutter Start Interrupt Enable.
bits : 15 - 15 (1 bit)
Enumeration:
0 : DISABLED
Disable flutter detection start events as an interrupt or wake up source.
1 : ENABLED
Enable flutter detection start events as an interrupt or wake up source.
End of enumeration elements list.
IN0 : Integrator 0 Output.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : LOW
The integrator 0 output is low.
1 : HIGH
The integrator 0 output is high.
End of enumeration elements list.
IN1 : Integrator 1 Output.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : LOW
The integrator 1 output is low.
1 : HIGH
The integrator 1 output is high.
End of enumeration elements list.
IN0PREV : Previous Integrator 0 Output.
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : LOW
The previous integrator 0 output was low.
1 : HIGH
The previous integrator 0 output was high.
End of enumeration elements list.
IN1PREV : Previous Integrator 1 Output.
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0 : LOW
The previous integrator 1 output was low.
1 : HIGH
The previous integrator 1 output was high.
End of enumeration elements list.
STATE : Pulse Counter State.
bits : 20 - 21 (2 bit)
access : read-only
Enumeration:
0 : ST0
The pulse counter is in state 0.
1 : ST1
The pulse counter is in state 1.
2 : ST2
The pulse counter is in state 2.
3 : ST3
The pulse counter is in state 3.
End of enumeration elements list.
DIRF : Direction Flag.
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : COUNTER_CLOCKWISE
The current direction is counter-clockwise.
1 : CLOCKWISE
The current direction is clockwise.
End of enumeration elements list.
FLF : Flutter Detected Flag.
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The switch operates normally.
1 : SET
A flutter event was detected.
End of enumeration elements list.
DIRHIST : Direction History .
bits : 24 - 27 (4 bit)
access : read-only
CMP0OUT : Comparator 0 Output.
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : LOW
The output of comparator 0 is low.
1 : HIGH
The output of comparator 0 is high.
End of enumeration elements list.
CMP1OUT : Comparator 1 Output.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : LOW
The output of comparator 1 is low.
1 : HIGH
The output of comparator1 is high.
End of enumeration elements list.
Calibration
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGOEN : Debug Output Enable.
bits : 14 - 14 (1 bit)
Enumeration:
0 : DISABLED
None
1 : ENABLED
None
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.